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am33xx: add ti814x specific register definitions

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Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Matt Porter 2013-03-15 10:07:06 +00:00 committed by Tom Rini
parent b2e682f7a0
commit 8b029f22a6
7 changed files with 71 additions and 21 deletions
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3
arch/arm/cpu/armv7/am33xx/sys_info.c
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@ -98,6 +98,9 @@ int print_cpuinfo(void)
case AM335X:
cpu_s = "AM335X";
break;
case TI81XX:
cpu_s = "TI81XX";
break;
default:
cpu_s = "Unknown cpu type";
break;

11
arch/arm/include/asm/arch-am33xx/cpu.h
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@ -42,9 +42,10 @@
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
/* cpu-id for AM33XX family */
/* cpu-id for AM33XX and TI81XX family */
#define AM335X 0xB944
#define DEVICE_ID 0x44E10600
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
/* This gives the status of the boot mode pins on the evm */
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
@ -52,9 +53,11 @@
/* Reset control */
#ifdef CONFIG_AM33XX
#define PRM_RSTCTRL 0x44E00F00
#define PRM_RSTST 0x44E00F08
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
#elif defined(CONFIG_TI814X)
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
#endif
#define PRM_RSTST (PRM_RSTCTRL + 8)
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232

21
arch/arm/include/asm/arch-am33xx/hardware.h
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@ -19,6 +19,7 @@
#ifndef __AM33XX_HARDWARE_H
#define __AM33XX_HARDWARE_H
#include <config.h>
#include <asm/arch/omap.h>
#ifdef CONFIG_AM33XX
#include <asm/arch/hardware_am33xx.h>
@ -26,8 +27,9 @@
#include <asm/arch/hardware_ti814x.h>
#endif
/* Module base addresses */
#define UART0_BASE 0x44E09000
/*
* Common hardware definitions
*/
/* DM Timer base addresses */
#define DM_TIMER0_BASE 0x4802C000
@ -42,21 +44,10 @@
/* GPIO Base address */
#define GPIO0_BASE 0x48032000
#define GPIO1_BASE 0x4804C000
#define GPIO2_BASE 0x481AC000
/* BCH Error Location Module */
#define ELM_BASE 0x48080000
/* Watchdog Timer */
#define WDT_BASE 0x44E35000
/* Control Module Base Address */
#define CTRL_BASE 0x44E10000
#define CTRL_DEVICE_BASE 0x44E10600
/* PRCM Base Address */
#define PRCM_BASE 0x44E00000
/* EMIF Base address */
#define EMIF4_0_CFG_BASE 0x4C000000
#define EMIF4_1_CFG_BASE 0x4D000000
@ -90,10 +81,6 @@
/* CPSW Config space */
#define CPSW_BASE 0x4A100000
#define CPSW_MDIO_BASE 0x4A101000
/* RTC base address */
#define RTC_BASE 0x44E3E000
/* OTG */
#define USB0_OTG_BASE 0x47401000

24
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
View File

@ -19,6 +19,24 @@
#ifndef __AM33XX_HARDWARE_AM33XX_H
#define __AM33XX_HARDWARE_AM33XX_H
/* Module base addresses */
/* UART Base Address */
#define UART0_BASE 0x44E09000
/* GPIO Base address */
#define GPIO2_BASE 0x481AC000
/* Watchdog Timer */
#define WDT_BASE 0x44E35000
/* Control Module Base Address */
#define CTRL_BASE 0x44E10000
#define CTRL_DEVICE_BASE 0x44E10600
/* PRCM Base Address */
#define PRCM_BASE 0x44E00000
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
@ -27,4 +45,10 @@
#define DDR_PHY_DATA_ADDR 0x44E120C8
#define DDR_DATA_REGS_NR 2
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A101000
/* RTC base address */
#define RTC_BASE 0x44E3E000
#endif /* __AM33XX_HARDWARE_AM33XX_H */

23
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
View File

@ -19,6 +19,23 @@
#ifndef __AM33XX_HARDWARE_TI814X_H
#define __AM33XX_HARDWARE_TI814X_H
/* Module base addresses */
/* UART Base Address */
#define UART0_BASE 0x48020000
/* Watchdog Timer */
#define WDT_BASE 0x481C7000
/* Control Module Base Address */
#define CTRL_BASE 0x48140000
/* PRCM Base Address */
#define PRCM_BASE 0x48180000
/* PLL Subsystem Base Address */
#define PLL_SUBSYS_BASE 0x481C5000
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x48140E0C
@ -27,4 +44,10 @@
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
#define DDR_DATA_REGS_NR 4
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A100800
/* RTC base address */
#define RTC_BASE 0x480C0000
#endif /* __AM33XX_HARDWARE_TI814X_H */

5
arch/arm/include/asm/arch-am33xx/omap.h
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@ -28,8 +28,13 @@
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
#ifdef CONFIG_AM33XX
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000
#elif defined(CONFIG_TI814X)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#endif
/* ROM code defines */
/* Boot device */

5
arch/arm/include/asm/arch-am33xx/spl.h
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@ -25,8 +25,13 @@
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
#ifdef CONFIG_AM33XX
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#elif defined(CONFIG_TI814X)
#define BOOT_DEVICE_MMC1 9
#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */
#endif
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_USBETH 68