global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG

Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>

arch/arm/mach-davinci/misc.c

@@ -27,7 +27,7 @@ int dram_init(void)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CFG_SYS_SDRAM_BASE,
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
 

arch/arm/mach-omap2/am33xx/board.c

@@ -73,7 +73,7 @@ int dram_init(void)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CFG_SYS_SDRAM_BASE,
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
 
@@ -521,7 +521,7 @@ void board_init_f(ulong dummy)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CFG_SYS_SDRAM_BASE,
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 }
 #endif
 

arch/arm/mach-omap2/sec-common.c

@@ -203,7 +203,7 @@ u32 get_sec_mem_start(void)
 			omap_sdram_size()
 #else
 			get_ram_size((void *)CFG_SYS_SDRAM_BASE,
-				     CONFIG_MAX_RAM_BANK_SIZE)
+				     CFG_MAX_RAM_BANK_SIZE)
 #endif
 			- sec_mem_size));
 	return sec_mem_start;

arch/arm/mach-orion5x/dram.c

@@ -39,7 +39,7 @@ int dram_init (void)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(long *) orion5x_sdram_bar(0),
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
 
@@ -51,7 +51,7 @@ int dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
 		gd->bd->bi_dram[i].size = get_ram_size(
 			(long *) (gd->bd->bi_dram[i].start),
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	}
 
 	return 0;

arch/arm/mach-orion5x/include/mach/orion5x.h

@@ -53,7 +53,7 @@
 #define MVCPU_WIN_ENABLE	ORION5X_WIN_ENABLE
 #define MVCPU_WIN_DISABLE	ORION5X_WIN_DISABLE
 
-#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
+#define CFG_MAX_RAM_BANK_SIZE		(64*1024*1024)
 
 /* include here SoC variants. 5181, 5281, 6183 should go here when
    adding support for them, and this comment should then be updated. */

board/phytec/phycore_am335x_r2/board.c

@@ -167,7 +167,7 @@ void sdram_init(void)
 
 	/* Detect memory physically present */
 	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
-				    CONFIG_MAX_RAM_BANK_SIZE);
+				    CFG_MAX_RAM_BANK_SIZE);
 
 	/* Reconfigure memory for actual detected size */
 	switch (gd->ram_size) {

board/ti/ks2_evm/board.c

@@ -47,7 +47,7 @@ int dram_init(void)
 	ddr3_size = ddr3_init();
 
 	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
-				    CONFIG_MAX_RAM_BANK_SIZE);
+				    CFG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
 	if (!(board_is_k2g_ice() || board_is_k2g_i1()))
 		aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);

include/configs/am43xx_evm.h

@@ -8,7 +8,7 @@
 #ifndef __CONFIG_AM43XX_EVM_H
 #define __CONFIG_AM43XX_EVM_H
 
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
 #define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>

include/configs/bur_am335x_common.h

@@ -19,7 +19,7 @@
 
 #endif /* CONFIG_DM */
 
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
 /* Timer information */
 #define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */

include/configs/cm_t43.h

@@ -8,7 +8,7 @@
 #ifndef __CONFIG_CM_T43_H
 #define __CONFIG_CM_T43_H
 
-#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2GB */
+#define CFG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2GB */
 #define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>

include/configs/da850evm.h

@@ -31,7 +31,7 @@
  */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 /* memtest start addr */
 
 /* memtest will be run on 16MB */

include/configs/draco.h

@@ -25,7 +25,7 @@
 	"led1=64,0,1\0"
 
  /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
 /* Default env settings */
 #define CFG_EXTRA_ENV_SETTINGS \

include/configs/etamin.h

@@ -67,7 +67,7 @@
 	"led5=63,0,1\0"
 
 /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
 
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120

include/configs/legoev3.h

@@ -27,7 +27,7 @@
  */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 
 /* memtest start addr */
 

include/configs/omapl138_lcdk.h

@@ -26,7 +26,7 @@
  */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 
 /* memtest start addr */
 

include/configs/pxm2.h

@@ -23,7 +23,7 @@
 	"led0=117,0,1\0" \
 
  /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 1GB */
 
 /* Use common default */
 

include/configs/rastaban.h

@@ -32,7 +32,7 @@
 	"led5=63,0,1\0"
 
  /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120

include/configs/rut.h

@@ -19,7 +19,7 @@
 #define DDR_PLL_FREQ	303
 
  /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20) /* 256 MiB */
+#define CFG_MAX_RAM_BANK_SIZE	(256 << 20) /* 256 MiB */
 
 /* Watchdog */
 #define WATCHDOG_TRIGGER_GPIO	14

include/configs/thuban.h

@@ -25,7 +25,7 @@
 	"led1=64,0,1\0"
 
  /* Physical Memory Map */
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
 #define EEPROM_ADDR_DDR3 0x90
 #define EEPROM_ADDR_CHIP 0x120

include/configs/ti816x_evm.h

@@ -19,7 +19,7 @@
 #define V_OSCK          24000000    /* Clock output from T2 */
 #define V_SCLK          (V_OSCK >> 1)
 
-#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
+#define CFG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
 /**

include/configs/ti_am335x_common.h

@@ -11,7 +11,7 @@
 #ifndef __CONFIG_TI_AM335X_COMMON_H__
 #define __CONFIG_TI_AM335X_COMMON_H__
 
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CFG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 #define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>

include/configs/ti_armv7_keystone2.h

@@ -15,7 +15,7 @@
 
 /* Memory Configuration */
 #define CFG_SYS_LPAE_SDRAM_BASE	0x800000000
-#define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
+#define CFG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 #define SPL_MALLOC_F_SIZE	CONFIG_SYS_MALLOC_F_LEN