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mx6: clock: Fix the calculation of PLL_ENET frequency

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According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2013-12-03 18:26:13 -02:00 committed by Stefano Babic
parent 502a710f5b
commit 89cfd0f575
1 changed files with 1 additions and 1 deletions
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2
arch/arm/cpu/armv7/mx6/clock.c
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@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div = __raw_readl(&imx_ccm->analog_pll_enet);
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return (div == 3 ? 125000000 : 25000000 * (div << 1));
return 25000000 * (div + (div >> 1) + 1);
default:
return 0;
}