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boards: ls2088aqds: Add support of I2C driver model.
Update ls2088aqds board init code to support DM_I2C. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Chuanhua Han
Prabhakar Kushwaha
parent
db07c447ca
commit
885ae0513a
@ -90,11 +90,16 @@ struct ls2080a_qds_mdio {
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struct mii_dev *realbus;
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};
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struct reg_pair {
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uint addr;
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u8 *val;
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};
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static void sgmii_configure_repeater(int serdes_port)
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{
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struct mii_dev *bus;
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uint8_t a = 0xf;
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int i, j, ret;
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int i, j, k, ret;
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int dpmac_id = 0, dpmac, mii_bus = 0;
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unsigned short value;
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char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
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@ -105,10 +110,30 @@ static void sgmii_configure_repeater(int serdes_port)
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
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struct reg_pair reg_pair[10] = {
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{6, ®_val[0]}, {4, ®_val[1]},
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{8, ®_val[2]}, {0xf, NULL},
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{0x11, NULL}, {0x16, NULL},
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{0x18, NULL}, {0x23, ®_val[3]},
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{0x2d, ®_val[4]}, {4, ®_val[5]},
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};
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int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
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#ifdef CONFIG_DM_I2C
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struct udevice *udev;
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#endif
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/* Set I2c to Slot 1 */
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i2c_write(0x77, 0, 0, &a, 1);
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x77, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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for (dpmac = 0; dpmac < 8; dpmac++) {
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/* Check the PHY status */
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@ -121,7 +146,15 @@ static void sgmii_configure_repeater(int serdes_port)
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mii_bus = 1;
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dpmac_id = dpmac + 9;
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a = 0xb;
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i2c_write(0x76, 0, 0, &a, 1);
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x76, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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break;
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}
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@ -154,29 +187,29 @@ static void sgmii_configure_repeater(int serdes_port)
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for (i = 0; i < 4; i++) {
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for (j = 0; j < 4; j++) {
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a = 0x18;
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i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
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a = 0x38;
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i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
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a = 0x4;
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i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
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reg_pair[3].val = &ch_a_eq[i];
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reg_pair[4].val = &ch_a_ctl2[j];
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reg_pair[5].val = &ch_b_eq[i];
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reg_pair[6].val = &ch_b_ctl2[j];
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i2c_write(i2c_addr[dpmac], 0xf, 1,
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&ch_a_eq[i], 1);
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i2c_write(i2c_addr[dpmac], 0x11, 1,
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&ch_a_ctl2[j], 1);
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for (k = 0; k < 10; k++) {
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(i2c_addr[dpmac],
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reg_pair[k].addr,
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1, reg_pair[k].val, 1);
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#else
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ret = i2c_get_chip_for_busnum(0,
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i2c_addr[dpmac],
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1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev,
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reg_pair[k].addr,
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reg_pair[k].val, 1);
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#endif
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if (ret)
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goto error;
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}
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i2c_write(i2c_addr[dpmac], 0x16, 1,
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&ch_b_eq[i], 1);
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i2c_write(i2c_addr[dpmac], 0x18, 1,
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&ch_b_ctl2[j], 1);
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a = 0x14;
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i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
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a = 0xb5;
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i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
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a = 0x20;
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i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
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mdelay(100);
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ret = miiphy_read(dev[mii_bus],
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riser_phy_addr[dpmac],
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@ -217,7 +250,7 @@ error:
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static void qsgmii_configure_repeater(int dpmac)
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{
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uint8_t a = 0xf;
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int i, j;
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int i, j, k;
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int i2c_phy_addr = 0;
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int phy_addr = 0;
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
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@ -227,12 +260,32 @@ static void qsgmii_configure_repeater(int dpmac)
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
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struct reg_pair reg_pair[10] = {
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{6, ®_val[0]}, {4, ®_val[1]},
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{8, ®_val[2]}, {0xf, NULL},
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{0x11, NULL}, {0x16, NULL},
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{0x18, NULL}, {0x23, ®_val[3]},
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{0x2d, ®_val[4]}, {4, ®_val[5]},
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};
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const char *dev = "LS2080A_QDS_MDIO0";
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int ret = 0;
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unsigned short value;
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#ifdef CONFIG_DM_I2C
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struct udevice *udev;
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#endif
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/* Set I2c to Slot 1 */
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i2c_write(0x77, 0, 0, &a, 1);
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x77, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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switch (dpmac) {
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case 1:
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@ -283,25 +336,29 @@ static void qsgmii_configure_repeater(int dpmac)
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for (i = 0; i < 4; i++) {
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for (j = 0; j < 4; j++) {
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a = 0x18;
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i2c_write(i2c_phy_addr, 6, 1, &a, 1);
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a = 0x38;
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i2c_write(i2c_phy_addr, 4, 1, &a, 1);
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a = 0x4;
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i2c_write(i2c_phy_addr, 8, 1, &a, 1);
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reg_pair[3].val = &ch_a_eq[i];
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reg_pair[4].val = &ch_a_ctl2[j];
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reg_pair[5].val = &ch_b_eq[i];
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reg_pair[6].val = &ch_b_ctl2[j];
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i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
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i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
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for (k = 0; k < 10; k++) {
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(i2c_phy_addr,
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reg_pair[k].addr,
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1, reg_pair[k].val, 1);
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#else
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ret = i2c_get_chip_for_busnum(0,
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i2c_phy_addr,
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1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev,
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reg_pair[k].addr,
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reg_pair[k].val, 1);
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#endif
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if (ret)
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goto error;
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}
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i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
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i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
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a = 0x14;
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i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
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a = 0xb5;
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i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
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a = 0x20;
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i2c_write(i2c_phy_addr, 4, 1, &a, 1);
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mdelay(100);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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@ -161,8 +161,16 @@ unsigned long get_board_ddr_clk(void)
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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#ifdef CONFIG_DM_I2C
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
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if (!ret)
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ret = dm_i2c_write(dev, 0, &ch, 1);
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#else
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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#endif
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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@ -225,9 +233,15 @@ int board_init(void)
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
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#ifdef CONFIG_DM_I2C
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rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
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#else
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rtc_enable_32khz_output();
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#endif
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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@ -16,7 +16,9 @@ unsigned long get_board_ddr_clk(void);
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#ifdef CONFIG_FSL_QSPI
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#define CONFIG_QIXIS_I2C_ACCESS
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#ifndef CONFIG_DM_I2C
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#define CONFIG_SYS_I2C_EARLY_INIT
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#endif
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#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
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#endif
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@ -324,6 +326,7 @@ unsigned long get_board_ddr_clk(void);
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*/
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#define RTC
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#define CONFIG_RTC_DS3231 1
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#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
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