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net, davinci_emac: make clock divider in MDIO control register configurable

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Define CONFIG_SYS_EMAC_TI_CLKDIV for setting the clkdiv value
in the MDIO control register.

Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Sandeep Paulraj <s-paulraj@ti.com>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Heiko Schocher 2011-11-01 20:00:27 +00:00 committed by Albert ARIBAUD
parent 1fa892c67b
commit 882ecfa390
1 changed files with 7 additions and 2 deletions
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9
drivers/net/davinci_emac.c
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@ -53,6 +53,11 @@ unsigned int emac_dbg = 0;
#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
#endif
#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
EMAC_MDIO_CLOCK_FREQ) - 1)
#endif
static void davinci_eth_mdio_enable(void);
static int gen_init_phy(int phy_addr);
@ -131,7 +136,7 @@ static void davinci_eth_mdio_enable(void)
{
u_int32_t clkdiv;
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) |
MDIO_CONTROL_ENABLE |
@ -473,7 +478,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
#endif
/* Init MDIO & get link state */
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
&adap_mdio->CONTROL);