mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-19 17:53:24 +08:00
Merge git://git.denx.de/u-boot-sh
- Beacon EmbeddedWorks RZG2H/N Dev Kit support
This commit is contained in:
commit
88262788fe
@ -809,6 +809,8 @@ dtb-$(CONFIG_RCAR_GEN2) += \
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dtb-$(CONFIG_RCAR_GEN3) += \
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r8a774a1-beacon-rzg2m-kit.dtb \
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r8a774b1-beacon-rzg2n-kit.dtb \
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r8a774e1-beacon-rzg2h-kit.dtb \
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r8a77950-ulcb-u-boot.dtb \
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r8a77950-salvator-x-u-boot.dtb \
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r8a77960-ulcb-u-boot.dtb \
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@ -5,35 +5,27 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/clk/versaclock.h>
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/ {
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aliases {
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serial0 = &scif2;
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serial1 = &hscif0;
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serial2 = &hscif1;
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serial3 = &scif0;
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serial4 = &hscif2;
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serial5 = &scif5;
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spi0 = &msiof0;
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spi1 = &msiof1;
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spi2 = &msiof2;
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spi3 = &msiof3;
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ethernet0 = &avb;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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backlight: backlight {
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backlight_lvds: backlight-lvds {
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compatible = "pwm-backlight";
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power-supply = <®_lcd>;
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enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
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pwms = <&pwm0 0 50000>;
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pwms = <&pwm2 0 25000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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};
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backlight_dpi: backlight-dpi {
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compatible = "pwm-backlight";
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power-supply = <®_lcd>;
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enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>;
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pwms = <&pwm0 0 25000>;
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brightness-levels = <0 25 33 50 63 75 88 100>;
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default-brightness-level = <6>;
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};
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hdmi0-out {
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compatible = "hdmi-connector";
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type = "a";
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@ -48,38 +40,38 @@
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keys {
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compatible = "gpio-keys";
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key-1 {
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key-1 { /* S19 */
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gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_1>;
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label = "Switch-1";
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linux,code = <KEY_UP>;
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label = "Up";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-2 {
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key-2 { /*S20 */
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gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_2>;
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label = "Switch-2";
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linux,code = <KEY_LEFT>;
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label = "Left";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-3 {
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key-3 { /* S21 */
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gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_3>;
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label = "Switch-3";
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linux,code = <KEY_DOWN>;
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label = "Down";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-4 {
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key-4 { /* S22 */
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gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_4>;
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label = "Switch-4";
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linux,code = <KEY_RIGHT>;
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label = "Right";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-5 {
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key-5 { /* S23 */
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gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_5>;
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label = "Switch-4";
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linux,code = <KEY_ENTER>;
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label = "Center";
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wakeup-source;
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debounce-interval = <20>;
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};
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@ -98,17 +90,59 @@
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led1 {
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gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
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label = "LED1";
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linux,default-trigger = "heartbeat";
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};
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led2 {
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gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
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label = "LED2";
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linux,default-trigger = "heartbeat";
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};
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led3 {
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gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
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label = "LED3";
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linux,default-trigger = "heartbeat";
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};
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};
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lvds {
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compatible = "panel-lvds";
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power-supply = <®_lcd_reset>;
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width-mm = <223>;
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height-mm = <125>;
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backlight = <&backlight_lvds>;
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data-mapping = "vesa-24";
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panel-timing {
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/* 800x480@60Hz */
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clock-frequency = <30000000>;
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hactive = <800>;
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vactive = <480>;
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hsync-len = <48>;
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hfront-porch = <40>;
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hback-porch = <40>;
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vfront-porch = <13>;
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vback-porch = <29>;
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vsync-len = <1>;
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hsync-active = <1>;
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vsync-active = <3>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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port {
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panel_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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};
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rgb {
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/* Different LCD with compatible timings */
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compatible = "rocktech,rk070er9427";
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backlight = <&backlight_dpi>;
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enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
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power-supply = <®_lcd>;
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port {
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rgb_panel: endpoint {
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remote-endpoint = <&du_out_rgb>;
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};
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};
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};
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@ -117,7 +151,7 @@
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regulator-name = "audio-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
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gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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@ -167,15 +201,12 @@
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1>, <1800000 0>;
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regulator-always-on;
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};
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/* External DU dot clocks */
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@ -190,10 +221,29 @@
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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&audio_clk_a {
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clock-frequency = <22579200>;
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hs_ep: endpoint {
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remote-endpoint = <&usb3_hs_ep>;
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};
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};
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port@1 {
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reg = <1>;
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ss_ep: endpoint {
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remote-endpoint = <&hd3ss3220_in_ep>;
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};
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};
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};
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};
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};
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&audio_clk_b {
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@ -214,30 +264,19 @@
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status = "okay";
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>,
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<&versaclock5 1>,
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<&x302_clk>,
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<&versaclock5 2>;
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clock-names = "du.0", "du.1", "du.2",
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"dclkin.0", "dclkin.1", "dclkin.2";
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&du_out_rgb {
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remote-endpoint = <&rgb_panel>;
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};
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&ehci0 {
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dr_mode = "otg";
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>;
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
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};
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&ehci1 {
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>;
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
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};
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&hdmi0 {
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@ -258,7 +297,6 @@
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};
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};
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port@2 {
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/* HDMI sound */
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reg = <2>;
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dw_hdmi0_snd_in: endpoint {
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remote-endpoint = <&rsnd_endpoint1>;
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@ -281,7 +319,7 @@
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&i2c2 {
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status = "okay";
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clock-frequency = <100000>;
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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@ -299,18 +337,49 @@
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#gpio-cells = <2>;
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};
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versaclock6_bb: versaclock6_bb@6a {
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gpio_exp4: gpio@23 {
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compatible = "onnn,pca9654";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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versaclock6_bb: clock-controller@6a {
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compatible = "idt,5p49v6965";
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reg = <0x6a>;
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#clock-cells = <1>;
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clocks = <&x304_clk>;
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clock-names = "xin";
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/* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
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assigned-clocks = <&versaclock6_bb 1>,
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<&versaclock6_bb 2>,
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<&versaclock6_bb 3>,
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<&versaclock6_bb 4>;
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assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24000000>;
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assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
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OUT1 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
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};
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OUT2 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
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};
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OUT3 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <3300000>;
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idt,slew-percent = <100>;
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};
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OUT4 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <3300000>;
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idt,slew-percent = <100>;
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};
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};
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};
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@ -324,13 +393,14 @@
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&i2c5 {
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status = "okay";
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clock-frequency = <100000>;
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||||
clock-frequency = <400000>;
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||||
pinctrl-0 = <&i2c5_pins>;
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pinctrl-names = "default";
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codec: wm8962@1a {
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compatible = "wlf,wm8962";
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reg = <0x1a>;
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clocks = <&versaclock6_bb 3>;
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DCVDD-supply = <®_audio>;
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||||
DBVDD-supply = <®_audio>;
|
||||
AVDD-supply = <®_audio>;
|
||||
@ -375,6 +445,49 @@
|
||||
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
hd3ss3220@47 {
|
||||
compatible = "ti,hd3ss3220";
|
||||
reg = <0x47>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hd3ss3220_in_ep: endpoint {
|
||||
remote-endpoint = <&ss_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hd3ss3220_out_ep: endpoint {
|
||||
remote-endpoint = <&usb3_role_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&msiof1 {
|
||||
pinctrl-0 = <&msiof1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
@ -440,6 +553,11 @@
|
||||
function = "pwm0";
|
||||
};
|
||||
|
||||
pwm2_pins: pwm2 {
|
||||
groups = "pwm2_a";
|
||||
function = "pwm2";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
@ -458,7 +576,7 @@
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a_a";
|
||||
groups = "audio_clk_a_a", "audio_clk_b_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
@ -490,6 +608,12 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-0 = <&pwm2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
@ -503,23 +627,6 @@
|
||||
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -551,6 +658,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
@ -584,6 +696,26 @@
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&tmu0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
@ -595,3 +727,62 @@
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_peri0 {
|
||||
companion = <&xhci0>;
|
||||
status = "okay";
|
||||
usb-role-switch;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb3_hs_ep: endpoint {
|
||||
remote-endpoint = <&hs_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
usb3_role_switch: endpoint {
|
||||
remote-endpoint = <&hd3ss3220_out_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin0 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin1 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin2 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin3 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin4 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin5 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin6 {
|
||||
status = "okay";
|
||||
};
|
||||
&vin7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci0
|
||||
{
|
||||
pinctrl-0 = <&usb30_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -4,17 +4,18 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
|
||||
/ {
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
reg = <0x0 0x48000000 0x0 0xc000000>;
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
memory@57000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
reg = <0x0 0x57000000 0x0 0x29000000>;
|
||||
};
|
||||
|
||||
osc_32k: osc_32k {
|
||||
@ -55,7 +56,8 @@
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
rx-internal-delay-ps = <1800>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
@ -88,7 +90,6 @@
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
max-speed = <4000000>;
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
@ -97,6 +98,7 @@
|
||||
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&osc_32k>;
|
||||
clock-names = "extclk";
|
||||
max-speed = <4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -108,7 +110,7 @@
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pca9654: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
@ -147,7 +149,7 @@
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "microchip, at24c64", "atmel,24c64";
|
||||
compatible = "microchip,at24c64", "atmel,24c64";
|
||||
pagesize = <32>;
|
||||
read-only; /* Manufacturing EEPROM programmed at factory */
|
||||
reg = <0x50>;
|
||||
@ -169,7 +171,32 @@
|
||||
<&versaclock5 2>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 4>;
|
||||
|
||||
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
|
||||
|
||||
OUT1 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
|
||||
OUT2 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
|
||||
OUT3 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
|
||||
OUT4 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <3300000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -295,18 +322,14 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_extal_clk {
|
||||
clock-frequency = <50000000>;
|
||||
&usb2_clksel {
|
||||
status = "okay";
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&versaclock5 3>, <&usb3s0_clk>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if",
|
||||
"usb_extal", "usb_xtal";
|
||||
};
|
||||
|
||||
&usb3s0_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&vspb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vspi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -10,6 +10,61 @@
|
||||
#include "beacon-renesom-baseboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2M Development Kit";
|
||||
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
|
||||
model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
|
||||
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif0;
|
||||
serial2 = &hscif1;
|
||||
serial3 = &scif0;
|
||||
serial4 = &hscif2;
|
||||
serial5 = &scif5;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
/* Reference versaclock instead of audio_clk_a */
|
||||
&rcar_sound {
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&versaclock6_bb 4>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
|
||||
};
|
||||
|
@ -408,7 +408,7 @@
|
||||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a774a1";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
@ -835,6 +835,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&usb_extal_clk>, <&usb3s0_clk>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if",
|
||||
"usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
reset-names = "ehci_ohci", "hs-usb-if";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a774a1-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
@ -1115,6 +1130,8 @@
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -2300,6 +2317,23 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774a1-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@ -2371,6 +2405,44 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0_ep: pcie-ep@fe000000 {
|
||||
compatible = "renesas,r8a774a1-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xfe000000 0 0x80000>,
|
||||
<0x0 0xfe100000 0 0x100000>,
|
||||
<0x0 0xfe200000 0 0x200000>,
|
||||
<0x0 0x30000000 0 0x8000000>,
|
||||
<0x0 0x38000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 319>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 319>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec1_ep: pcie-ep@ee800000 {
|
||||
compatible = "renesas,r8a774a1-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xee800000 0 0x80000>,
|
||||
<0x0 0xee900000 0 0x100000>,
|
||||
<0x0 0xeea00000 0 0x200000>,
|
||||
<0x0 0xc0000000 0 0x8000000>,
|
||||
<0x0 0xc8000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 318>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 318>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fdp1@fe940000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe940000 0 0x2400>;
|
||||
|
34
arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
Normal file
34
arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
Normal file
@ -0,0 +1,34 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&cpg {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&prr {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
/delete-property/ cd-gpios;
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
status = "disabled";
|
||||
};
|
66
arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
Normal file
66
arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
Normal file
@ -0,0 +1,66 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020, Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r8a774b1.dtsi"
|
||||
#include "beacon-renesom-som.dtsi"
|
||||
#include "beacon-renesom-baseboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2N Development Kit";
|
||||
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif0;
|
||||
serial2 = &hscif1;
|
||||
serial3 = &scif0;
|
||||
serial4 = &hscif2;
|
||||
serial5 = &scif5;
|
||||
serial6 = &scif4;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
/* Reference versaclock instead of audio_clk_a */
|
||||
&rcar_sound {
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&versaclock6_bb 4>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774B1_CLK_S0D4>;
|
||||
};
|
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Device Tree Source for the r8a774b1 SoC
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
@ -282,7 +282,7 @@
|
||||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a774b1";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
@ -709,6 +709,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a774b1-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&usb_extal_clk>, <&usb3s0_clk>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if",
|
||||
"usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
reset-names = "ehci_ohci", "hs-usb-if";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a774b1-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
@ -989,6 +1004,8 @@
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -2158,6 +2175,23 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774b1-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a774b1",
|
||||
"renesas,rcar-gen3-sata";
|
||||
@ -2240,6 +2274,44 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0_ep: pcie-ep@fe000000 {
|
||||
compatible = "renesas,r8a774b1-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xfe000000 0 0x80000>,
|
||||
<0x0 0xfe100000 0 0x100000>,
|
||||
<0x0 0xfe200000 0 0x200000>,
|
||||
<0x0 0x30000000 0 0x8000000>,
|
||||
<0x0 0x38000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 319>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 319>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec1_ep: pcie-ep@ee800000 {
|
||||
compatible = "renesas,r8a774b1-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xee800000 0 0x80000>,
|
||||
<0x0 0xee900000 0 0x100000>,
|
||||
<0x0 0xeea00000 0 0x200000>,
|
||||
<0x0 0xc0000000 0 0x8000000>,
|
||||
<0x0 0xc8000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 318>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 318>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fdp1@fe940000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe940000 0 0x2400>;
|
||||
|
44
arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
Normal file
44
arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
Normal file
@ -0,0 +1,44 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&cpg {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&prr {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
/delete-property/ cd-gpios;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr104;
|
||||
max-frequency = <208000000>;
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
};
|
71
arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
Normal file
71
arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
Normal file
@ -0,0 +1,71 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020, Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r8a774e1.dtsi"
|
||||
#include "beacon-renesom-som.dtsi"
|
||||
#include "beacon-renesom-baseboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2H Development Kit";
|
||||
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif0;
|
||||
serial2 = &hscif1;
|
||||
serial3 = &scif0;
|
||||
serial4 = &hscif2;
|
||||
serial5 = &scif5;
|
||||
serial6 = &scif4;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@500000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x5 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
/* Reference versaclock instead of audio_clk_a */
|
||||
&rcar_sound {
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&versaclock6_bb 4>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774E1_CLK_S0D4>;
|
||||
};
|
File diff suppressed because it is too large
Load Diff
@ -60,11 +60,21 @@ choice
|
||||
prompt "Renesas ARM64 SoCs board select"
|
||||
optional
|
||||
|
||||
config TARGET_BEACON_RZG2H
|
||||
bool "Beacon EmbeddedWorks RZ/G2H Dev Kit"
|
||||
select R8A774E1
|
||||
select PINCTRL_PFC_R8A774E1
|
||||
|
||||
config TARGET_BEACON_RZG2M
|
||||
bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
|
||||
select R8A774A1
|
||||
select PINCTRL_PFC_R8A774A1
|
||||
|
||||
config TARGET_BEACON_RZG2N
|
||||
bool "Beacon EmbeddedWorks RZ/G2N Dev Kit"
|
||||
select R8A774B1
|
||||
select PINCTRL_PFC_R8A774B1
|
||||
|
||||
config TARGET_CONDOR
|
||||
bool "Condor board"
|
||||
imply R8A77980
|
||||
|
@ -1,4 +1,4 @@
|
||||
if TARGET_BEACON_RZG2M
|
||||
if TARGET_BEACON_RZG2H || TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
@ -4,3 +4,5 @@ S: Maintained
|
||||
F: board/beacon/beacon-rzg2m/
|
||||
F: include/configs/beacon-rzg2m.h
|
||||
F: configs/r8a774a1_beacon_defconfig
|
||||
F: configs/r8a774b1_beacon_defconfig
|
||||
F: configs/r8a774e1_beacon_defconfig
|
||||
|
71
configs/r8a774b1_beacon_defconfig
Normal file
71
configs/r8a774b1_beacon_defconfig
Normal file
@ -0,0 +1,71 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A774B1=y
|
||||
CONFIG_TARGET_BEACON_RZG2N=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774b1-beacon-rzg2n-kit.dtb"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
67
configs/r8a774e1_beacon_defconfig
Normal file
67
configs/r8a774e1_beacon_defconfig
Normal file
@ -0,0 +1,67 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A774E1=y
|
||||
CONFIG_TARGET_BEACON_RZG2H=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774e1-beacon-rzg2h-kit.dtb"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_PINCTRL_PFC_R8A774E1=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
13
include/dt-bindings/clk/versaclock.h
Normal file
13
include/dt-bindings/clk/versaclock.h
Normal file
@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
/* This file defines field values used by the versaclock 6 family
|
||||
* for defining output type
|
||||
*/
|
||||
|
||||
#define VC5_LVPECL 0
|
||||
#define VC5_CMOS 1
|
||||
#define VC5_HCSL33 2
|
||||
#define VC5_LVDS 3
|
||||
#define VC5_CMOS2 4
|
||||
#define VC5_CMOSD 5
|
||||
#define VC5_HCSL25 6
|
Loading…
Reference in New Issue
Block a user