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pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0
Synchronize R-Car Gen3 pin control tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
a6a743df24
commit
8719ca8113
@ -2,7 +2,7 @@
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/*
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* R8A7795 ES2.0+ processor support - PFC hardware block.
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*
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* Copyright (C) 2015-2019 Renesas Electronics Corporation
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*/
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#include <common.h>
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@ -202,8 +202,8 @@
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#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
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/* GPSR7 */
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#define GPSR7_3 FM(GP7_03)
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#define GPSR7_2 FM(GP7_02)
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#define GPSR7_3 FM(HDMI1_CEC)
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#define GPSR7_2 FM(HDMI0_CEC)
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#define GPSR7_1 FM(AVS2)
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#define GPSR7_0 FM(AVS1)
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@ -352,7 +352,7 @@
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#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
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#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
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@ -463,7 +463,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
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#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
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#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
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#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
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#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
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#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
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/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
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#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
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@ -499,8 +499,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
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#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
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#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
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#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
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#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
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#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
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#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
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#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
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#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
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#define PINMUX_MOD_SELS \
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@ -552,6 +552,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
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FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
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FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
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#define PINMUX_PHYS \
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FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
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enum {
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PINMUX_RESERVED = 0,
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@ -577,6 +580,7 @@ enum {
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PINMUX_IPSR
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PINMUX_MOD_SELS
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PINMUX_STATIC
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PINMUX_PHYS
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PINMUX_MARK_END,
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#undef F_
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#undef FM
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@ -588,11 +592,8 @@ static const u16 pinmux_data[] = {
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PINMUX_SINGLE(AVS1),
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PINMUX_SINGLE(AVS2),
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PINMUX_SINGLE(CLKOUT),
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PINMUX_SINGLE(GP7_02),
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PINMUX_SINGLE(GP7_03),
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PINMUX_SINGLE(I2C_SEL_0_1),
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PINMUX_SINGLE(I2C_SEL_3_1),
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PINMUX_SINGLE(I2C_SEL_5_1),
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PINMUX_SINGLE(HDMI0_CEC),
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PINMUX_SINGLE(HDMI1_CEC),
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PINMUX_SINGLE(MSIOF0_RXD),
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PINMUX_SINGLE(MSIOF0_SCK),
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PINMUX_SINGLE(MSIOF0_TXD),
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@ -616,14 +617,16 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
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PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
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PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
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PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
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PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
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PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
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PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
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PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
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PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
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PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
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PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
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PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
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@ -676,14 +679,16 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
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PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
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PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
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PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
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PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
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PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
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PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
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PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
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PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
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PINMUX_IPSR_GPSR(IP1_31_28, A0),
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PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
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@ -1115,16 +1120,18 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
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PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
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PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
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PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
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PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
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PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
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PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
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PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
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PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
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PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
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PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
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PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
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PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
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PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
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PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
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PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
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@ -1157,7 +1164,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
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PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
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PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
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PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
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PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
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PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
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PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
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PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
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@ -1216,7 +1223,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
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PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
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PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
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PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
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PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
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PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
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@ -1263,7 +1270,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
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PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
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PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
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PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
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PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
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PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
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PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
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@ -1272,7 +1279,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
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PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
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PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
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PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
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PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
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PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
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PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
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@ -1403,9 +1410,10 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
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/* IPSR17 */
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PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
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PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
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PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
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PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
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PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
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PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
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PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
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PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
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@ -1491,10 +1499,10 @@ static const u16 pinmux_data[] = {
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/*
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* Static pins can not be muxed between different functions but
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* still needs a mark entry in the pinmux list. Add each static
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* still need mark entries in the pinmux list. Add each static
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* pin to the list without an associated function. The sh-pfc
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* core will do the right thing and skip trying to mux then pin
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* while still applying configuration to it
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* core will do the right thing and skip trying to mux the pin
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* while still applying configuration to it.
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*/
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#define FM(x) PINMUX_DATA(x##_MARK, 0),
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PINMUX_STATIC
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@ -2125,23 +2133,20 @@ static const unsigned int du_disp_mux[] = {
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DU_DISP_MARK,
|
||||
};
|
||||
|
||||
/* - GP7_02/03 -------------------------------------------------------------- */
|
||||
static const unsigned int gp7_02_pins[] = {
|
||||
/* GP7_02 */
|
||||
/* - HDMI ------------------------------------------------------------------- */
|
||||
static const unsigned int hdmi0_cec_pins[] = {
|
||||
/* HDMI0_CEC */
|
||||
RCAR_GP_PIN(7, 2),
|
||||
};
|
||||
|
||||
static const unsigned int gp7_02_mux[] = {
|
||||
GP7_02_MARK,
|
||||
static const unsigned int hdmi0_cec_mux[] = {
|
||||
HDMI0_CEC_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int gp7_03_pins[] = {
|
||||
/* GP7_03 */
|
||||
static const unsigned int hdmi1_cec_pins[] = {
|
||||
/* HDMI1_CEC */
|
||||
RCAR_GP_PIN(7, 3),
|
||||
};
|
||||
|
||||
static const unsigned int gp7_03_mux[] = {
|
||||
GP7_03_MARK,
|
||||
static const unsigned int hdmi1_cec_mux[] = {
|
||||
HDMI1_CEC_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF0 ----------------------------------------------------------------- */
|
||||
@ -2352,6 +2357,15 @@ static const unsigned int hscif4_data_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - I2C -------------------------------------------------------------------- */
|
||||
static const unsigned int i2c0_pins[] = {
|
||||
/* SCL, SDA */
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
|
||||
static const unsigned int i2c0_mux[] = {
|
||||
SCL0_MARK, SDA0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c1_a_pins[] = {
|
||||
/* SDA, SCL */
|
||||
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
|
||||
@ -2380,6 +2394,25 @@ static const unsigned int i2c2_b_pins[] = {
|
||||
static const unsigned int i2c2_b_mux[] = {
|
||||
SDA2_B_MARK, SCL2_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c3_pins[] = {
|
||||
/* SCL, SDA */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
|
||||
static const unsigned int i2c3_mux[] = {
|
||||
SCL3_MARK, SDA3_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c5_pins[] = {
|
||||
/* SCL, SDA */
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
};
|
||||
|
||||
static const unsigned int i2c5_mux[] = {
|
||||
SCL5_MARK, SDA5_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c6_a_pins[] = {
|
||||
/* SDA, SCL */
|
||||
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
|
||||
@ -3123,7 +3156,7 @@ static const unsigned int msiof3_ss1_e_mux[] = {
|
||||
MSIOF3_SS1_E_MARK,
|
||||
};
|
||||
static const unsigned int msiof3_ss2_e_pins[] = {
|
||||
/* SS1 */
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(2, 0),
|
||||
};
|
||||
static const unsigned int msiof3_ss2_e_mux[] = {
|
||||
@ -4067,67 +4100,29 @@ static const unsigned int vin4_clk_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin5_data8_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
static const union vin_data16 vin5_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
},
|
||||
};
|
||||
static const unsigned int vin5_data8_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data10_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
};
|
||||
static const unsigned int vin5_data10_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data12_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
};
|
||||
static const unsigned int vin5_data12_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data16_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin5_data16_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
static const union vin_data16 vin5_data_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -4232,8 +4227,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(du_oddf),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(gp7_02),
|
||||
SH_PFC_PIN_GROUP(gp7_03),
|
||||
SH_PFC_PIN_GROUP(hdmi0_cec),
|
||||
SH_PFC_PIN_GROUP(hdmi1_cec),
|
||||
SH_PFC_PIN_GROUP(hscif0_data),
|
||||
SH_PFC_PIN_GROUP(hscif0_clk),
|
||||
SH_PFC_PIN_GROUP(hscif0_ctrl),
|
||||
@ -4262,10 +4257,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(hscif4_clk),
|
||||
SH_PFC_PIN_GROUP(hscif4_ctrl),
|
||||
SH_PFC_PIN_GROUP(hscif4_data_b),
|
||||
SH_PFC_PIN_GROUP(i2c0),
|
||||
SH_PFC_PIN_GROUP(i2c1_a),
|
||||
SH_PFC_PIN_GROUP(i2c1_b),
|
||||
SH_PFC_PIN_GROUP(i2c2_a),
|
||||
SH_PFC_PIN_GROUP(i2c2_b),
|
||||
SH_PFC_PIN_GROUP(i2c3),
|
||||
SH_PFC_PIN_GROUP(i2c5),
|
||||
SH_PFC_PIN_GROUP(i2c6_a),
|
||||
SH_PFC_PIN_GROUP(i2c6_b),
|
||||
SH_PFC_PIN_GROUP(i2c6_c),
|
||||
@ -4478,28 +4476,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(usb2),
|
||||
SH_PFC_PIN_GROUP(usb2_ch3),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
SH_PFC_PIN_GROUP(vin5_data8),
|
||||
SH_PFC_PIN_GROUP(vin5_data10),
|
||||
SH_PFC_PIN_GROUP(vin5_data12),
|
||||
SH_PFC_PIN_GROUP(vin5_data16),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
@ -4615,12 +4613,12 @@ static const char * const du_groups[] = {
|
||||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const gp7_02_groups[] = {
|
||||
"gp7_02",
|
||||
static const char * const hdmi0_groups[] = {
|
||||
"hdmi0_cec",
|
||||
};
|
||||
|
||||
static const char * const gp7_03_groups[] = {
|
||||
"gp7_03",
|
||||
static const char * const hdmi1_groups[] = {
|
||||
"hdmi1_cec",
|
||||
};
|
||||
|
||||
static const char * const hscif0_groups[] = {
|
||||
@ -4666,6 +4664,10 @@ static const char * const hscif4_groups[] = {
|
||||
"hscif4_data_b",
|
||||
};
|
||||
|
||||
static const char * const i2c0_groups[] = {
|
||||
"i2c0",
|
||||
};
|
||||
|
||||
static const char * const i2c1_groups[] = {
|
||||
"i2c1_a",
|
||||
"i2c1_b",
|
||||
@ -4676,6 +4678,14 @@ static const char * const i2c2_groups[] = {
|
||||
"i2c2_b",
|
||||
};
|
||||
|
||||
static const char * const i2c3_groups[] = {
|
||||
"i2c3",
|
||||
};
|
||||
|
||||
static const char * const i2c5_groups[] = {
|
||||
"i2c5",
|
||||
};
|
||||
|
||||
static const char * const i2c6_groups[] = {
|
||||
"i2c6_a",
|
||||
"i2c6_b",
|
||||
@ -5029,15 +5039,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(gp7_02),
|
||||
SH_PFC_FUNCTION(gp7_03),
|
||||
SH_PFC_FUNCTION(hdmi0),
|
||||
SH_PFC_FUNCTION(hdmi1),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
SH_PFC_FUNCTION(hscif2),
|
||||
SH_PFC_FUNCTION(hscif3),
|
||||
SH_PFC_FUNCTION(hscif4),
|
||||
SH_PFC_FUNCTION(i2c0),
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(i2c5),
|
||||
SH_PFC_FUNCTION(i2c6),
|
||||
SH_PFC_FUNCTION(intc_ex),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
@ -5751,8 +5764,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
|
||||
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
@ -6006,8 +6019,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
[25] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
|
||||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -557,7 +557,7 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
|
||||
FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
|
||||
FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
|
||||
FM(PRESETOUT) \
|
||||
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
|
||||
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
|
||||
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
|
||||
|
||||
enum {
|
||||
@ -1569,7 +1569,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
|
||||
@ -1853,6 +1853,280 @@ static const unsigned int canfd1_data_mux[] = {
|
||||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
/* - DRIF0 --------------------------------------------------------------- */
|
||||
static const unsigned int drif0_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_ctrl_a_mux[] = {
|
||||
RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data0_a_mux[] = {
|
||||
RIF0_D0_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 7),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data1_a_mux[] = {
|
||||
RIF0_D1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_ctrl_b_mux[] = {
|
||||
RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(5, 1),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data0_b_mux[] = {
|
||||
RIF0_D0_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(5, 2),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data1_b_mux[] = {
|
||||
RIF0_D1_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_ctrl_c_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_ctrl_c_mux[] = {
|
||||
RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data0_c_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(5, 13),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data0_c_mux[] = {
|
||||
RIF0_D0_C_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data1_c_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(5, 14),
|
||||
};
|
||||
|
||||
static const unsigned int drif0_data1_c_mux[] = {
|
||||
RIF0_D1_C_MARK,
|
||||
};
|
||||
|
||||
/* - DRIF1 --------------------------------------------------------------- */
|
||||
static const unsigned int drif1_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_ctrl_a_mux[] = {
|
||||
RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data0_a_mux[] = {
|
||||
RIF1_D0_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 20),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data1_a_mux[] = {
|
||||
RIF1_D1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_ctrl_b_mux[] = {
|
||||
RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(5, 7),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data0_b_mux[] = {
|
||||
RIF1_D0_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(5, 8),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data1_b_mux[] = {
|
||||
RIF1_D1_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_ctrl_c_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_ctrl_c_mux[] = {
|
||||
RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data0_c_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(5, 6),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data0_c_mux[] = {
|
||||
RIF1_D0_C_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data1_c_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
|
||||
static const unsigned int drif1_data1_c_mux[] = {
|
||||
RIF1_D1_C_MARK,
|
||||
};
|
||||
|
||||
/* - DRIF2 --------------------------------------------------------------- */
|
||||
static const unsigned int drif2_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
|
||||
};
|
||||
|
||||
static const unsigned int drif2_ctrl_a_mux[] = {
|
||||
RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 7),
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data0_a_mux[] = {
|
||||
RIF2_D0_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data1_a_mux[] = {
|
||||
RIF2_D1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif2_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
|
||||
};
|
||||
|
||||
static const unsigned int drif2_ctrl_b_mux[] = {
|
||||
RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 30),
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data0_b_mux[] = {
|
||||
RIF2_D0_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
|
||||
static const unsigned int drif2_data1_b_mux[] = {
|
||||
RIF2_D1_B_MARK,
|
||||
};
|
||||
|
||||
/* - DRIF3 --------------------------------------------------------------- */
|
||||
static const unsigned int drif3_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
|
||||
static const unsigned int drif3_ctrl_a_mux[] = {
|
||||
RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data0_a_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data0_a_mux[] = {
|
||||
RIF3_D0_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data1_a_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 20),
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data1_a_mux[] = {
|
||||
RIF3_D1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif3_ctrl_b_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
|
||||
};
|
||||
|
||||
static const unsigned int drif3_ctrl_b_mux[] = {
|
||||
RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data0_b_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data0_b_mux[] = {
|
||||
RIF3_D0_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data1_b_pins[] = {
|
||||
/* D1 */
|
||||
RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
|
||||
static const unsigned int drif3_data1_b_mux[] = {
|
||||
RIF3_D1_B_MARK,
|
||||
};
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
/* R[7:2], G[7:2], B[7:2] */
|
||||
@ -3763,6 +4037,42 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
|
||||
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
|
||||
};
|
||||
|
||||
/* - TMU -------------------------------------------------------------------- */
|
||||
static const unsigned int tmu_tclk1_a_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 23),
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk1_a_mux[] = {
|
||||
TCLK1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk1_b_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk1_b_mux[] = {
|
||||
TCLK1_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk2_a_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk2_a_mux[] = {
|
||||
TCLK2_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk2_b_pins[] = {
|
||||
/* TCLK */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
|
||||
static const unsigned int tmu_tclk2_b_mux[] = {
|
||||
TCLK2_B_MARK,
|
||||
};
|
||||
|
||||
/* - USB0 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb0_pins[] = {
|
||||
@ -4040,6 +4350,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(canfd0_data_a),
|
||||
SH_PFC_PIN_GROUP(canfd0_data_b),
|
||||
SH_PFC_PIN_GROUP(canfd1_data),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_b),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_c),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_c),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_c),
|
||||
SH_PFC_PIN_GROUP(drif1_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif1_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif1_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif1_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif1_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif1_data1_b),
|
||||
SH_PFC_PIN_GROUP(drif1_ctrl_c),
|
||||
SH_PFC_PIN_GROUP(drif1_data0_c),
|
||||
SH_PFC_PIN_GROUP(drif1_data1_c),
|
||||
SH_PFC_PIN_GROUP(drif2_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif2_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif2_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif2_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif2_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif2_data1_b),
|
||||
SH_PFC_PIN_GROUP(drif3_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_a),
|
||||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(du_rgb666),
|
||||
SH_PFC_PIN_GROUP(du_rgb888),
|
||||
SH_PFC_PIN_GROUP(du_clk_out_0),
|
||||
@ -4283,6 +4623,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(ssi9_data_b),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
@ -4370,6 +4714,48 @@ static const char * const canfd1_groups[] = {
|
||||
"canfd1_data",
|
||||
};
|
||||
|
||||
static const char * const drif0_groups[] = {
|
||||
"drif0_ctrl_a",
|
||||
"drif0_data0_a",
|
||||
"drif0_data1_a",
|
||||
"drif0_ctrl_b",
|
||||
"drif0_data0_b",
|
||||
"drif0_data1_b",
|
||||
"drif0_ctrl_c",
|
||||
"drif0_data0_c",
|
||||
"drif0_data1_c",
|
||||
};
|
||||
|
||||
static const char * const drif1_groups[] = {
|
||||
"drif1_ctrl_a",
|
||||
"drif1_data0_a",
|
||||
"drif1_data1_a",
|
||||
"drif1_ctrl_b",
|
||||
"drif1_data0_b",
|
||||
"drif1_data1_b",
|
||||
"drif1_ctrl_c",
|
||||
"drif1_data0_c",
|
||||
"drif1_data1_c",
|
||||
};
|
||||
|
||||
static const char * const drif2_groups[] = {
|
||||
"drif2_ctrl_a",
|
||||
"drif2_data0_a",
|
||||
"drif2_data1_a",
|
||||
"drif2_ctrl_b",
|
||||
"drif2_data0_b",
|
||||
"drif2_data1_b",
|
||||
};
|
||||
|
||||
static const char * const drif3_groups[] = {
|
||||
"drif3_ctrl_a",
|
||||
"drif3_data0_a",
|
||||
"drif3_data1_a",
|
||||
"drif3_ctrl_b",
|
||||
"drif3_data0_b",
|
||||
"drif3_data1_b",
|
||||
};
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
"du_rgb888",
|
||||
@ -4714,6 +5100,13 @@ static const char * const ssi_groups[] = {
|
||||
"ssi9_ctrl_b",
|
||||
};
|
||||
|
||||
static const char * const tmu_groups[] = {
|
||||
"tmu_tclk1_a",
|
||||
"tmu_tclk1_b",
|
||||
"tmu_tclk2_a",
|
||||
"tmu_tclk2_b",
|
||||
};
|
||||
|
||||
static const char * const usb0_groups[] = {
|
||||
"usb0",
|
||||
};
|
||||
@ -4766,6 +5159,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(can_clk),
|
||||
SH_PFC_FUNCTION(canfd0),
|
||||
SH_PFC_FUNCTION(canfd1),
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
@ -4800,6 +5197,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(sdhi2),
|
||||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
SH_PFC_FUNCTION(tmu),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
SH_PFC_FUNCTION(usb1),
|
||||
SH_PFC_FUNCTION(usb30),
|
||||
@ -5743,7 +6141,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
|
||||
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
|
||||
[ 1] = PIN_NONE,
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
* R8A77970 processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
|
||||
*
|
||||
@ -20,12 +21,12 @@
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_28(1, fn, sfx), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_6(4, fn, sfx), \
|
||||
PORT_GP_15(5, fn, sfx)
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
@ -1383,6 +1384,56 @@ static const unsigned int pwm4_b_mux[] = {
|
||||
PWM4_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* SPCLK, SSL */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK
|
||||
};
|
||||
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* SPCLK, SSL */
|
||||
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
||||
/* - SCIF Clock ------------------------------------------------------------- */
|
||||
static const unsigned int scif_clk_a_pins[] = {
|
||||
/* SCIF_CLK */
|
||||
@ -1529,47 +1580,25 @@ static const unsigned int tmu_tclk2_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin0_data8_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
static const union vin_data12 vin0_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
},
|
||||
};
|
||||
static const unsigned int vin0_data8_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data10_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
};
|
||||
static const unsigned int vin0_data10_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data12_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
};
|
||||
static const unsigned int vin0_data12_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
static const union vin_data12 vin0_data_mux = {
|
||||
.data12 = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin0_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1601,47 +1630,25 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin1_data8_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
},
|
||||
};
|
||||
static const unsigned int vin1_data8_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data10_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
};
|
||||
static const unsigned int vin1_data10_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data12_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const unsigned int vin1_data12_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1757,6 +1764,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(pwm3_b),
|
||||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
@ -1776,16 +1789,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
SH_PFC_PIN_GROUP(vin0_data8),
|
||||
SH_PFC_PIN_GROUP(vin0_data10),
|
||||
SH_PFC_PIN_GROUP(vin0_data12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
SH_PFC_PIN_GROUP(vin1_data8),
|
||||
SH_PFC_PIN_GROUP(vin1_data10),
|
||||
SH_PFC_PIN_GROUP(vin1_data12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
@ -1951,6 +1964,18 @@ static const char * const pwm4_groups[] = {
|
||||
"pwm4_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const scif_clk_groups[] = {
|
||||
"scif_clk_a",
|
||||
"scif_clk_b",
|
||||
@ -2034,6 +2059,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(scif_clk),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
@ -2352,7 +2379,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -2380,18 +2407,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
IOCTRL30,
|
||||
IOCTRL31,
|
||||
IOCTRL32,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[IOCTRL30] = { 0xe6060380 },
|
||||
[IOCTRL31] = { 0xe6060384 },
|
||||
[IOCTRL32] = { 0xe6060388 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
*pocctrl = 0xe6060380;
|
||||
*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
|
||||
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
|
||||
return bit;
|
||||
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
|
||||
return bit + 22;
|
||||
|
||||
*pocctrl += 4;
|
||||
*pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
|
||||
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
|
||||
return bit - 10;
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
|
||||
@ -2419,6 +2459,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -384,6 +384,9 @@ FM(IP12_23_20) IP12_23_20 \
|
||||
FM(IP12_27_24) IP12_27_24 \
|
||||
FM(IP12_31_28) IP12_31_28 \
|
||||
|
||||
/* The bit numbering in MOD_SEL fields is reversed */
|
||||
#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
|
||||
|
||||
/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
|
||||
#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
|
||||
#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
|
||||
@ -391,10 +394,10 @@ FM(IP12_31_28) IP12_31_28 \
|
||||
#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
|
||||
#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
|
||||
#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
|
||||
#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
|
||||
#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
|
||||
#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
|
||||
#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
|
||||
#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
|
||||
#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
|
||||
#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
|
||||
#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
|
||||
#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
|
||||
#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
|
||||
#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
|
||||
@ -471,12 +474,6 @@ enum {
|
||||
#undef FM
|
||||
};
|
||||
|
||||
#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
|
||||
|
||||
#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel)
|
||||
|
||||
static const u16 pinmux_data[] = {
|
||||
PINMUX_DATA_GP_ALL(),
|
||||
|
||||
@ -520,6 +517,10 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_SINGLE(QSPI0_SPCLK),
|
||||
PINMUX_SINGLE(SCL0),
|
||||
PINMUX_SINGLE(SDA0),
|
||||
PINMUX_SINGLE(MSIOF0_RXD),
|
||||
PINMUX_SINGLE(MSIOF0_TXD),
|
||||
PINMUX_SINGLE(MSIOF0_SYNC),
|
||||
PINMUX_SINGLE(MSIOF0_SCK),
|
||||
|
||||
/* IPSR0 */
|
||||
PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
|
||||
@ -1277,6 +1278,289 @@ static const unsigned int mmc_ctrl_mux[] = {
|
||||
MMC_CLK_MARK, MMC_CMD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_clk_mux[] = {
|
||||
MSIOF0_SCK_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_sync_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(4, 13),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_sync_mux[] = {
|
||||
MSIOF0_SYNC_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss1_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(4, 20),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss1_mux[] = {
|
||||
MSIOF0_SS1_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss2_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(4, 21),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss2_mux[] = {
|
||||
MSIOF0_SS2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_txd_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(4, 14),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_txd_mux[] = {
|
||||
MSIOF0_TXD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_rxd_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(4, 15),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_rxd_mux[] = {
|
||||
MSIOF0_RXD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF1 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof1_clk_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_clk_mux[] = {
|
||||
MSIOF1_SCK_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_sync_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(4, 19),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_sync_mux[] = {
|
||||
MSIOF1_SYNC_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss1_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(4, 25),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss1_mux[] = {
|
||||
MSIOF1_SS1_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss2_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(4, 22),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss2_mux[] = {
|
||||
MSIOF1_SS2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_txd_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(4, 17),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_txd_mux[] = {
|
||||
MSIOF1_TXD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_rxd_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(4, 18),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_rxd_mux[] = {
|
||||
MSIOF1_RXD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF2 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof2_clk_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_clk_mux[] = {
|
||||
MSIOF2_SCK_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_a_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(0, 6),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_a_mux[] = {
|
||||
MSIOF2_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_b_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(0, 2),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_b_mux[] = {
|
||||
MSIOF2_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss1_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss1_mux[] = {
|
||||
MSIOF2_SS1_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss2_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(0, 8),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss2_mux[] = {
|
||||
MSIOF2_SS2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_txd_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(0, 4),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_txd_mux[] = {
|
||||
MSIOF2_TXD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_rxd_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(0, 5),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_rxd_mux[] = {
|
||||
MSIOF2_RXD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF3 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof3_clk_a_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(2, 24),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_clk_a_mux[] = {
|
||||
MSIOF3_SCK_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_a_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(2, 21),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_a_mux[] = {
|
||||
MSIOF3_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_a_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(2, 14),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_a_mux[] = {
|
||||
MSIOF3_SS1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_a_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_a_mux[] = {
|
||||
MSIOF3_SS2_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_a_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(2, 22),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_a_mux[] = {
|
||||
MSIOF3_TXD_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_a_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(2, 23),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_a_mux[] = {
|
||||
MSIOF3_RXD_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_clk_b_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_clk_b_mux[] = {
|
||||
MSIOF3_SCK_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_b_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(1, 9),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_b_mux[] = {
|
||||
MSIOF3_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_b_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(1, 6),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_b_mux[] = {
|
||||
MSIOF3_SS1_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_b_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_b_mux[] = {
|
||||
MSIOF3_SS2_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_b_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_b_mux[] = {
|
||||
MSIOF3_TXD_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_b_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_b_mux[] = {
|
||||
MSIOF3_RXD_B_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0 ------------------------------------------------------------------ */
|
||||
static const unsigned int pwm0_a_pins[] = {
|
||||
/* PWM */
|
||||
@ -1752,6 +2036,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
SH_PFC_PIN_GROUP(msiof0_ss1),
|
||||
SH_PFC_PIN_GROUP(msiof0_ss2),
|
||||
SH_PFC_PIN_GROUP(msiof0_txd),
|
||||
SH_PFC_PIN_GROUP(msiof0_rxd),
|
||||
SH_PFC_PIN_GROUP(msiof1_clk),
|
||||
SH_PFC_PIN_GROUP(msiof1_sync),
|
||||
SH_PFC_PIN_GROUP(msiof1_ss1),
|
||||
SH_PFC_PIN_GROUP(msiof1_ss2),
|
||||
SH_PFC_PIN_GROUP(msiof1_txd),
|
||||
SH_PFC_PIN_GROUP(msiof1_rxd),
|
||||
SH_PFC_PIN_GROUP(msiof2_clk),
|
||||
SH_PFC_PIN_GROUP(msiof2_sync_a),
|
||||
SH_PFC_PIN_GROUP(msiof2_sync_b),
|
||||
SH_PFC_PIN_GROUP(msiof2_ss1),
|
||||
SH_PFC_PIN_GROUP(msiof2_ss2),
|
||||
SH_PFC_PIN_GROUP(msiof2_txd),
|
||||
SH_PFC_PIN_GROUP(msiof2_rxd),
|
||||
SH_PFC_PIN_GROUP(msiof3_clk_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_sync_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss1_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss2_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_txd_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_rxd_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_clk_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_sync_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss1_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss2_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_txd_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_rxd_b),
|
||||
SH_PFC_PIN_GROUP(pwm0_a),
|
||||
SH_PFC_PIN_GROUP(pwm0_b),
|
||||
SH_PFC_PIN_GROUP(pwm0_c),
|
||||
@ -1982,6 +2297,49 @@ static const char * const vin4_groups[] = {
|
||||
"vin4_clk",
|
||||
};
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
"msiof0_ss1",
|
||||
"msiof0_ss2",
|
||||
"msiof0_txd",
|
||||
"msiof0_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof1_groups[] = {
|
||||
"msiof1_clk",
|
||||
"msiof1_sync",
|
||||
"msiof1_ss1",
|
||||
"msiof1_ss2",
|
||||
"msiof1_txd",
|
||||
"msiof1_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof2_groups[] = {
|
||||
"msiof2_clk",
|
||||
"msiof2_sync_a",
|
||||
"msiof2_sync_b",
|
||||
"msiof2_ss1",
|
||||
"msiof2_ss2",
|
||||
"msiof2_txd",
|
||||
"msiof2_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof3_groups[] = {
|
||||
"msiof3_clk_a",
|
||||
"msiof3_sync_a",
|
||||
"msiof3_ss1_a",
|
||||
"msiof3_ss2_a",
|
||||
"msiof3_txd_a",
|
||||
"msiof3_rxd_a",
|
||||
"msiof3_clk_b",
|
||||
"msiof3_sync_b",
|
||||
"msiof3_ss1_b",
|
||||
"msiof3_ss2_b",
|
||||
"msiof3_txd_b",
|
||||
"msiof3_rxd_b",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb0),
|
||||
@ -1996,6 +2354,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(mmc),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
SH_PFC_FUNCTION(msiof1),
|
||||
SH_PFC_FUNCTION(msiof2),
|
||||
SH_PFC_FUNCTION(msiof3),
|
||||
SH_PFC_FUNCTION(pwm0),
|
||||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
|
||||
@ -66,6 +66,12 @@ struct sh_pfc_pin_group {
|
||||
.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
|
||||
}
|
||||
|
||||
union vin_data12 {
|
||||
unsigned int data12[12];
|
||||
unsigned int data10[10];
|
||||
unsigned int data8[8];
|
||||
};
|
||||
|
||||
union vin_data16 {
|
||||
unsigned int data16[16];
|
||||
unsigned int data12[12];
|
||||
@ -282,6 +288,7 @@ extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Helper macros to create pin and port lists
|
||||
*/
|
||||
@ -350,6 +357,28 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
|
||||
* an additional select register that controls physical multiplexing
|
||||
* with another pin.
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - psel: Physical multiplexing selector
|
||||
* - msel: Module selector
|
||||
*/
|
||||
#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration in which a pin is physically multiplexed
|
||||
* with other pins.
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - psel: Physical multiplexing selector
|
||||
*/
|
||||
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##psel)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration for a single-function pin with GPIO
|
||||
* capability.
|
||||
@ -397,12 +426,11 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
|
||||
#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
|
||||
#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_11(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
||||
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user