x86: ivybridge: Move lpc_enable() into gma.c

This graphics init code is best placed in the gma init code. Move the code
and drop the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-01-17 16:11:39 -07:00 committed by Bin Meng
parent ddf10c20d2
commit 865c24eea1
4 changed files with 4 additions and 9 deletions

View File

@ -29,7 +29,6 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
hose = pci_bus_to_hose(0);
lpc_enable(PCH_LPC_DEV);
lpc_init_extra(hose, PCH_LPC_DEV);
/* Cause the SATA device to do its init */

View File

@ -806,6 +806,10 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
u32 reg32;
int ret;
/* Enable PCH Display Port */
writew(0x0010, RCB_REG(DISPBDF));
setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
if (!nbridge)
return -ENODEV;

View File

@ -602,13 +602,6 @@ int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev)
return 0;
}
void lpc_enable(pci_dev_t dev)
{
/* Enable PCH Display Port */
writew(0x0010, RCB_REG(DISPBDF));
setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
}
static int bd82x6x_lpc_early_init(struct udevice *dev)
{
/* Setting up Southbridge. In the northbridge code. */

View File

@ -471,6 +471,5 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#define TCO2_STS 0x66
int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev);
void lpc_enable(pci_dev_t dev);
#endif