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pinctrl: rockchip: Add rv1126 support
Add pinctrl driver for Rockchip RV1126. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
Kever Yang
parent
32b2ea9818
commit
8430a87502
@ -15,3 +15,4 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
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obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
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obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
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obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
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obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
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416
drivers/pinctrl/rockchip/pinctrl-rv1126.c
Normal file
416
drivers/pinctrl/rockchip/pinctrl-rv1126.c
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@ -0,0 +1,416 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
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{
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.num = 0,
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.pin = 20,
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.reg = 0x10000,
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.bit = 0,
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.mask = 0xf
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},
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{
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.num = 0,
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.pin = 21,
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.reg = 0x10000,
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.bit = 4,
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.mask = 0xf
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},
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{
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.num = 0,
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.pin = 22,
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.reg = 0x10000,
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.bit = 8,
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.mask = 0xf
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},
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{
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.num = 0,
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.pin = 23,
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.reg = 0x10000,
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.bit = 12,
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.mask = 0xf
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},
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};
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static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
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MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
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MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
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MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
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MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
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MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
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MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
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MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
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MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
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MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
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MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
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MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
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MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
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MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
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MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
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MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
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MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
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MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
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MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
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MR_TOPGRF(RK_GPIO3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
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MR_TOPGRF(RK_GPIO1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
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MR_TOPGRF(RK_GPIO3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
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MR_TOPGRF(RK_GPIO1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
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MR_TOPGRF(RK_GPIO3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
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MR_TOPGRF(RK_GPIO3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
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MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
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MR_TOPGRF(RK_GPIO3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
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MR_TOPGRF(RK_GPIO2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
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MR_TOPGRF(RK_GPIO2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
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MR_PMUGRF(RK_GPIO0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
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MR_PMUGRF(RK_GPIO3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
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MR_PMUGRF(RK_GPIO2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
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MR_PMUGRF(RK_GPIO2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
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MR_PMUGRF(RK_GPIO0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
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MR_PMUGRF(RK_GPIO1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
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MR_PMUGRF(RK_GPIO0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */
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};
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static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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regmap = priv->regmap_pmu;
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else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
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regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
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else
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regmap = priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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if (mux_type & IOMUX_WIDTH_4BIT) {
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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} else {
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bit = (pin % 8) * 2;
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mask = 0x3;
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}
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RV1126_PULL_PMU_OFFSET 0x40
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#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
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#define RV1126_PULL_PINS_PER_REG 8
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#define RV1126_PULL_BITS_PER_PIN 2
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#define RV1126_PULL_BANK_STRIDE 16
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#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
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static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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if (RV1126_GPIO_C4_D7(pin_num)) {
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*regmap = priv->regmap_base;
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*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
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*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
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*bit = pin_num % RV1126_PULL_PINS_PER_REG;
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*bit *= RV1126_PULL_BITS_PER_PIN;
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return;
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}
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*regmap = priv->regmap_pmu;
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*reg = RV1126_PULL_PMU_OFFSET;
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} else {
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*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
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*regmap = priv->regmap_base;
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*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
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}
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*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
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*bit *= RV1126_PULL_BITS_PER_PIN;
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}
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static int rv1126_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -EOPNOTSUPP;
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rv1126_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RV1126_DRV_PMU_OFFSET 0x20
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#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
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#define RV1126_DRV_BITS_PER_PIN 4
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#define RV1126_DRV_PINS_PER_REG 4
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#define RV1126_DRV_BANK_STRIDE 32
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static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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if (RV1126_GPIO_C4_D7(pin_num)) {
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*regmap = priv->regmap_base;
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*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
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*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
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*reg -= 0x4;
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*bit = pin_num % RV1126_DRV_PINS_PER_REG;
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*bit *= RV1126_DRV_BITS_PER_PIN;
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return;
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}
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*regmap = priv->regmap_pmu;
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*reg = RV1126_DRV_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
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*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
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}
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*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RV1126_DRV_PINS_PER_REG;
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*bit *= RV1126_DRV_BITS_PER_PIN;
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}
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static int rv1126_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg;
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u32 data;
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u8 bit;
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rv1126_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (strength << bit);
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return regmap_write(regmap, reg, data);
|
||||
}
|
||||
|
||||
#define RV1126_SCHMITT_PMU_OFFSET 0x60
|
||||
#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
|
||||
#define RV1126_SCHMITT_BANK_STRIDE 16
|
||||
#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
|
||||
#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
|
||||
|
||||
static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num,
|
||||
struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int pins_per_reg;
|
||||
|
||||
if (bank->bank_num == 0) {
|
||||
if (RV1126_GPIO_C4_D7(pin_num)) {
|
||||
*regmap = priv->regmap_base;
|
||||
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
|
||||
*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
|
||||
*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
|
||||
return 0;
|
||||
}
|
||||
*regmap = priv->regmap_pmu;
|
||||
*reg = RV1126_SCHMITT_PMU_OFFSET;
|
||||
pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
|
||||
} else {
|
||||
*regmap = priv->regmap_base;
|
||||
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
|
||||
pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
|
||||
*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
|
||||
}
|
||||
*reg += ((pin_num / pins_per_reg) * 4);
|
||||
*bit = pin_num % pins_per_reg;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rv1126_set_schmitt(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int enable)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg;
|
||||
u8 bit;
|
||||
u32 data;
|
||||
|
||||
rv1126_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = BIT(bit + 16) | (enable << bit);
|
||||
|
||||
return regmap_write(regmap, reg, data);
|
||||
}
|
||||
|
||||
static struct rockchip_pin_bank rv1126_pin_banks[] = {
|
||||
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
|
||||
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
|
||||
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
|
||||
IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
|
||||
IOMUX_WIDTH_4BIT),
|
||||
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
0x10010, 0x10018, 0x10020, 0x10028),
|
||||
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT),
|
||||
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT,
|
||||
IOMUX_WIDTH_4BIT),
|
||||
PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
|
||||
IOMUX_WIDTH_4BIT, 0, 0, 0),
|
||||
};
|
||||
|
||||
static const struct rockchip_pin_ctrl rv1126_pin_ctrl = {
|
||||
.pin_banks = rv1126_pin_banks,
|
||||
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
|
||||
.nr_pins = 130,
|
||||
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
|
||||
.pmu_mux_offset = 0x0,
|
||||
.iomux_routes = rv1126_mux_route_data,
|
||||
.niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
|
||||
.iomux_recalced = rv1126_mux_recalced_data,
|
||||
.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
|
||||
.set_mux = rv1126_set_mux,
|
||||
.set_pull = rv1126_set_pull,
|
||||
.set_drive = rv1126_set_drive,
|
||||
.set_schmitt = rv1126_set_schmitt,
|
||||
};
|
||||
|
||||
static const struct udevice_id rv1126_pinctrl_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rv1126-pinctrl",
|
||||
.data = (ulong)&rv1126_pin_ctrl
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_rv1126) = {
|
||||
.name = "rockchip_rv1126_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = rv1126_pinctrl_ids,
|
||||
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
|
||||
.ops = &rockchip_pinctrl_ops,
|
||||
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
.probe = rockchip_pinctrl_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user