mirror of
https://github.com/u-boot/u-boot.git
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ARM: dts: stratix10: Add base dtsi and devkit dts
From the Linux v4.16-rc4, add the base dtsi and devkit dts files for the Stratix10 SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Dinh Nguyen
Marek Vasut
parent
e74c15bc81
commit
81577a3b04
@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
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socfpga_cyclone5_sockit.dtb \
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socfpga_cyclone5_socrates.dtb \
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socfpga_cyclone5_sr1500.dtb \
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socfpga_stratix10_socdk.dtb \
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socfpga_cyclone5_vining_fpga.dtb
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dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
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381
arch/arm/dts/socfpga_stratix10.dtsi
Normal file
381
arch/arm/dts/socfpga_stratix10.dtsi
Normal file
@ -0,0 +1,381 @@
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/*
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* Copyright (C) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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#include <dt-bindings/reset/altr,rst-mgr-s10.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "altr,socfpga-stratix10";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 120 8>,
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<0 121 8>,
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<0 122 8>,
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<0 123 8>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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interrupt-parent = <&intc>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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intc: intc@fffc1000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0xfffc1000 0x0 0x1000>,
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<0x0 0xfffc2000 0x0 0x2000>,
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<0x0 0xfffc4000 0x0 0x2000>,
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<0x0 0xfffc6000 0x0 0x2000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges = <0 0 0 0xffffffff>;
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clkmgr@ffd1000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd10000 0x1000>;
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};
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff800000 0x2000>;
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interrupts = <0 90 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC0_RESET>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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gmac1: ethernet@ff802000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff802000 0x2000>;
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interrupts = <0 91 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC1_RESET>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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gmac2: ethernet@ff804000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff804000 0x2000>;
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interrupts = <0 92 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC2_RESET>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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gpio0: gpio@ffc03200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc03200 0x100>;
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resets = <&rst GPIO0_RESET>;
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status = "disabled";
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 110 4>;
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};
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};
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gpio1: gpio@ffc03300 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc03300 0x100>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 111 4>;
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};
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};
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i2c0: i2c@ffc02800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02800 0x100>;
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interrupts = <0 103 4>;
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resets = <&rst I2C0_RESET>;
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status = "disabled";
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};
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i2c1: i2c@ffc02900 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02900 0x100>;
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interrupts = <0 104 4>;
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resets = <&rst I2C1_RESET>;
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status = "disabled";
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};
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i2c2: i2c@ffc02a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02a00 0x100>;
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interrupts = <0 105 4>;
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resets = <&rst I2C2_RESET>;
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status = "disabled";
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};
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i2c3: i2c@ffc02b00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02b00 0x100>;
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interrupts = <0 106 4>;
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resets = <&rst I2C3_RESET>;
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status = "disabled";
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};
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i2c4: i2c@ffc02c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02c00 0x100>;
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interrupts = <0 107 4>;
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resets = <&rst I2C4_RESET>;
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status = "disabled";
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};
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mmc: dwmmc0@ff808000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xff808000 0x1000>;
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interrupts = <0 96 4>;
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fifo-depth = <0x400>;
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resets = <&rst SDMMC_RESET>;
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reset-names = "reset";
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status = "disabled";
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};
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ocram: sram@ffe00000 {
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compatible = "mmio-sram";
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reg = <0xffe00000 0x100000>;
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};
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rst: rstmgr@ffd11000 {
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#reset-cells = <1>;
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compatible = "altr,rst-mgr";
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reg = <0xffd11000 0x1000>;
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altr,modrst-offset = <0x20>;
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};
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spi0: spi@ffda4000 {
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compatible = "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xffda4000 0x1000>;
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interrupts = <0 99 4>;
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resets = <&rst SPIM0_RESET>;
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reg-io-width = <4>;
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num-chipselect = <4>;
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bus-num = <0>;
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status = "disabled";
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};
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spi1: spi@ffda5000 {
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compatible = "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xffda5000 0x1000>;
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interrupts = <0 100 4>;
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resets = <&rst SPIM1_RESET>;
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reg-io-width = <4>;
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num-chipselect = <4>;
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bus-num = <0>;
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status = "disabled";
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};
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sysmgr: sysmgr@ffd12000 {
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compatible = "altr,sys-mgr", "syscon";
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reg = <0xffd12000 0x1000>;
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};
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/* Local timer */
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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timer0: timer0@ffc03000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 113 4>;
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reg = <0xffc03000 0x100>;
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};
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timer1: timer1@ffc03100 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 114 4>;
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reg = <0xffc03100 0x100>;
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};
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timer2: timer2@ffd00000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 115 4>;
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reg = <0xffd00000 0x100>;
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};
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timer3: timer3@ffd00100 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 116 4>;
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reg = <0xffd00100 0x100>;
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};
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uart0: serial0@ffc02000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02000 0x100>;
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interrupts = <0 108 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst UART0_RESET>;
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status = "disabled";
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};
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uart1: serial1@ffc02100 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02100 0x100>;
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interrupts = <0 109 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst UART1_RESET>;
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status = "disabled";
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};
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usbphy0: usbphy@0 {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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status = "okay";
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};
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usb0: usb@ffb00000 {
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compatible = "snps,dwc2";
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reg = <0xffb00000 0x40000>;
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interrupts = <0 93 4>;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
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reset-names = "dwc2", "dwc2-ecc";
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status = "disabled";
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};
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usb1: usb@ffb40000 {
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compatible = "snps,dwc2";
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reg = <0xffb40000 0x40000>;
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interrupts = <0 94 4>;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
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reset-names = "dwc2", "dwc2-ecc";
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status = "disabled";
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};
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watchdog0: watchdog@ffd00200 {
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compatible = "snps,dw-wdt";
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reg = <0xffd00200 0x100>;
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interrupts = <0 117 4>;
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resets = <&rst WATCHDOG0_RESET>;
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status = "disabled";
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};
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watchdog1: watchdog@ffd00300 {
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compatible = "snps,dw-wdt";
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reg = <0xffd00300 0x100>;
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interrupts = <0 118 4>;
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resets = <&rst WATCHDOG1_RESET>;
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status = "disabled";
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};
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watchdog2: watchdog@ffd00400 {
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compatible = "snps,dw-wdt";
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reg = <0xffd00400 0x100>;
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interrupts = <0 125 4>;
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resets = <&rst WATCHDOG2_RESET>;
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status = "disabled";
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};
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watchdog3: watchdog@ffd00500 {
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compatible = "snps,dw-wdt";
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reg = <0xffd00500 0x100>;
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interrupts = <0 126 4>;
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resets = <&rst WATCHDOG3_RESET>;
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status = "disabled";
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};
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};
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};
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92
arch/arm/dts/socfpga_stratix10_socdk.dts
Normal file
92
arch/arm/dts/socfpga_stratix10_socdk.dts
Normal file
@ -0,0 +1,92 @@
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/*
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* Copyright (C) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include "socfpga_stratix10.dtsi"
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/ {
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model = "SoCFPGA Stratix 10 SoCDK";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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max-frame-size = <3800>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <1860>; /* 960ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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};
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};
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};
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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