mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-25 13:14:19 +08:00
Code Issues Packages Projects Releases Wiki Activity

85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN

Browse Source 
This config option is for an erratum workaround; rename it to be more
clear.  Also, drop it from config files don't need it and were
undefining it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Becky Bruce 2010-12-17 17:17:58 -06:00 committed by Kumar Gala
parent 70961ba414
commit 810c442749
12 changed files with 11 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -46,6 +46,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif
return 0;
}

2
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -293,7 +293,7 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
#if defined(CONFIG_DDR_DLL)
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int x = 10;

4
doc/README.mpc85xxads
View File

@ -144,8 +144,8 @@ Updated 13-July-2004 Jon Loeliger
also manual config the DDR after undef this
definition.
CONFIG_DDR_ECC only for ECC DDR module
CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
stability.
CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed
for more stability.
CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
Other than the above definitions, the rest in the config files are

1
include/configs/MPC8536DS.h
View File

@ -144,7 +144,6 @@
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

2
include/configs/MPC8548CDS.h
View File

@ -89,7 +89,7 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/MPC8572DS.h
View File

@ -131,7 +131,6 @@
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/P1_P2_RDB.h
View File

@ -146,7 +146,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

2
include/configs/SBC8540.h
View File

@ -118,7 +118,7 @@
#undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1)
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */

2
include/configs/TQM85xx.h
View File

@ -162,7 +162,7 @@
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
#define CONFIG_DDR_DLL /* DLL fix needed */
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */

2
include/configs/sbc8560.h
View File

@ -116,7 +116,7 @@
#undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1)
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */

2
include/configs/stxgp3.h
View File

@ -123,7 +123,7 @@
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/stxssa.h
View File

@ -135,7 +135,6 @@
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef