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arch: mach-k3: introduce basic files to support the am62px SoC family
Introduce the basic functions and definitions needed to properly initialize TI's am62p family of SoCs Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Bryan Brattlof
Tom Rini
parent
e61755001e
commit
7f88327e94
@ -10,6 +10,9 @@ config SOC_K3_AM625
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config SOC_K3_AM62A7
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bool "TI's K3 based AM62A7 SoC Family Support"
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config SOC_K3_AM62P5
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bool "TI's K3 based AM62P5 SoC Family Support"
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config SOC_K3_AM642
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bool "TI's K3 based AM642 SoC Family Support"
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@ -80,6 +83,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
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default 0x43c3f290 if SOC_K3_AM625
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default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
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default 0x7000f290 if SOC_K3_AM62A7 && ARM64
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default 0x43c4f290 if SOC_K3_AM62P5
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help
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Address at which ROM stores the value which determines if SPL
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is booted up by primary boot media or secondary boot media.
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@ -118,7 +122,7 @@ config K3_EARLY_CONS_IDX
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config K3_ATF_LOAD_ADDR
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hex "Load address of ATF image"
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default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7)
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default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5)
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default 0x70000000
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help
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The load address for the ATF image. This value is used to build the
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@ -156,6 +160,7 @@ source "arch/arm/mach-k3/am65x/Kconfig"
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source "arch/arm/mach-k3/am64x/Kconfig"
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source "arch/arm/mach-k3/am62x/Kconfig"
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source "arch/arm/mach-k3/am62ax/Kconfig"
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source "arch/arm/mach-k3/am62px/Kconfig"
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source "arch/arm/mach-k3/j721e/Kconfig"
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source "arch/arm/mach-k3/j721s2/Kconfig"
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source "arch/arm/mach-k3/j784s4/Kconfig"
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@ -22,5 +22,6 @@ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
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obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
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obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
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obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
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obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o
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endif
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obj-y += common.o security.o
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281
arch/arm/mach-k3/am62p5_init.c
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281
arch/arm/mach-k3/am62p5_init.c
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@ -0,0 +1,281 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* AM62P5: SoC specific initialization
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*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include "sysfw-loader.h"
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#include "common.h"
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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struct fwl_data cbass_main_fwls[] = {
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{ "FSS_DAT_REG3", 7, 8 },
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};
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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* it to the .data section.
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*/
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u32 bootindex __section(".data");
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static struct rom_extended_boot_data bootdata __section(".data");
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static void store_boot_info_from_rom(void)
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{
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bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
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sizeof(struct rom_extended_boot_data));
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}
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 4);
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mmr_unlock(CTRL_MMR0_BASE, 5);
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mmr_unlock(CTRL_MMR0_BASE, 6);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
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/* Unlock PADCFG_CTRL_MMR padconf registers */
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mmr_unlock(PADCFG_MMR0_BASE, 1);
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mmr_unlock(PADCFG_MMR1_BASE, 1);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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if (IS_ENABLED(CONFIG_CPU_V7R))
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setup_k3_mpu_regions();
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/*
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* Cannot delay this further as there is a chance that
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* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
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*/
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store_boot_info_from_rom();
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ctrl_mmr_unlock();
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/* Init DM early */
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ret = spl_early_init();
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if (ret)
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panic("spl_early_init() failed: %d\n", ret);
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/*
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* Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
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* MAIN_UART1 modules and continue regardless of the result of pinctrl.
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* Do this without probing the device, but instead by searching the
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* device that would request the given sequence number if probed. The
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* UARTs will be used by the DM firmware and TIFS firmware images
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* respectively and the firmware depend on SPL to initialize the pin
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* settings.
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*/
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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/*
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* Allow establishing an early console as required for example when
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* doing a UART-based boot. Note that this console may not "survive"
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* through a SYSFW PM-init step and will need a re-init in some way
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* due to changing module clock frequencies.
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*/
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if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) {
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ret = early_console_init();
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if (ret)
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panic("early_console_init() failed: %d\n", ret);
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}
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/*
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* Configure and start up system controller firmware. Provide
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* the U-Boot console init function to the SYSFW post-PM configuration
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* callback hook, effectively switching on (or over) the console
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* output.
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*/
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if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
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ret = is_rom_loaded_sysfw(&bootdata);
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if (!ret)
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panic("ROM has not loaded TIFS firmware\n");
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k3_sysfw_loader(true, NULL, NULL);
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/* Disable ROM configured firewalls */
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remove_fwl_configs(cbass_main_fwls,
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ARRAY_SIZE(cbass_main_fwls));
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}
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/*
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* Force probe of clk_k3 driver here to ensure basic default clock
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* configuration is always done.
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*/
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if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(ti_clk),
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&dev);
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if (ret)
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printf("Failed to initialize clk-k3!\n");
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}
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preloader_console_init();
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/* Output System Firmware version info */
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k3_sysfw_print_ver();
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if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) {
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret)
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panic("DRAM init failed: %d\n", ret);
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}
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spl_enable_cache();
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debug("am62px_init: %s done\n", __func__);
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
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u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
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switch (bootmode) {
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case BOOT_DEVICE_EMMC:
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return MMCSD_MODE_EMMCBOOT;
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case BOOT_DEVICE_MMC:
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if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
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return MMCSD_MODE_RAW;
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default:
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return MMCSD_MODE_FS;
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}
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}
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static u32 __get_backup_bootmedia(u32 devstat)
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{
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u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
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u32 bkup_bootmode_cfg =
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(devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
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switch (bkup_bootmode) {
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case BACKUP_BOOT_DEVICE_UART:
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return BOOT_DEVICE_UART;
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case BACKUP_BOOT_DEVICE_USB:
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return BOOT_DEVICE_USB;
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case BACKUP_BOOT_DEVICE_ETHERNET:
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return BOOT_DEVICE_ETHERNET;
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case BACKUP_BOOT_DEVICE_MMC:
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if (bkup_bootmode_cfg)
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1;
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case BACKUP_BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BACKUP_BOOT_DEVICE_I2C:
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return BOOT_DEVICE_I2C;
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case BACKUP_BOOT_DEVICE_DFU:
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if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
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return BOOT_DEVICE_USB;
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return BOOT_DEVICE_DFU;
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};
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return BOOT_DEVICE_RAM;
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}
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static u32 __get_primary_bootmedia(u32 devstat)
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{
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u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
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u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
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switch (bootmode) {
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case BOOT_DEVICE_OSPI:
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fallthrough;
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case BOOT_DEVICE_QSPI:
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fallthrough;
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case BOOT_DEVICE_XSPI:
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fallthrough;
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case BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BOOT_DEVICE_ETHERNET_RGMII:
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fallthrough;
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case BOOT_DEVICE_ETHERNET_RMII:
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return BOOT_DEVICE_ETHERNET;
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case BOOT_DEVICE_EMMC:
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return BOOT_DEVICE_MMC1;
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case BOOT_DEVICE_SPI_NAND:
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return BOOT_DEVICE_SPINAND;
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case BOOT_DEVICE_MMC:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
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MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1;
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case BOOT_DEVICE_DFU:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
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return BOOT_DEVICE_USB;
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return BOOT_DEVICE_DFU;
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case BOOT_DEVICE_NOBOOT:
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return BOOT_DEVICE_RAM;
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}
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return bootmode;
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}
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u32 spl_boot_device(void)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmedia;
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if (bootindex == K3_PRIMARY_BOOTMODE)
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bootmedia = __get_primary_bootmedia(devstat);
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else
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bootmedia = __get_backup_bootmedia(devstat);
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debug("am62px_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
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__func__, devstat, bootmedia, bootindex);
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return bootmedia;
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}
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32
arch/arm/mach-k3/am62px/Kconfig
Normal file
32
arch/arm/mach-k3/am62px/Kconfig
Normal file
@ -0,0 +1,32 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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#
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if SOC_K3_AM62P5
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choice
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prompt "TI K3 AM62Px based boards"
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optional
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config TARGET_AM62P5_A53_EVM
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bool "TI K3 based AM62P5 EVM running on A53"
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select ARM64
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select BINMAN
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config TARGET_AM62P5_R5_EVM
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bool "TI K3 based AM62P5 EVM running on R5"
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select CPU_V7R
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select SYS_THUMB_BUILD
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select K3_LOAD_SYSFW
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select RAM
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select SPL_RAM
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select K3_DDRSS
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select BINMAN
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imply SYS_K3_SPL_ATF
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endchoice
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source "board/ti/am62px/Kconfig"
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endif
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83
arch/arm/mach-k3/include/mach/am62p_hardware.h
Normal file
83
arch/arm/mach-k3/include/mach/am62p_hardware.h
Normal file
@ -0,0 +1,83 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM62Px SoC definitions, structures etc.
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __ASM_ARCH_AM62P_HARDWARE_H
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#define __ASM_ARCH_AM62P_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define PADCFG_MMR0_BASE 0x04080000
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#define PADCFG_MMR1_BASE 0x000f0000
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#define CTRL_MMR0_BASE 0x00100000
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#define MCU_CTRL_MMR0_BASE 0x04500000
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
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/* Primary Bootmode MMC Config macros */
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
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#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
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/* Primary Bootmode USB Config macros */
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
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/* Backup Bootmode USB Config macros */
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#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
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* shared register definitions. The same registers are also used for
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* PADCFG_MMR lock/kick-mechanism.
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*/
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#define CTRLMMR_LOCK_KICK0 0x1008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK1 0x100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
|
||||
#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
|
||||
#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
|
||||
|
||||
#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
|
||||
#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
|
||||
|
||||
#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c4f1e0
|
||||
|
||||
#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
|
||||
|
||||
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
|
||||
|
||||
#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
|
||||
|
||||
static const u32 put_device_ids[] = {};
|
||||
|
||||
static const u32 put_core_ids[] = {};
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_AM62P_HARDWARE_H */
|
||||
49
arch/arm/mach-k3/include/mach/am62p_spl.h
Normal file
49
arch/arm/mach-k3/include/mach/am62p_spl.h
Normal file
@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_AM62P_SPL_H_
|
||||
#define _ASM_ARCH_AM62P_SPL_H_
|
||||
|
||||
/* Primary BootMode devices */
|
||||
#define BOOT_DEVICE_SPI_NAND 0x00
|
||||
#define BOOT_DEVICE_RAM 0xFF
|
||||
#define BOOT_DEVICE_OSPI 0x01
|
||||
#define BOOT_DEVICE_QSPI 0x02
|
||||
#define BOOT_DEVICE_SPI 0x03
|
||||
#define BOOT_DEVICE_CPGMAC 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RGMII 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RMII 0x05
|
||||
#define BOOT_DEVICE_I2C 0x06
|
||||
#define BOOT_DEVICE_UART 0x07
|
||||
#define BOOT_DEVICE_MMC 0x08
|
||||
#define BOOT_DEVICE_EMMC 0x09
|
||||
|
||||
#define BOOT_DEVICE_USB 0x2A
|
||||
#define BOOT_DEVICE_DFU 0x0A
|
||||
#define BOOT_DEVICE_GPMC_NAND 0x0B
|
||||
#define BOOT_DEVICE_GPMC_NOR 0x0C
|
||||
#define BOOT_DEVICE_XSPI 0x0E
|
||||
#define BOOT_DEVICE_NOBOOT 0x0F
|
||||
|
||||
/* U-Boot used aliases */
|
||||
#define BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BOOT_DEVICE_SPINAND 0x10
|
||||
#define BOOT_DEVICE_MMC2 0x08
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
/* Invalid */
|
||||
#define BOOT_DEVICE_MMC2_2 0x1F
|
||||
|
||||
/* Backup BootMode devices */
|
||||
#define BACKUP_BOOT_DEVICE_DFU 0x01
|
||||
#define BACKUP_BOOT_DEVICE_UART 0x03
|
||||
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BACKUP_BOOT_DEVICE_MMC 0x05
|
||||
#define BACKUP_BOOT_DEVICE_SPI 0x06
|
||||
#define BACKUP_BOOT_DEVICE_I2C 0x07
|
||||
#define BACKUP_BOOT_DEVICE_USB 0x09
|
||||
|
||||
#define K3_PRIMARY_BOOTMODE 0x0
|
||||
|
||||
#endif /* _ASM_ARCH_AM62P_SPL_H_ */
|
||||
@ -36,6 +36,10 @@
|
||||
#include "j784s4_hardware.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM62P5
|
||||
#include "am62p_hardware.h"
|
||||
#endif
|
||||
|
||||
/* Assuming these addresses and definitions stay common across K3 devices */
|
||||
#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
|
||||
#define JTAG_ID_VARIANT_SHIFT 28
|
||||
|
||||
@ -34,4 +34,8 @@
|
||||
#include "j784s4_spl.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM62P5
|
||||
#include "am62p_spl.h"
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARCH_SPL_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user