mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-29 15:43:44 +08:00
Code Issues Packages Projects Releases Wiki Activity

global: Migrate CONFIG_SH_ETHER_PHY_ADDR to CFG

Browse Source 
Perform a simple rename of CONFIG_SH_ETHER_PHY_ADDR to CFG_SH_ETHER_PHY_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:13:50 -05:00
parent ff53ecc387
commit 7c480bab14
11 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -544,7 +544,7 @@ The following options need to be configured:
CONFIG_SH_ETHER_USE_PORT
Define the number of ports to be used
CONFIG_SH_ETHER_PHY_ADDR
CFG_SH_ETHER_PHY_ADDR
Define the ETH PHY's address
CFG_SH_ETHER_CACHE_WRITEBACK

6
drivers/net/sh_eth.c
View File

@ -33,8 +33,8 @@
#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#endif
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#ifndef CFG_SH_ETHER_PHY_ADDR
# error "Please define CFG_SH_ETHER_PHY_ADDR"
#endif
#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \
@ -694,7 +694,7 @@ static int sh_ether_probe(struct udevice *udev)
priv->bus = miiphy_get_dev_by_name(udev->name);
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
(void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);

2
include/configs/alt.h
View File

@ -22,7 +22,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/condor.h
View File

@ -15,7 +15,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/gose.h
View File

@ -21,7 +21,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/grpeach.h
View File

@ -18,7 +18,7 @@
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0
#define CFG_SH_ETHER_PHY_ADDR 0
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/koelsch.h
View File

@ -21,7 +21,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/lager.h
View File

@ -22,7 +22,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/porter.h
View File

@ -23,7 +23,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/silk.h
View File

@ -23,7 +23,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE

2
include/configs/stout.h
View File

@ -27,7 +27,7 @@
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE