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https://github.com/u-boot/u-boot.git
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spi: atmel: Drop non-dm code
All board configs are now enabled DM_SPI for SPL and U-Boot proper, so now its time to drop non-dm code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
This commit is contained in:
Jagan Teki
Tom Rini
parent
5a6eab8ab0
commit
7b09477873
@ -26,206 +26,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_DM_SPI
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static int spi_has_wdrbt(struct atmel_spi_slave *slave)
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{
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unsigned int ver;
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ver = spi_readl(slave, VERSION);
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return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
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}
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void spi_init()
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{
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct atmel_spi_slave *as;
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unsigned int scbr;
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u32 csrx;
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void *regs;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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switch (bus) {
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case 0:
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regs = (void *)ATMEL_BASE_SPI0;
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break;
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#ifdef ATMEL_BASE_SPI1
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case 1:
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regs = (void *)ATMEL_BASE_SPI1;
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break;
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#endif
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#ifdef ATMEL_BASE_SPI2
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case 2:
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regs = (void *)ATMEL_BASE_SPI2;
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break;
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#endif
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#ifdef ATMEL_BASE_SPI3
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case 3:
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regs = (void *)ATMEL_BASE_SPI3;
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break;
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#endif
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default:
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return NULL;
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}
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scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
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if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
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/* Too low max SCK rate */
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return NULL;
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if (scbr < 1)
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scbr = 1;
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csrx = ATMEL_SPI_CSRx_SCBR(scbr);
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csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
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if (!(mode & SPI_CPHA))
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csrx |= ATMEL_SPI_CSRx_NCPHA;
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if (mode & SPI_CPOL)
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csrx |= ATMEL_SPI_CSRx_CPOL;
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as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
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if (!as)
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return NULL;
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as->regs = regs;
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as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
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| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
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if (spi_has_wdrbt(as))
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as->mr |= ATMEL_SPI_MR_WDRBT;
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spi_writel(as, CSR(cs), csrx);
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return &as->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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free(as);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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/* Enable the SPI hardware */
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spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
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/*
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* Select the slave. This should set SCK to the correct
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* initial state, etc.
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*/
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spi_writel(as, MR, as->mr);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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/* Disable the SPI hardware */
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spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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unsigned int len_tx;
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unsigned int len_rx;
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unsigned int len;
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u32 status;
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const u8 *txp = dout;
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u8 *rxp = din;
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u8 value;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* TODO: The controller can do non-multiple-of-8 bit
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* transfers, but this driver currently doesn't support it.
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*
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* It's also not clear how such transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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/*
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* The controller can do automatic CS control, but it is
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* somewhat quirky, and it doesn't really buy us much anyway
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* in the context of U-Boot.
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*/
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if (flags & SPI_XFER_BEGIN) {
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spi_cs_activate(slave);
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/*
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* sometimes the RDR is not empty when we get here,
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* in theory that should not happen, but it DOES happen.
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* Read it here to be on the safe side.
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* That also clears the OVRES flag. Required if the
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* following loop exits due to OVRES!
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*/
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spi_readl(as, RDR);
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}
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for (len_tx = 0, len_rx = 0; len_rx < len; ) {
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status = spi_readl(as, SR);
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if (status & ATMEL_SPI_SR_OVRES)
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return -1;
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if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
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if (txp)
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value = *txp++;
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else
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value = 0;
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spi_writel(as, TDR, value);
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len_tx++;
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}
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if (status & ATMEL_SPI_SR_RDRF) {
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value = spi_readl(as, RDR);
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if (rxp)
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*rxp++ = value;
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len_rx++;
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}
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}
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out:
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if (flags & SPI_XFER_END) {
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/*
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* Wait until the transfer is completely done before
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* we deactivate CS.
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*/
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do {
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status = spi_readl(as, SR);
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} while (!(status & ATMEL_SPI_SR_TXEMPTY));
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spi_cs_deactivate(slave);
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}
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return 0;
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}
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#else
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#define MAX_CS_COUNT 4
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struct atmel_spi_platdata {
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@ -515,4 +315,3 @@ U_BOOT_DRIVER(atmel_spi) = {
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.priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
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.probe = atmel_spi_probe,
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};
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#endif
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@ -79,22 +79,6 @@
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#define ATMEL_SPI_BITS_16 8
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struct atmel_spi_slave {
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struct spi_slave slave;
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void *regs;
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u32 mr;
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};
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static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct atmel_spi_slave, slave);
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}
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/* Register access macros */
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#define spi_readl(as, reg) \
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readl(as->regs + ATMEL_SPI_##reg)
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#define spi_writel(as, reg, value) \
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writel(value, as->regs + ATMEL_SPI_##reg)
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#if !defined(CONFIG_SYS_SPI_WRITE_TOUT)
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#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
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#endif
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@ -87,7 +87,6 @@
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*/
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#ifdef CONFIG_CMD_SF
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#define CONFIG_ATMEL_SPI
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#define CONFIG_ATMEL_SPI0
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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@ -39,7 +39,6 @@
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#ifdef CONFIG_CMD_SF
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#define CONFIG_ATMEL_SPI
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#define CONFIG_ATMEL_SPI0
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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@ -103,7 +103,6 @@ CONFIG_ATMEL_LEGACY
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CONFIG_ATMEL_MCI_8BIT
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CONFIG_ATMEL_NAND_HWECC
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CONFIG_ATMEL_NAND_HW_PMECC
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CONFIG_ATMEL_SPI0
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CONFIG_AT_TRANS
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CONFIG_AUTO_ZRELADDR
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CONFIG_BACKSIDE_L2_CACHE
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