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powerpc/85xx: Fix synchronization of timebase on MP boot

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There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0.  We can simply just read back the value to
synchronizatize the write, before we set TB to 0.

Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-03-13 10:55:53 -05:00
parent cc1dd33f27
commit 7afc45ad7d
1 changed files with 9 additions and 0 deletions
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9
arch/powerpc/cpu/mpc85xx/mp.c
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@ -276,8 +276,13 @@ static void plat_mp_up(unsigned long bootpg)
/* enable time base at the platform */
out_be32(&rcpm->ctbenrl, 0);
/* readback to sync write */
in_be32(&rcpm->ctbenrl);
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
@ -347,6 +352,10 @@ static void plat_mp_up(unsigned long bootpg)
else
devdisr |= MPC85xx_DEVDISR_TB0;
out_be32(&gur->devdisr, devdisr);
/* readback to sync write */
in_be32(&gur->devdisr);
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);