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https://github.com/u-boot/u-boot.git
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imx: ventana: add HDMI and LVDS display capability
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey
Stefano Babic
parent
effb7dc6d9
commit
7a278f9f1b
@ -12,6 +12,7 @@
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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@ -19,6 +20,7 @@
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/sata.h>
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#include <asm/imx-common/video.h>
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#include <jffs2/load_kernel.h>
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#include <hwconfig.h>
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#include <i2c.h>
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@ -369,6 +371,134 @@ int board_eth_init(bd_t *bis)
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return 0;
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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static void enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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static int detect_i2c(struct display_info_t const *dev)
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{
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return i2c_set_bus_num(dev->bus) == 0 &&
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i2c_probe(dev->addr) == 0;
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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struct iomuxc *iomux = (struct iomuxc *)
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IOMUXC_BASE_ADDR;
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/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
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u32 reg = readl(&iomux->gpr[2]);
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reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
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writel(reg, &iomux->gpr[2]);
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/* Enable Backlight */
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imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
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MUX_PAD_CTRL(NO_PAD_CTRL));
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gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
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}
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struct display_info_t const displays[] = {{
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/* HDMI Output */
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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/* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
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.bus = 2,
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.addr = 0x4,
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.pixfmt = IPU_PIX_FMT_LVDS666,
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.detect = detect_i2c,
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.enable = enable_lvds,
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.mode = {
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.name = "Hannstar-XGA",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* Turn on LDB0,IPU,IPU DI0 clocks */
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reg = __raw_readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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/* set LDB0, LDB1 clk select to 011/011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
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|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
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|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
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|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
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|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
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|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
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|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
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|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
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|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
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|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
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| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
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<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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/* Backlight CABEN on LVDS connector */
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imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
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MUX_PAD_CTRL(NO_PAD_CTRL));
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gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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/* read ventana EEPROM, check for validity, and return baseboard type */
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static int
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read_eeprom(void)
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@ -944,6 +1074,9 @@ int board_early_init_f(void)
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setup_iomux_uart();
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gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
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#if defined(CONFIG_VIDEO_IPUV3)
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setup_display();
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#endif
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return 0;
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}
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@ -194,6 +194,22 @@
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#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
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#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
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/* Framebuffer and LCD */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_CMD_HDMIDETECT
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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/* serial console (ttymxc1,115200) */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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