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mmc: rockchip: add SDHCI driver support for rockchip soc

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Rockchip rk3399 using arasan sdhci-5.1 controller.
This patch add the controller support to enable mmc device
with full driver-model support, tested on rk3399 evb board.

According to my test result, this driver should be OK,
the command "part list mmc 0" can result in a right output,
but all the mmc command failed like this:
	=> mmc info
	No MMC device available
	Command failed, result=1

The result of get_mmc_num in cmd/mmc.c is always 0?

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Kever Yang 2016-07-18 17:00:58 +08:00 committed by Simon Glass
parent d26f375ae4
commit 79c830653b
3 changed files with 100 additions and 0 deletions
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6
drivers/mmc/Kconfig
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@ -61,6 +61,12 @@ config ZYNQ_SDHCI
help
Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
config ROCKCHIP_SDHCI
bool "Arasan SDHCI controller for Rockchip support"
depends on DM_MMC && BLK && DM_MMC_OPS
help
Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER

1
drivers/mmc/Makefile
View File

@ -56,6 +56,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o

93
drivers/mmc/rockchip_sdhci.c Normal file
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@ -0,0 +1,93 @@
/*
* (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* Rockchip SD Host Controller Interface
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
/* 400KHz is max freq for card ID etc. Use that as min */
#define EMMC_MIN_FREQ 400000
struct rockchip_sdhc_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct rockchip_sdhc {
struct sdhci_host host;
void *base;
};
static int arasan_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
int ret;
u32 caps;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
caps, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, EMMC_MIN_FREQ,
host->version, host->quirks, 0);
host->mmc = &plat->mmc;
if (ret)
return ret;
host->mmc->priv = &prv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
}
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name;
host->ioaddr = dev_get_addr_ptr(dev);
return 0;
}
static int rockchip_sdhci_bind(struct udevice *dev)
{
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
int ret;
ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
if (ret)
return ret;
return 0;
}
static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-5.1" },
{ }
};
U_BOOT_DRIVER(arasan_sdhci_drv) = {
.name = "arasan_sdhci",
.id = UCLASS_MMC,
.of_match = arasan_sdhci_ids,
.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
.ops = &sdhci_ops,
.bind = rockchip_sdhci_bind,
.probe = arasan_sdhci_probe,
.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
};