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https://github.com/u-boot/u-boot.git
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ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
Synchronize the Amlogic AXG Device Tree files and bindings include from the recent Linux 4.20-rc1, because it includes patches fixing support for U-boot. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
parent
485bba395e
commit
78a08019cd
@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_MESON) += \
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meson-gxl-s905x-p212.dtb \
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meson-gxl-s905x-libretech-cc.dtb \
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meson-gxl-s905x-khadas-vim.dtb \
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meson-gxm-khadas-vim2.dtb
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meson-gxm-khadas-vim2.dtb \
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meson-axg-s400.dtb
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dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra20-medcom-wide.dtb \
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tegra20-paz00.dtb \
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554
arch/arm/dts/meson-axg-s400.dts
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554
arch/arm/dts/meson-axg-s400.dts
Normal file
@ -0,0 +1,554 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "meson-axg.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
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model = "Amlogic Meson AXG S400 Development Board";
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adc_keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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button-next {
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label = "Next";
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linux,code = <KEY_NEXT>;
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press-threshold-microvolt = <1116000>; /* 62% */
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};
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button-prev {
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label = "Previous";
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linux,code = <KEY_PREVIOUS>;
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press-threshold-microvolt = <900000>; /* 50% */
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};
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button-wifi {
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label = "Wifi";
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linux,code = <KEY_WLAN>;
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press-threshold-microvolt = <684000>; /* 38% */
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};
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button-up {
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label = "Volume Up";
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linux,code = <KEY_VOLUMEUP>;
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press-threshold-microvolt = <468000>; /* 26% */
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};
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button-down {
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label = "Volume Down";
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linux,code = <KEY_VOLUMEDOWN>;
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press-threshold-microvolt = <252000>; /* 14% */
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};
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button-voice {
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label = "Voice";
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linux,code = <KEY_VOICECOMMAND>;
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press-threshold-microvolt = <0>; /* 0% */
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};
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};
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aliases {
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serial0 = &uart_AO;
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serial1 = &uart_A;
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};
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linein: audio-codec@0 {
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#sound-dai-cells = <0>;
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compatible = "everest,es7241";
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VDDA-supply = <&vcc_3v3>;
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VDDP-supply = <&vcc_3v3>;
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VDDD-supply = <&vcc_3v3>;
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status = "okay";
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sound-name-prefix = "Linein";
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};
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lineout: audio-codec@1 {
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#sound-dai-cells = <0>;
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compatible = "everest,es7154";
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VDD-supply = <&vcc_3v3>;
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PVDD-supply = <&vcc_5v>;
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status = "okay";
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sound-name-prefix = "Lineout";
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};
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spdif_dit: audio-codec@2 {
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#sound-dai-cells = <0>;
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compatible = "linux,spdif-dit";
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status = "okay";
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sound-name-prefix = "DIT";
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};
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dmics: audio-codec@3 {
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#sound-dai-cells = <0>;
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compatible = "dmic-codec";
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num-channels = <7>;
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wakeup-delay-ms = <50>;
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status = "okay";
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sound-name-prefix = "MIC";
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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main_12v: regulator-main_12v {
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compatible = "regulator-fixed";
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regulator-name = "12V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-always-on;
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};
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vcc_3v3: regulator-vcc_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VCC_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vddao_3v3>;
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regulator-always-on;
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};
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vcc_5v: regulator-vcc_5v {
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compatible = "regulator-fixed";
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regulator-name = "VCC5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&main_12v>;
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gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vddao_3v3: regulator-vddao_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VDDAO_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&main_12v>;
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regulator-always-on;
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};
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vddio_ao18: regulator-vddio_ao18 {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_AO18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vddao_3v3>;
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regulator-always-on;
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};
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vddio_boot: regulator-vddio_boot {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_BOOT";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vddao_3v3>;
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regulator-always-on;
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};
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usb_pwr: regulator-usb_pwr {
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compatible = "regulator-fixed";
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regulator-name = "USB_PWR";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc_5v>;
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gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
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clocks = <&wifi32k>;
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clock-names = "ext_clock";
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};
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speaker-leds {
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compatible = "gpio-leds";
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aled1 {
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label = "speaker:aled1";
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gpios = <&gpio_speaker 7 0>;
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};
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aled2 {
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label = "speaker:aled2";
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gpios = <&gpio_speaker 6 0>;
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};
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aled3 {
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label = "speaker:aled3";
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gpios = <&gpio_speaker 5 0>;
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};
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aled4 {
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label = "speaker:aled4";
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gpios = <&gpio_speaker 4 0>;
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};
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aled5 {
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label = "speaker:aled5";
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gpios = <&gpio_speaker 3 0>;
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};
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aled6 {
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label = "speaker:aled6";
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gpios = <&gpio_speaker 2 0>;
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};
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};
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sound {
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compatible = "amlogic,axg-sound-card";
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model = "AXG-S400";
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audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
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<&tdmin_lb>, <&tdmout_c>;
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audio-widgets = "Line", "Lineout",
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"Line", "Linein",
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"Speaker", "Speaker1 Left",
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"Speaker", "Speaker1 Right";
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audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
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"SPDIFOUT IN 0", "FRDDR_A OUT 3",
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"TDMOUT_C IN 1", "FRDDR_B OUT 2",
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"SPDIFOUT IN 1", "FRDDR_B OUT 3",
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"TDMOUT_C IN 2", "FRDDR_C OUT 2",
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"SPDIFOUT IN 2", "FRDDR_C OUT 3",
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"TDM_C Playback", "TDMOUT_C OUT",
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"TDMIN_A IN 2", "TDM_C Capture",
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"TDMIN_A IN 5", "TDM_C Loopback",
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"TDMIN_B IN 2", "TDM_C Capture",
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"TDMIN_B IN 5", "TDM_C Loopback",
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"TDMIN_C IN 2", "TDM_C Capture",
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"TDMIN_C IN 5", "TDM_C Loopback",
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"TDMIN_LB IN 2", "TDM_C Loopback",
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"TDMIN_LB IN 5", "TDM_C Capture",
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"TODDR_A IN 0", "TDMIN_A OUT",
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"TODDR_B IN 0", "TDMIN_A OUT",
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"TODDR_C IN 0", "TDMIN_A OUT",
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"TODDR_A IN 1", "TDMIN_B OUT",
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"TODDR_B IN 1", "TDMIN_B OUT",
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"TODDR_C IN 1", "TDMIN_B OUT",
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"TODDR_A IN 2", "TDMIN_C OUT",
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"TODDR_B IN 2", "TDMIN_C OUT",
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"TODDR_C IN 2", "TDMIN_C OUT",
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"TODDR_A IN 4", "PDM Capture",
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"TODDR_B IN 4", "PDM Capture",
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"TODDR_C IN 4", "PDM Capture",
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"TODDR_A IN 6", "TDMIN_LB OUT",
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"TODDR_B IN 6", "TDMIN_LB OUT",
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"TODDR_C IN 6", "TDMIN_LB OUT",
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"Lineout", "Lineout AOUTL",
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"Lineout", "Lineout AOUTR",
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"Speaker1 Left", "SPK1 OUT_A",
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"Speaker1 Left", "SPK1 OUT_B",
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"Speaker1 Right", "SPK1 OUT_C",
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"Speaker1 Right", "SPK1 OUT_D",
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"Linein AINL", "Linein",
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"Linein AINR", "Linein";
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assigned-clocks = <&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>;
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assigned-clock-parents = <0>, <0>, <0>;
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assigned-clock-rates = <589824000>,
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<270950400>,
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<393216000>;
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status = "okay";
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dai-link@0 {
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sound-dai = <&frddr_a>;
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};
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dai-link@1 {
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sound-dai = <&frddr_b>;
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};
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dai-link@2 {
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sound-dai = <&frddr_c>;
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};
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dai-link@3 {
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sound-dai = <&toddr_a>;
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};
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dai-link@4 {
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sound-dai = <&toddr_b>;
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};
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dai-link@5 {
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sound-dai = <&toddr_c>;
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};
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dai-link@6 {
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sound-dai = <&tdmif_c>;
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dai-format = "i2s";
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dai-tdm-slot-tx-mask-2 = <1 1>;
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dai-tdm-slot-rx-mask-1 = <1 1>;
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mclk-fs = <256>;
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codec@0 {
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sound-dai = <&lineout>;
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};
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codec@1 {
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sound-dai = <&speaker_amp1>;
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};
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codec@2 {
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sound-dai = <&linein>;
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};
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};
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dai-link@7 {
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sound-dai = <&spdifout>;
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codec {
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sound-dai = <&spdif_dit>;
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};
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};
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dai-link@8 {
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sound-dai = <&pdm>;
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codec {
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sound-dai = <&dmics>;
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};
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};
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};
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wifi32k: wifi32k {
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compatible = "pwm-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
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};
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_rgmii_y_pins>;
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pinctrl-names = "default";
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phy-handle = <ð_phy0>;
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phy-mode = "rgmii";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy0: ethernet-phy@0 {
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/* Realtek RTL8211F (0x001cc916) */
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reg = <0>;
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eee-broken-1000t;
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};
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};
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};
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&frddr_a {
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status = "okay";
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};
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&frddr_b {
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status = "okay";
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};
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&frddr_c {
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status = "okay";
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};
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&ir {
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status = "okay";
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pinctrl-0 = <&remote_input_ao_pins>;
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pinctrl-names = "default";
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};
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&i2c1 {
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status = "okay";
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pinctrl-0 = <&i2c1_z_pins>;
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pinctrl-names = "default";
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speaker_amp1: audio-codec@1b {
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compatible = "ti,tas5707";
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reg = <0x1b>;
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reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
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#sound-dai-cells = <0>;
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AVDD-supply = <&vcc_3v3>;
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DVDD-supply = <&vcc_3v3>;
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PVDD_A-supply = <&main_12v>;
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PVDD_B-supply = <&main_12v>;
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PVDD_C-supply = <&main_12v>;
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PVDD_D-supply = <&main_12v>;
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sound-name-prefix = "SPK1";
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};
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};
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&i2c_AO {
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status = "okay";
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pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
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pinctrl-names = "default";
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gpio_speaker: gpio-controller@1f {
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compatible = "nxp,pca9557";
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reg = <0x1f>;
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gpio-controller;
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#gpio-cells = <2>;
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vcc-supply = <&vddao_3v3>;
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};
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};
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&pdm {
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pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
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<&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pwm_ab {
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status = "okay";
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pinctrl-0 = <&pwm_a_x20_pins>;
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pinctrl-names = "default";
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};
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&saradc {
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status = "okay";
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vref-supply = <&vddio_ao18>;
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};
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/* wifi module */
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&sd_emmc_b {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&sdio_pins>;
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pinctrl-1 = <&sdio_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <100000000>;
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non-removable;
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disable-wp;
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mmc-pwrseq = <&sdio_pwrseq>;
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vmmc-supply = <&vddao_3v3>;
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vqmmc-supply = <&vddio_boot>;
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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/* emmc storage */
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&sd_emmc_c {
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <180000000>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vddio_boot>;
|
||||
};
|
||||
|
||||
&spdifout {
|
||||
pinctrl-0 = <&spdif_out_a20_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmif_a {
|
||||
pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
|
||||
<&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmif_b {
|
||||
pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
|
||||
<&tdmb_din3_pins>, <&mclk_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmif_c {
|
||||
pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
|
||||
<&tdmc_din1_pins>, <&tdmc_dout2_pins>,
|
||||
<&mclk_c_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmin_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmin_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmin_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmin_lb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmout_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&toddr_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&toddr_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&toddr_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
1589
arch/arm/dts/meson-axg.dtsi
Normal file
1589
arch/arm/dts/meson-axg.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
26
include/dt-bindings/clock/axg-aoclkc.h
Normal file
26
include/dt-bindings/clock/axg-aoclkc.h
Normal file
@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2018 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
|
||||
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
|
||||
|
||||
#define CLKID_AO_REMOTE 0
|
||||
#define CLKID_AO_I2C_MASTER 1
|
||||
#define CLKID_AO_I2C_SLAVE 2
|
||||
#define CLKID_AO_UART1 3
|
||||
#define CLKID_AO_UART2 4
|
||||
#define CLKID_AO_IR_BLASTER 5
|
||||
#define CLKID_AO_SAR_ADC 6
|
||||
#define CLKID_AO_CLK81 7
|
||||
#define CLKID_AO_SAR_ADC_SEL 8
|
||||
#define CLKID_AO_SAR_ADC_DIV 9
|
||||
#define CLKID_AO_SAR_ADC_CLK 10
|
||||
#define CLKID_AO_ALT_XTAL 11
|
||||
|
||||
#endif
|
||||
94
include/dt-bindings/clock/axg-audio-clkc.h
Normal file
94
include/dt-bindings/clock/axg-audio-clkc.h
Normal file
@ -0,0 +1,94 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2018 Baylibre SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
#define __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
|
||||
#define AUD_CLKID_SLV_SCLK0 9
|
||||
#define AUD_CLKID_SLV_SCLK1 10
|
||||
#define AUD_CLKID_SLV_SCLK2 11
|
||||
#define AUD_CLKID_SLV_SCLK3 12
|
||||
#define AUD_CLKID_SLV_SCLK4 13
|
||||
#define AUD_CLKID_SLV_SCLK5 14
|
||||
#define AUD_CLKID_SLV_SCLK6 15
|
||||
#define AUD_CLKID_SLV_SCLK7 16
|
||||
#define AUD_CLKID_SLV_SCLK8 17
|
||||
#define AUD_CLKID_SLV_SCLK9 18
|
||||
#define AUD_CLKID_SLV_LRCLK0 19
|
||||
#define AUD_CLKID_SLV_LRCLK1 20
|
||||
#define AUD_CLKID_SLV_LRCLK2 21
|
||||
#define AUD_CLKID_SLV_LRCLK3 22
|
||||
#define AUD_CLKID_SLV_LRCLK4 23
|
||||
#define AUD_CLKID_SLV_LRCLK5 24
|
||||
#define AUD_CLKID_SLV_LRCLK6 25
|
||||
#define AUD_CLKID_SLV_LRCLK7 26
|
||||
#define AUD_CLKID_SLV_LRCLK8 27
|
||||
#define AUD_CLKID_SLV_LRCLK9 28
|
||||
#define AUD_CLKID_DDR_ARB 29
|
||||
#define AUD_CLKID_PDM 30
|
||||
#define AUD_CLKID_TDMIN_A 31
|
||||
#define AUD_CLKID_TDMIN_B 32
|
||||
#define AUD_CLKID_TDMIN_C 33
|
||||
#define AUD_CLKID_TDMIN_LB 34
|
||||
#define AUD_CLKID_TDMOUT_A 35
|
||||
#define AUD_CLKID_TDMOUT_B 36
|
||||
#define AUD_CLKID_TDMOUT_C 37
|
||||
#define AUD_CLKID_FRDDR_A 38
|
||||
#define AUD_CLKID_FRDDR_B 39
|
||||
#define AUD_CLKID_FRDDR_C 40
|
||||
#define AUD_CLKID_TODDR_A 41
|
||||
#define AUD_CLKID_TODDR_B 42
|
||||
#define AUD_CLKID_TODDR_C 43
|
||||
#define AUD_CLKID_LOOPBACK 44
|
||||
#define AUD_CLKID_SPDIFIN 45
|
||||
#define AUD_CLKID_SPDIFOUT 46
|
||||
#define AUD_CLKID_RESAMPLE 47
|
||||
#define AUD_CLKID_POWER_DETECT 48
|
||||
#define AUD_CLKID_MST_A_MCLK 49
|
||||
#define AUD_CLKID_MST_B_MCLK 50
|
||||
#define AUD_CLKID_MST_C_MCLK 51
|
||||
#define AUD_CLKID_MST_D_MCLK 52
|
||||
#define AUD_CLKID_MST_E_MCLK 53
|
||||
#define AUD_CLKID_MST_F_MCLK 54
|
||||
#define AUD_CLKID_SPDIFOUT_CLK 55
|
||||
#define AUD_CLKID_SPDIFIN_CLK 56
|
||||
#define AUD_CLKID_PDM_DCLK 57
|
||||
#define AUD_CLKID_PDM_SYSCLK 58
|
||||
#define AUD_CLKID_MST_A_SCLK 79
|
||||
#define AUD_CLKID_MST_B_SCLK 80
|
||||
#define AUD_CLKID_MST_C_SCLK 81
|
||||
#define AUD_CLKID_MST_D_SCLK 82
|
||||
#define AUD_CLKID_MST_E_SCLK 83
|
||||
#define AUD_CLKID_MST_F_SCLK 84
|
||||
#define AUD_CLKID_MST_A_LRCLK 86
|
||||
#define AUD_CLKID_MST_B_LRCLK 87
|
||||
#define AUD_CLKID_MST_C_LRCLK 88
|
||||
#define AUD_CLKID_MST_D_LRCLK 89
|
||||
#define AUD_CLKID_MST_E_LRCLK 90
|
||||
#define AUD_CLKID_MST_F_LRCLK 91
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
|
||||
#define AUD_CLKID_TDMIN_A_SCLK 123
|
||||
#define AUD_CLKID_TDMIN_B_SCLK 124
|
||||
#define AUD_CLKID_TDMIN_C_SCLK 125
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK 126
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK 127
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK 128
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK 129
|
||||
#define AUD_CLKID_TDMIN_A_LRCLK 130
|
||||
#define AUD_CLKID_TDMIN_B_LRCLK 131
|
||||
#define AUD_CLKID_TDMIN_C_LRCLK 132
|
||||
#define AUD_CLKID_TDMIN_LB_LRCLK 133
|
||||
#define AUD_CLKID_TDMOUT_A_LRCLK 134
|
||||
#define AUD_CLKID_TDMOUT_B_LRCLK 135
|
||||
#define AUD_CLKID_TDMOUT_C_LRCLK 136
|
||||
|
||||
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
||||
76
include/dt-bindings/clock/axg-clkc.h
Normal file
76
include/dt-bindings/clock/axg-clkc.h
Normal file
@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Meson-AXG clock tree IDs
|
||||
*
|
||||
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __AXG_CLKC_H
|
||||
#define __AXG_CLKC_H
|
||||
|
||||
#define CLKID_SYS_PLL 0
|
||||
#define CLKID_FIXED_PLL 1
|
||||
#define CLKID_FCLK_DIV2 2
|
||||
#define CLKID_FCLK_DIV3 3
|
||||
#define CLKID_FCLK_DIV4 4
|
||||
#define CLKID_FCLK_DIV5 5
|
||||
#define CLKID_FCLK_DIV7 6
|
||||
#define CLKID_GP0_PLL 7
|
||||
#define CLKID_CLK81 10
|
||||
#define CLKID_MPLL0 11
|
||||
#define CLKID_MPLL1 12
|
||||
#define CLKID_MPLL2 13
|
||||
#define CLKID_MPLL3 14
|
||||
#define CLKID_DDR 15
|
||||
#define CLKID_AUDIO_LOCKER 16
|
||||
#define CLKID_MIPI_DSI_HOST 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC0 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_RNG0 23
|
||||
#define CLKID_UART0 24
|
||||
#define CLKID_MIPI_DSI_PHY 25
|
||||
#define CLKID_SPICC1 26
|
||||
#define CLKID_PCIE_A 27
|
||||
#define CLKID_PCIE_B 28
|
||||
#define CLKID_HIU_IFACE 29
|
||||
#define CLKID_ASSIST_MISC 30
|
||||
#define CLKID_SD_EMMC_B 31
|
||||
#define CLKID_SD_EMMC_C 32
|
||||
#define CLKID_DMA 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_AUDIO 35
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_UART1 37
|
||||
#define CLKID_G2D 38
|
||||
#define CLKID_USB0 39
|
||||
#define CLKID_USB1 40
|
||||
#define CLKID_RESET 41
|
||||
#define CLKID_USB 42
|
||||
#define CLKID_AHB_ARB0 43
|
||||
#define CLKID_EFUSE 44
|
||||
#define CLKID_BOOT_ROM 45
|
||||
#define CLKID_AHB_DATA_BUS 46
|
||||
#define CLKID_AHB_CTRL_BUS 47
|
||||
#define CLKID_USB1_DDR_BRIDGE 48
|
||||
#define CLKID_USB0_DDR_BRIDGE 49
|
||||
#define CLKID_MMC_PCLK 50
|
||||
#define CLKID_VPU_INTR 51
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 52
|
||||
#define CLKID_GIC 53
|
||||
#define CLKID_AO_MEDIA_CPU 54
|
||||
#define CLKID_AO_AHB_SRAM 55
|
||||
#define CLKID_AO_AHB_BUS 56
|
||||
#define CLKID_AO_IFACE 57
|
||||
#define CLKID_AO_I2C 58
|
||||
#define CLKID_SD_EMMC_B_CLK0 59
|
||||
#define CLKID_SD_EMMC_C_CLK0 60
|
||||
#define CLKID_HIFI_PLL 69
|
||||
#define CLKID_PCIE_CML_EN0 79
|
||||
#define CLKID_PCIE_CML_EN1 80
|
||||
#define CLKID_MIPI_ENABLE 81
|
||||
#define CLKID_GEN_CLK 84
|
||||
|
||||
#endif /* __AXG_CLKC_H */
|
||||
116
include/dt-bindings/gpio/meson-axg-gpio.h
Normal file
116
include/dt-bindings/gpio/meson-axg-gpio.h
Normal file
@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
|
||||
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
|
||||
#define _DT_BINDINGS_MESON_AXG_GPIO_H
|
||||
|
||||
/* First GPIO chip */
|
||||
#define GPIOAO_0 0
|
||||
#define GPIOAO_1 1
|
||||
#define GPIOAO_2 2
|
||||
#define GPIOAO_3 3
|
||||
#define GPIOAO_4 4
|
||||
#define GPIOAO_5 5
|
||||
#define GPIOAO_6 6
|
||||
#define GPIOAO_7 7
|
||||
#define GPIOAO_8 8
|
||||
#define GPIOAO_9 9
|
||||
#define GPIOAO_10 10
|
||||
#define GPIOAO_11 11
|
||||
#define GPIOAO_12 12
|
||||
#define GPIOAO_13 13
|
||||
#define GPIO_TEST_N 14
|
||||
|
||||
/* Second GPIO chip */
|
||||
#define GPIOZ_0 0
|
||||
#define GPIOZ_1 1
|
||||
#define GPIOZ_2 2
|
||||
#define GPIOZ_3 3
|
||||
#define GPIOZ_4 4
|
||||
#define GPIOZ_5 5
|
||||
#define GPIOZ_6 6
|
||||
#define GPIOZ_7 7
|
||||
#define GPIOZ_8 8
|
||||
#define GPIOZ_9 9
|
||||
#define GPIOZ_10 10
|
||||
#define BOOT_0 11
|
||||
#define BOOT_1 12
|
||||
#define BOOT_2 13
|
||||
#define BOOT_3 14
|
||||
#define BOOT_4 15
|
||||
#define BOOT_5 16
|
||||
#define BOOT_6 17
|
||||
#define BOOT_7 18
|
||||
#define BOOT_8 19
|
||||
#define BOOT_9 20
|
||||
#define BOOT_10 21
|
||||
#define BOOT_11 22
|
||||
#define BOOT_12 23
|
||||
#define BOOT_13 24
|
||||
#define BOOT_14 25
|
||||
#define GPIOA_0 26
|
||||
#define GPIOA_1 27
|
||||
#define GPIOA_2 28
|
||||
#define GPIOA_3 29
|
||||
#define GPIOA_4 30
|
||||
#define GPIOA_5 31
|
||||
#define GPIOA_6 32
|
||||
#define GPIOA_7 33
|
||||
#define GPIOA_8 34
|
||||
#define GPIOA_9 35
|
||||
#define GPIOA_10 36
|
||||
#define GPIOA_11 37
|
||||
#define GPIOA_12 38
|
||||
#define GPIOA_13 39
|
||||
#define GPIOA_14 40
|
||||
#define GPIOA_15 41
|
||||
#define GPIOA_16 42
|
||||
#define GPIOA_17 43
|
||||
#define GPIOA_18 44
|
||||
#define GPIOA_19 45
|
||||
#define GPIOA_20 46
|
||||
#define GPIOX_0 47
|
||||
#define GPIOX_1 48
|
||||
#define GPIOX_2 49
|
||||
#define GPIOX_3 50
|
||||
#define GPIOX_4 51
|
||||
#define GPIOX_5 52
|
||||
#define GPIOX_6 53
|
||||
#define GPIOX_7 54
|
||||
#define GPIOX_8 55
|
||||
#define GPIOX_9 56
|
||||
#define GPIOX_10 57
|
||||
#define GPIOX_11 58
|
||||
#define GPIOX_12 59
|
||||
#define GPIOX_13 60
|
||||
#define GPIOX_14 61
|
||||
#define GPIOX_15 62
|
||||
#define GPIOX_16 63
|
||||
#define GPIOX_17 64
|
||||
#define GPIOX_18 65
|
||||
#define GPIOX_19 66
|
||||
#define GPIOX_20 67
|
||||
#define GPIOX_21 68
|
||||
#define GPIOX_22 69
|
||||
#define GPIOY_0 70
|
||||
#define GPIOY_1 71
|
||||
#define GPIOY_2 72
|
||||
#define GPIOY_3 73
|
||||
#define GPIOY_4 74
|
||||
#define GPIOY_5 75
|
||||
#define GPIOY_6 76
|
||||
#define GPIOY_7 77
|
||||
#define GPIOY_8 78
|
||||
#define GPIOY_9 79
|
||||
#define GPIOY_10 80
|
||||
#define GPIOY_11 81
|
||||
#define GPIOY_12 82
|
||||
#define GPIOY_13 83
|
||||
#define GPIOY_14 84
|
||||
#define GPIOY_15 85
|
||||
|
||||
#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
|
||||
17
include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
Normal file
17
include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
Normal file
@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
*
|
||||
* Copyright (c) 2018 Baylibre SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
|
||||
|
||||
#define AXG_ARB_TODDR_A 0
|
||||
#define AXG_ARB_TODDR_B 1
|
||||
#define AXG_ARB_TODDR_C 2
|
||||
#define AXG_ARB_FRDDR_A 3
|
||||
#define AXG_ARB_FRDDR_B 4
|
||||
#define AXG_ARB_FRDDR_C 5
|
||||
|
||||
#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
|
||||
124
include/dt-bindings/reset/amlogic,meson-axg-reset.h
Normal file
124
include/dt-bindings/reset/amlogic,meson-axg-reset.h
Normal file
@ -0,0 +1,124 @@
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2017 Amlogic, inc.
|
||||
* Author: Yixun Lan <yixun.lan@amlogic.com>
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR BSD)
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
#define RESET_HIU 0
|
||||
#define RESET_PCIE_A 1
|
||||
#define RESET_PCIE_B 2
|
||||
#define RESET_DDR_TOP 3
|
||||
/* 4 */
|
||||
#define RESET_VIU 5
|
||||
#define RESET_PCIE_PHY 6
|
||||
#define RESET_PCIE_APB 7
|
||||
/* 8 */
|
||||
/* 9 */
|
||||
#define RESET_VENC 10
|
||||
#define RESET_ASSIST 11
|
||||
/* 12 */
|
||||
#define RESET_VCBUS 13
|
||||
/* 14 */
|
||||
/* 15 */
|
||||
#define RESET_GIC 16
|
||||
#define RESET_CAPB3_DECODE 17
|
||||
/* 18-21 */
|
||||
#define RESET_SYS_CPU_CAPB3 22
|
||||
#define RESET_CBUS_CAPB3 23
|
||||
#define RESET_AHB_CNTL 24
|
||||
#define RESET_AHB_DATA 25
|
||||
#define RESET_VCBUS_CLK81 26
|
||||
#define RESET_MMC 27
|
||||
/* 28-31 */
|
||||
/* RESET1 */
|
||||
/* 32 */
|
||||
/* 33 */
|
||||
#define RESET_USB_OTG 34
|
||||
#define RESET_DDR 35
|
||||
#define RESET_AO_RESET 36
|
||||
/* 37 */
|
||||
#define RESET_AHB_SRAM 38
|
||||
/* 39 */
|
||||
/* 40 */
|
||||
#define RESET_DMA 41
|
||||
#define RESET_ISA 42
|
||||
#define RESET_ETHERNET 43
|
||||
/* 44 */
|
||||
#define RESET_SD_EMMC_B 45
|
||||
#define RESET_SD_EMMC_C 46
|
||||
#define RESET_ROM_BOOT 47
|
||||
#define RESET_SYS_CPU_0 48
|
||||
#define RESET_SYS_CPU_1 49
|
||||
#define RESET_SYS_CPU_2 50
|
||||
#define RESET_SYS_CPU_3 51
|
||||
#define RESET_SYS_CPU_CORE_0 52
|
||||
#define RESET_SYS_CPU_CORE_1 53
|
||||
#define RESET_SYS_CPU_CORE_2 54
|
||||
#define RESET_SYS_CPU_CORE_3 55
|
||||
#define RESET_SYS_PLL_DIV 56
|
||||
#define RESET_SYS_CPU_AXI 57
|
||||
#define RESET_SYS_CPU_L2 58
|
||||
#define RESET_SYS_CPU_P 59
|
||||
#define RESET_SYS_CPU_MBIST 60
|
||||
/* 61-63 */
|
||||
/* RESET2 */
|
||||
/* 64 */
|
||||
/* 65 */
|
||||
#define RESET_AUDIO 66
|
||||
/* 67 */
|
||||
#define RESET_MIPI_HOST 68
|
||||
#define RESET_AUDIO_LOCKER 69
|
||||
#define RESET_GE2D 70
|
||||
/* 71-76 */
|
||||
#define RESET_AO_CPU_RESET 77
|
||||
/* 78-95 */
|
||||
/* RESET3 */
|
||||
#define RESET_RING_OSCILLATOR 96
|
||||
/* 97-127 */
|
||||
/* RESET4 */
|
||||
/* 128 */
|
||||
/* 129 */
|
||||
#define RESET_MIPI_PHY 130
|
||||
/* 131-140 */
|
||||
#define RESET_VENCL 141
|
||||
#define RESET_I2C_MASTER_2 142
|
||||
#define RESET_I2C_MASTER_1 143
|
||||
/* 144-159 */
|
||||
/* RESET5 */
|
||||
/* 160-191 */
|
||||
/* RESET6 */
|
||||
#define RESET_PERIPHS_GENERAL 192
|
||||
#define RESET_PERIPHS_SPICC 193
|
||||
/* 194 */
|
||||
/* 195 */
|
||||
#define RESET_PERIPHS_I2C_MASTER_0 196
|
||||
/* 197-200 */
|
||||
#define RESET_PERIPHS_UART_0 201
|
||||
#define RESET_PERIPHS_UART_1 202
|
||||
/* 203-204 */
|
||||
#define RESET_PERIPHS_SPI_0 205
|
||||
#define RESET_PERIPHS_I2C_MASTER_3 206
|
||||
/* 207-223 */
|
||||
/* RESET7 */
|
||||
#define RESET_USB_DDR_0 224
|
||||
#define RESET_USB_DDR_1 225
|
||||
#define RESET_USB_DDR_2 226
|
||||
#define RESET_USB_DDR_3 227
|
||||
/* 228 */
|
||||
#define RESET_DEVICE_MMC_ARB 229
|
||||
/* 230 */
|
||||
#define RESET_VID_LOCK 231
|
||||
#define RESET_A9_DMC_PIPEL 232
|
||||
#define RESET_DMC_VPU_PIPEL 233
|
||||
/* 234-255 */
|
||||
|
||||
#endif
|
||||
20
include/dt-bindings/reset/axg-aoclkc.h
Normal file
20
include/dt-bindings/reset/axg-aoclkc.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2018 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
|
||||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
|
||||
|
||||
#define RESET_AO_REMOTE 0
|
||||
#define RESET_AO_I2C_MASTER 1
|
||||
#define RESET_AO_I2C_SLAVE 2
|
||||
#define RESET_AO_UART1 3
|
||||
#define RESET_AO_UART2 4
|
||||
#define RESET_AO_IR_BLASTER 5
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user