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board: novena: convert to DM_I2C
Conversion to DM_I2C is mandatory, enable DM_I2C to disable board removal warning. Convert EEPROM and IT6251 access to use DM_I2C API. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Anatolij Gustschin
Heiko Schocher
parent
b913ba95c7
commit
763e406c4e
@ -137,23 +137,23 @@ struct novena_eeprom_data {
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int misc_init_r(void)
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{
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struct novena_eeprom_data data;
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uchar *datap = (uchar *)&data;
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uint8_t *datap = (uint8_t *)&data;
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const char *signature = "Novena";
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struct udevice *eeprom;
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int ret;
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/* If 'ethaddr' is already set, do nothing. */
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if (env_get("ethaddr"))
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return 0;
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/* EEPROM is at bus 2. */
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ret = i2c_set_bus_num(2);
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/* EEPROM is at bus 2, address 0x56 */
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ret = i2c_get_chip_for_busnum(2, 0x56, 1, &eeprom);
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if (ret) {
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puts("Cannot select EEPROM I2C bus.\n");
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return 0;
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}
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/* EEPROM is at address 0x56. */
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ret = eeprom_read(0x56, 0, datap, sizeof(data));
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ret = dm_i2c_read(eeprom, 0, datap, sizeof(data));
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if (ret) {
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puts("Cannot read I2C EEPROM.\n");
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return 0;
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@ -58,28 +58,29 @@
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#define IT6521_RETRY_MAX 20
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static struct udevice *it6251_chip;
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static struct udevice *it6251_lvds;
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static int it6251_is_stable(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
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int status;
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int clkcnt;
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int rpclkcnt;
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int refstate;
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rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
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((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
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rpclkcnt = (dm_i2c_reg_read(it6251_chip, 0x13) & 0xff) |
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((dm_i2c_reg_read(it6251_chip, 0x14) << 8) & 0x0f00);
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debug("RPCLKCnt: %d\n", rpclkcnt);
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status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
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status = dm_i2c_reg_read(it6251_chip, IT6251_SYSTEM_STATUS);
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debug("System status: 0x%02x\n", status);
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clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
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((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
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clkcnt = (dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
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((dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_HIGH) << 8) &
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0x0f00);
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debug("Clock: 0x%02x\n", clkcnt);
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refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
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refstate = dm_i2c_reg_read(it6251_lvds, IT6251_REF_STATE);
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debug("Ref Link State: 0x%02x\n", refstate);
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if ((refstate & 0x1f) != 0)
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@ -97,16 +98,14 @@ static int it6251_is_stable(void)
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static int it6251_ready(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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/* Test if the IT6251 came out of reset by reading ID regs. */
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if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
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if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_LOW) != 0x15)
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return 0;
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if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
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if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_HIGH) != 0xca)
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return 0;
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if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
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if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_LOW) != 0x51)
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return 0;
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if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
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if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_HIGH) != 0x62)
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return 0;
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return 1;
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@ -114,116 +113,112 @@ static int it6251_ready(void)
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static void it6251_program_regs(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
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i2c_reg_write(caddr, 0x05, 0x00);
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dm_i2c_reg_write(it6251_chip, 0x05, 0x00);
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mdelay(1);
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/* set LVDSRX address, and enable */
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i2c_reg_write(caddr, 0xfd, 0xbc);
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i2c_reg_write(caddr, 0xfe, 0x01);
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dm_i2c_reg_write(it6251_chip, 0xfd, 0xbc);
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dm_i2c_reg_write(it6251_chip, 0xfe, 0x01);
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/*
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* LVDSRX
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*/
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/* This write always fails, because the chip goes into reset */
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/* reset LVDSRX */
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i2c_reg_write(laddr, 0x05, 0xff);
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i2c_reg_write(laddr, 0x05, 0x00);
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dm_i2c_reg_write(it6251_lvds, 0x05, 0xff);
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dm_i2c_reg_write(it6251_lvds, 0x05, 0x00);
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/* reset LVDSRX PLL */
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i2c_reg_write(laddr, 0x3b, 0x42);
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i2c_reg_write(laddr, 0x3b, 0x43);
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dm_i2c_reg_write(it6251_lvds, 0x3b, 0x42);
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dm_i2c_reg_write(it6251_lvds, 0x3b, 0x43);
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/* something with SSC PLL */
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i2c_reg_write(laddr, 0x3c, 0x08);
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dm_i2c_reg_write(it6251_lvds, 0x3c, 0x08);
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/* don't swap links, but writing reserved registers */
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i2c_reg_write(laddr, 0x0b, 0x88);
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dm_i2c_reg_write(it6251_lvds, 0x0b, 0x88);
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/* JEIDA, 8-bit depth 0x11, orig 0x42 */
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i2c_reg_write(laddr, 0x2c, 0x01);
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dm_i2c_reg_write(it6251_lvds, 0x2c, 0x01);
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/* "reserved" */
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i2c_reg_write(laddr, 0x32, 0x04);
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dm_i2c_reg_write(it6251_lvds, 0x32, 0x04);
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/* "reserved" */
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i2c_reg_write(laddr, 0x35, 0xe0);
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dm_i2c_reg_write(it6251_lvds, 0x35, 0xe0);
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/* "reserved" + clock delay */
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i2c_reg_write(laddr, 0x2b, 0x24);
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dm_i2c_reg_write(it6251_lvds, 0x2b, 0x24);
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/* reset LVDSRX pix clock */
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i2c_reg_write(laddr, 0x05, 0x02);
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i2c_reg_write(laddr, 0x05, 0x00);
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dm_i2c_reg_write(it6251_lvds, 0x05, 0x02);
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dm_i2c_reg_write(it6251_lvds, 0x05, 0x00);
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/*
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* DPTX
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*/
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/* set for two lane mode, normal op, no swapping, no downspread */
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i2c_reg_write(caddr, 0x16, 0x02);
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dm_i2c_reg_write(it6251_chip, 0x16, 0x02);
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/* some AUX channel EDID magic */
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i2c_reg_write(caddr, 0x23, 0x40);
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dm_i2c_reg_write(it6251_chip, 0x23, 0x40);
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/* power down lanes 3-0 */
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i2c_reg_write(caddr, 0x5c, 0xf3);
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dm_i2c_reg_write(it6251_chip, 0x5c, 0xf3);
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/* enable DP scrambling, change EQ CR phase */
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i2c_reg_write(caddr, 0x5f, 0x06);
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dm_i2c_reg_write(it6251_chip, 0x5f, 0x06);
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/* color mode RGB, pclk/2 */
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i2c_reg_write(caddr, 0x60, 0x02);
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dm_i2c_reg_write(it6251_chip, 0x60, 0x02);
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/* dual pixel input mode, no EO swap, no RGB swap */
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i2c_reg_write(caddr, 0x61, 0x04);
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dm_i2c_reg_write(it6251_chip, 0x61, 0x04);
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/* M444B24 video format */
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i2c_reg_write(caddr, 0x62, 0x01);
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dm_i2c_reg_write(it6251_chip, 0x62, 0x01);
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/* vesa range / not interlace / vsync high / hsync high */
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i2c_reg_write(caddr, 0xa0, 0x0F);
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dm_i2c_reg_write(it6251_chip, 0xa0, 0x0F);
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/* hpd event timer set to 1.6-ish ms */
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i2c_reg_write(caddr, 0xc9, 0xf5);
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dm_i2c_reg_write(it6251_chip, 0xc9, 0xf5);
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/* more reserved magic */
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i2c_reg_write(caddr, 0xca, 0x4d);
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i2c_reg_write(caddr, 0xcb, 0x37);
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dm_i2c_reg_write(it6251_chip, 0xca, 0x4d);
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dm_i2c_reg_write(it6251_chip, 0xcb, 0x37);
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/* enhanced framing mode, auto video fifo reset, video mute disable */
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i2c_reg_write(caddr, 0xd3, 0x03);
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dm_i2c_reg_write(it6251_chip, 0xd3, 0x03);
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/* "vidstmp" and some reserved stuff */
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i2c_reg_write(caddr, 0xd4, 0x45);
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dm_i2c_reg_write(it6251_chip, 0xd4, 0x45);
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/* queue number -- reserved */
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i2c_reg_write(caddr, 0xe7, 0xa0);
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dm_i2c_reg_write(it6251_chip, 0xe7, 0xa0);
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/* info frame packets and reserved */
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i2c_reg_write(caddr, 0xe8, 0x33);
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dm_i2c_reg_write(it6251_chip, 0xe8, 0x33);
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/* more AVI stuff */
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i2c_reg_write(caddr, 0xec, 0x00);
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dm_i2c_reg_write(it6251_chip, 0xec, 0x00);
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/* select PC master reg for aux channel? */
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i2c_reg_write(caddr, 0x23, 0x42);
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dm_i2c_reg_write(it6251_chip, 0x23, 0x42);
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/* send PC request commands */
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i2c_reg_write(caddr, 0x24, 0x00);
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i2c_reg_write(caddr, 0x25, 0x00);
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i2c_reg_write(caddr, 0x26, 0x00);
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dm_i2c_reg_write(it6251_chip, 0x24, 0x00);
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dm_i2c_reg_write(it6251_chip, 0x25, 0x00);
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dm_i2c_reg_write(it6251_chip, 0x26, 0x00);
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/* native aux read */
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i2c_reg_write(caddr, 0x2b, 0x00);
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dm_i2c_reg_write(it6251_chip, 0x2b, 0x00);
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/* back to internal */
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i2c_reg_write(caddr, 0x23, 0x40);
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dm_i2c_reg_write(it6251_chip, 0x23, 0x40);
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/* voltage swing level 3 */
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i2c_reg_write(caddr, 0x19, 0xff);
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dm_i2c_reg_write(it6251_chip, 0x19, 0xff);
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/* pre-emphasis level 3 */
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i2c_reg_write(caddr, 0x1a, 0xff);
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dm_i2c_reg_write(it6251_chip, 0x1a, 0xff);
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/* start link training */
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i2c_reg_write(caddr, 0x17, 0x01);
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dm_i2c_reg_write(it6251_chip, 0x17, 0x01);
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}
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static int it6251_init(void)
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{
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const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
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int reg;
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int tries, retries = 0;
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@ -233,7 +228,7 @@ static int it6251_init(void)
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/* Wait for video stable. */
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for (tries = 0; tries < 100; tries++) {
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reg = i2c_reg_read(caddr, 0x17);
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reg = dm_i2c_reg_read(it6251_chip, 0x17);
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/* Test Link CFG, STS, LCS read done. */
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if ((reg & 0xe0) != 0xe0) {
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/* Not yet, wait a bit more. */
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@ -285,10 +280,14 @@ static int detect_lvds(struct display_info_t const *dev)
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enable_lvds(dev);
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ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
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if (ret) {
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puts("Cannot select IT6251 I2C bus.\n");
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return 0;
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if (!it6251_chip) {
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ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
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NOVENA_IT6251_CHIPADDR,
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1, &it6251_chip);
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if (ret) {
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puts("Cannot select IT6251 I2C bus.\n");
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return 0;
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}
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}
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/* Wait up-to ~250 mS for the LVDS to come up. */
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@ -435,9 +434,20 @@ void setup_display_lvds(void)
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{
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int ret;
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ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
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if (!it6251_chip) {
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ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
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NOVENA_IT6251_CHIPADDR,
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1, &it6251_chip);
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if (ret) {
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puts("Cannot select LVDS-to-eDP I2C bus.\n");
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return;
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}
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}
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ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
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NOVENA_IT6251_LVDSADDR, 1, &it6251_lvds);
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if (ret) {
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puts("Cannot select LVDS-to-eDP I2C bus.\n");
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puts("Cannot find IT6251 LVDS bus.\n");
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return;
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}
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@ -67,7 +67,7 @@ CONFIG_NETCONSOLE=y
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_DWC_AHSATA=y
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CONFIG_LBA48=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_DM_I2C=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_MXC=y
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CONFIG_FSL_USDHC=y
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