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net: mediatek: add support for NETSYS v3
This patch adds support for NETSYS v3 hardware. Comparing to NETSYS v2, NETSYS v3 has three GMACs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
parent
ba026ebe46
commit
7628194d7a
@ -76,6 +76,7 @@ enum mtk_switch {
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* @caps Flags shown the extra capability for the SoC
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* @ana_rgc3: The offset for register ANA_RGC3 related to
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* sgmiisys syscon
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* @gdma_count: Number of GDMAs
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* @pdma_base: Register base of PDMA block
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* @txd_size: Tx DMA descriptor size.
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* @rxd_size: Rx DMA descriptor size.
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@ -83,6 +84,7 @@ enum mtk_switch {
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struct mtk_soc_data {
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u32 caps;
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u32 ana_rgc3;
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u32 gdma_count;
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u32 pdma_base;
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u32 txd_size;
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u32 rxd_size;
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@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
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{
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u32 gdma_base;
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if (no == 1)
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if (no == 2)
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gdma_base = GDMA3_BASE;
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else if (no == 1)
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gdma_base = GDMA2_BASE;
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else
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gdma_base = GDMA1_BASE;
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@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
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txd->txd1 = virt_to_phys(pkt_base);
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txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
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txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
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15 : priv->gmac_id + 1);
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else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
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else
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txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
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@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
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rxd->rxd1 = virt_to_phys(pkt_base);
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
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MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
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rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
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else
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rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
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@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
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static int mtk_eth_start(struct udevice *dev)
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{
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struct mtk_eth_priv *priv = dev_get_priv(dev);
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int ret;
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int i, ret;
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/* Reset FE */
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reset_assert(&priv->rst_fe);
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@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice *dev)
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reset_deassert(&priv->rst_fe);
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mdelay(10);
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
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MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
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setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
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/* Packets forward to PDMA */
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mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
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if (priv->gmac_id == 0)
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mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
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else
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mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
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for (i = 0; i < priv->soc->gdma_count; i++) {
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if (i == priv->gmac_id)
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continue;
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mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
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}
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
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mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
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GDMA_CPU_BRIDGE_EN);
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}
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udelay(500);
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@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice *dev, void *packet, int length)
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flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
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roundup(length, ARCH_DMA_MINALIGN));
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
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MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
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txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
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else
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txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
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@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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return -EAGAIN;
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}
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
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MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
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length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
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else
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length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
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@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
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rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
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MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
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rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
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else
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rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
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@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
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static const struct mtk_soc_data mt7986_data = {
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.caps = MT7986_CAPS,
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.ana_rgc3 = 0x128,
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.gdma_count = 2,
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.pdma_base = PDMA_V2_BASE,
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_data = {
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static const struct mtk_soc_data mt7981_data = {
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.caps = MT7981_CAPS,
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.ana_rgc3 = 0x128,
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.gdma_count = 2,
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.pdma_base = PDMA_V2_BASE,
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_data = {
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static const struct mtk_soc_data mt7629_data = {
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.ana_rgc3 = 0x128,
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.gdma_count = 2,
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.pdma_base = PDMA_V1_BASE,
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_data = {
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static const struct mtk_soc_data mt7623_data = {
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.caps = MT7623_CAPS,
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.gdma_count = 2,
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.pdma_base = PDMA_V1_BASE,
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_data = {
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static const struct mtk_soc_data mt7622_data = {
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.ana_rgc3 = 0x2028,
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.gdma_count = 2,
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.pdma_base = PDMA_V1_BASE,
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_data = {
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static const struct mtk_soc_data mt7621_data = {
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.caps = MT7621_CAPS,
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.gdma_count = 2,
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.pdma_base = PDMA_V1_BASE,
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@ -18,6 +18,7 @@ enum mkt_eth_capabilities {
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MTK_U3_COPHY_V2_BIT,
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MTK_INFRA_BIT,
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MTK_NETSYS_V2_BIT,
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MTK_NETSYS_V3_BIT,
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/* PATH BITS */
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MTK_ETH_PATH_GMAC1_TRGMII_BIT,
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@ -29,6 +30,7 @@ enum mkt_eth_capabilities {
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#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
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#define MTK_INFRA BIT(MTK_INFRA_BIT)
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#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
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#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT)
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/* Supported path present on SoCs */
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#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
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@ -52,8 +54,10 @@ enum mkt_eth_capabilities {
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/* Frame Engine Register Bases */
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#define PDMA_V1_BASE 0x0800
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#define PDMA_V2_BASE 0x6000
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#define PDMA_V3_BASE 0x6800
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#define GDMA1_BASE 0x0500
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#define GDMA2_BASE 0x1500
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#define GDMA3_BASE 0x0540
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#define GMAC_BASE 0x10000
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/* Ethernet subsystem registers */
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@ -153,6 +157,9 @@ enum mkt_eth_capabilities {
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#define UN_DP_S 0
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#define UN_DP_M 0x0f
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#define GDMA_EG_CTRL_REG 0x004
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#define GDMA_CPU_BRIDGE_EN BIT(31)
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#define GDMA_MAC_LSB_REG 0x008
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#define GDMA_MAC_MSB_REG 0x00c
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