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imx: ventana: Add support for GW551x
The GW551x is a small form factor board based on the IMX6 SoC that includes: * up to 512MB DDR3 memory * up to 2GB NAND flash * 1x miniPCIe socket (with USB) * HDMI out (micro-HDMI) * HDMI in (micro-HDMI) * TTL level I/O (supported by GW16111 breakout board): * I2C * 2x UART * CAN * 2x DIO (GPIO/PWM) * USB OTG Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey
Stefano Babic
parent
0c81b14fac
commit
75f21e3131
@ -81,8 +81,14 @@ read_eeprom(int bus, struct ventana_board_info *info)
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type = GW54xx;
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break;
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case '5':
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type = GW552x;
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break;
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if (info->model[4] == '1') {
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type = GW551x;
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break;
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} else if (info->model[4] == '2') {
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type = GW552x;
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break;
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}
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/* fall through */
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default:
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printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
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type = GW_UNKNOWN;
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@ -400,7 +400,7 @@ int board_eth_init(bd_t *bis)
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setup_iomux_enet();
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#ifdef CONFIG_FEC_MXC
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if (board_type != GW552x)
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if (board_type != GW551x && board_type != GW552x)
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cpu_eth_init(bis);
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#endif
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@ -679,6 +679,15 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
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IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
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/* PANLED# */
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
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/* PCI_RST# */
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IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
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/* PANLEDG# */
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
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@ -720,6 +729,7 @@ struct ventana {
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int num_pads;
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/* DIO pinmux/val */
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struct dio_cfg dio_cfg[4];
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int num_gpios;
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/* various gpios (0 if non-existent) */
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int leds[3];
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int pcie_rst;
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@ -765,6 +775,7 @@ static struct ventana gpio_cfg[] = {
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4
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},
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},
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.num_gpios = 4,
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 10),
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@ -808,6 +819,7 @@ static struct ventana gpio_cfg[] = {
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4
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},
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},
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.num_gpios = 4,
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 10),
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@ -850,6 +862,7 @@ static struct ventana gpio_cfg[] = {
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0
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},
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},
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.num_gpios = 4,
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 7),
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@ -894,6 +907,7 @@ static struct ventana gpio_cfg[] = {
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0
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},
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},
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.num_gpios = 4,
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 7),
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@ -937,6 +951,7 @@ static struct ventana gpio_cfg[] = {
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4
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},
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},
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.num_gpios = 4,
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 7),
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@ -952,10 +967,10 @@ static struct ventana gpio_cfg[] = {
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.wdis = IMX_GPIO_NR(5, 17),
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},
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/* GW552x */
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/* GW551x */
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{
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.gpio_pads = gw552x_gpio_pads,
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.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
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.gpio_pads = gw551x_gpio_pads,
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.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
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.dio_cfg = {
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{
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{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
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@ -976,12 +991,39 @@ static struct ventana gpio_cfg[] = {
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3
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},
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{
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{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
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IMX_GPIO_NR(2, 10),
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{ 0, 0 },
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0
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{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
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IMX_GPIO_NR(1, 18),
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{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
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4
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},
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},
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.num_gpios = 2,
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.leds = {
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IMX_GPIO_NR(4, 7),
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},
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.pcie_rst = IMX_GPIO_NR(1, 0),
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.wdis = IMX_GPIO_NR(7, 12),
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},
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/* GW552x */
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{
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.gpio_pads = gw552x_gpio_pads,
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.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
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.dio_cfg = {
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{
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{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
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IMX_GPIO_NR(1, 19),
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{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
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2
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},
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{
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{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
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IMX_GPIO_NR(1, 17),
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{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
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3
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},
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},
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.num_gpios = 4,
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.leds = {
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IMX_GPIO_NR(4, 6),
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IMX_GPIO_NR(4, 7),
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@ -1138,6 +1180,8 @@ static void setup_board_gpio(int board)
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iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
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unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
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if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
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continue;
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sprintf(arg, "dio%d", i);
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if (!hwconfig(arg))
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continue;
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@ -1430,7 +1474,7 @@ int misc_init_r(void)
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sprintf(fdt, "%s-%s.dtb", cputype, str);
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setenv("fdt_file1", fdt);
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}
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if (board_type != GW552x)
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if (board_type != GW551x && board_type != GW552x)
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str[4] = 'x';
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str[5] = 'x';
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str[6] = 0;
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@ -220,6 +220,50 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
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* calibration - these are the various CPU/DDR3 combinations we support
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*/
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static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43380347,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C313539,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36393C39,
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};
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static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43380347,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C313539,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36393C39,
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};
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static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43380347,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C313539,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36393C39,
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};
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static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43380347,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C313539,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36393C39,
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};
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static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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@ -363,7 +407,21 @@ static void spl_dram_init(int width, int size_mb, int board_model)
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* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
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* mx6_ddr_cfg - chip specific timing/layout details
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*/
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if (width == 32 && size_mb == 512) {
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if (width == 16 && size_mb == 256) {
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mem = &mt41k128m16jt_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_128x16_mmdc_calib;
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else
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calib = &mx6sdl_128x16_mmdc_calib;
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debug("2gB density\n");
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} else if (width == 16 && size_mb == 512) {
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mem = &mt41k256m16ha_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_256x16_mmdc_calib;
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else
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calib = &mx6sdl_256x16_mmdc_calib;
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debug("4gB density\n");
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} else if (width == 32 && size_mb == 512) {
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mem = &mt41k128m16jt_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_128x32_mmdc_calib;
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@ -109,6 +109,7 @@ enum {
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GW52xx,
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GW53xx,
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GW54xx,
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GW551x,
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GW552x,
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GW_UNKNOWN,
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GW_BADCRC,
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