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ARC: Cache: Get rid of [slc,pae,icache,dcache]_exists global variables
There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these variables get overwritten when we copy .data section from ROM. Instead we'll use icache_exists(), dcache_exists(), slc_exists(), pae_exists() functions which directly check BCRs every time. In U-Boot case ops are used only during self-relocation and DMA so we shouldn't be hit by noticeable performance degradation. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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@ -94,7 +94,6 @@
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#define DC_CTRL_CACHE_DISABLE BIT(0)
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#define DC_CTRL_INV_MODE_FLUSH BIT(6)
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#define DC_CTRL_FLUSH_STATUS BIT(8)
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#define CACHE_VER_NUM_MASK 0xF
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#define OP_INV BIT(0)
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#define OP_FLUSH BIT(1)
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@ -112,20 +111,16 @@
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* relocation but will be used after being zeroed.
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*/
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int l1_line_sz __section(".data");
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bool dcache_exists __section(".data") = false;
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bool icache_exists __section(".data") = false;
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#define CACHE_LINE_MASK (~(l1_line_sz - 1))
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int slc_line_sz __section(".data");
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bool slc_exists __section(".data") = false;
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bool ioc_exists __section(".data") = false;
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bool pae_exists __section(".data") = false;
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/* To force enable IOC set ioc_enable to 'true' */
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bool ioc_enable __section(".data") = false;
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void read_decode_mmu_bcr(void)
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static inline bool pae_exists(void)
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{
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/* TODO: should we compare mmu version from BCR and from CONFIG? */
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#if (CONFIG_ARC_MMU_VER >= 4)
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@ -133,15 +128,46 @@ void read_decode_mmu_bcr(void)
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mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
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pae_exists = !!mmu4.fields.pae;
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if (mmu4.fields.pae)
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return true;
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#endif /* (CONFIG_ARC_MMU_VER >= 4) */
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return false;
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}
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static inline bool icache_exists(void)
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{
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union bcr_di_cache ibcr;
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ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
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return !!ibcr.fields.ver;
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}
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static inline bool dcache_exists(void)
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{
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union bcr_di_cache dbcr;
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dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
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return !!dbcr.fields.ver;
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}
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static inline bool slc_exists(void)
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{
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if (is_isa_arcv2()) {
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union bcr_generic sbcr;
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sbcr.word = read_aux_reg(ARC_BCR_SLC);
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return !!sbcr.fields.ver;
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}
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return false;
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}
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static void __slc_entire_op(const int op)
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{
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unsigned int ctrl;
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if (!slc_exists)
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if (!slc_exists())
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return;
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ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
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@ -182,7 +208,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
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unsigned int ctrl;
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unsigned long end;
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if (!slc_exists)
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if (!slc_exists())
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return;
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/*
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@ -263,12 +289,9 @@ static void read_decode_cache_bcr_arcv2(void)
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union bcr_slc_cfg slc_cfg;
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union bcr_clust_cfg cbcr;
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union bcr_generic sbcr;
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sbcr.word = read_aux_reg(ARC_BCR_SLC);
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if (sbcr.fields.ver) {
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if (slc_exists()) {
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slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
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slc_exists = true;
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slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
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}
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@ -286,7 +309,6 @@ void read_decode_cache_bcr(void)
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ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
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if (ibcr.fields.ver) {
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icache_exists = true;
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l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
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if (!ic_line_sz)
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panic("Instruction exists but line length is 0\n");
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@ -294,7 +316,6 @@ void read_decode_cache_bcr(void)
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dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
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if (dbcr.fields.ver) {
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dcache_exists = true;
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l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
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if (!dc_line_sz)
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panic("Data cache exists but line length is 0\n");
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@ -314,20 +335,18 @@ void cache_init(void)
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if (is_isa_arcv2() && ioc_exists)
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arc_ioc_setup();
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read_decode_mmu_bcr();
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/*
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* ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
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* only if PAE exists in current HW. So we had to check pae_exist
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* before using them.
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*/
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if (is_isa_arcv2() && slc_exists && pae_exists)
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if (is_isa_arcv2() && slc_exists() && pae_exists())
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slc_upper_region_init();
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}
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int icache_status(void)
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{
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if (!icache_exists)
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if (!icache_exists())
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return 0;
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if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
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@ -338,14 +357,14 @@ int icache_status(void)
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void icache_enable(void)
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{
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if (icache_exists)
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if (icache_exists())
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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if (icache_exists)
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if (icache_exists())
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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@ -378,7 +397,7 @@ void invalidate_icache_all(void)
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int dcache_status(void)
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{
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if (!dcache_exists)
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if (!dcache_exists())
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return 0;
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if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
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@ -389,7 +408,7 @@ int dcache_status(void)
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void dcache_enable(void)
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{
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if (!dcache_exists)
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if (!dcache_exists())
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
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@ -398,7 +417,7 @@ void dcache_enable(void)
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void dcache_disable(void)
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{
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if (!dcache_exists)
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if (!dcache_exists())
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
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