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mips: octeon: Add cvmx-helper-pki.c
Import cvmx-helper-pki.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
Stefan Roese
parent
046922ea78
commit
755a6ea953
549
arch/mips/mach-octeon/cvmx-helper-pki.c
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549
arch/mips/mach-octeon/cvmx-helper-pki.c
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@ -0,0 +1,549 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* PKI helper functions.
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*/
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#include <time.h>
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#include <log.h>
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#include <linux/delay.h>
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#include <mach/cvmx-regs.h>
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#include <mach/cvmx-csr.h>
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#include <mach/cvmx-bootmem.h>
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#include <mach/octeon-model.h>
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#include <mach/cvmx-fuse.h>
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#include <mach/octeon-feature.h>
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#include <mach/cvmx-qlm.h>
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#include <mach/octeon_qlm.h>
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#include <mach/cvmx-pcie.h>
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#include <mach/cvmx-coremask.h>
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#include <mach/cvmx-agl-defs.h>
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#include <mach/cvmx-bgxx-defs.h>
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#include <mach/cvmx-ciu-defs.h>
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#include <mach/cvmx-gmxx-defs.h>
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#include <mach/cvmx-gserx-defs.h>
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#include <mach/cvmx-ilk-defs.h>
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#include <mach/cvmx-ipd-defs.h>
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#include <mach/cvmx-pexp-defs.h>
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#include <mach/cvmx-pcsx-defs.h>
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#include <mach/cvmx-pcsxx-defs.h>
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#include <mach/cvmx-pki-defs.h>
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#include <mach/cvmx-pko-defs.h>
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#include <mach/cvmx-sli-defs.h>
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#include <mach/cvmx-xcv-defs.h>
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#include <mach/cvmx-hwpko.h>
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#include <mach/cvmx-ilk.h>
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#include <mach/cvmx-pki.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-board.h>
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#include <mach/cvmx-helper-cfg.h>
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#include <mach/cvmx-helper-pki.h>
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#include <mach/cvmx-global-resources.h>
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#include <mach/cvmx-pko-internal-ports-range.h>
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#include <mach/cvmx-ilk.h>
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#include <mach/cvmx-pip.h>
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static int pki_helper_debug;
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bool cvmx_pki_dflt_init[CVMX_MAX_NODES] = { [0 ... CVMX_MAX_NODES - 1] = 1 };
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static bool cvmx_pki_dflt_bp_en[CVMX_MAX_NODES] = { [0 ... CVMX_MAX_NODES - 1] =
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true };
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static struct cvmx_pki_cluster_grp_config pki_dflt_clgrp[CVMX_MAX_NODES] = {
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{ 0, 0xf },
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{ 0, 0xf }
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};
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struct cvmx_pki_pool_config pki_dflt_pool[CVMX_MAX_NODES] = {
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[0 ... CVMX_MAX_NODES -
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1] = { .pool_num = -1, .buffer_size = 2048, .buffer_count = 0 }
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};
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struct cvmx_pki_aura_config pki_dflt_aura[CVMX_MAX_NODES] = {
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[0 ... CVMX_MAX_NODES -
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1] = { .aura_num = 0, .pool_num = -1, .buffer_count = 0 }
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};
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struct cvmx_pki_style_config pki_dflt_style[CVMX_MAX_NODES] = {
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[0 ... CVMX_MAX_NODES - 1] = { .parm_cfg = { .lenerr_en = 1,
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.maxerr_en = 1,
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.minerr_en = 1,
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.fcs_strip = 1,
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.fcs_chk = 1,
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.first_skip = 40,
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.mbuff_size = 2048 } }
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};
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struct cvmx_pki_sso_grp_config pki_dflt_sso_grp[CVMX_MAX_NODES];
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struct cvmx_pki_qpg_config pki_dflt_qpg[CVMX_MAX_NODES];
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struct cvmx_pki_pkind_config pki_dflt_pkind[CVMX_MAX_NODES];
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u64 pkind_style_map[CVMX_MAX_NODES][CVMX_PKI_NUM_PKIND] = {
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[0 ... CVMX_MAX_NODES -
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1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
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};
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/* To store the qos watcher values before they are written to pcam when watcher
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* is enabled. There is no cvmx-pip.c file exist so it ended up here
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*/
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struct cvmx_pki_legacy_qos_watcher qos_watcher[8];
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/** @INTERNAL
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* This function setsup default ltype map
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* @param node node number
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*/
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void __cvmx_helper_pki_set_dflt_ltype_map(int node)
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{
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_NONE,
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CVMX_PKI_BELTYPE_NONE);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_ENET,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_VLAN,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SNAP_PAYLD,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_ARP,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_RARP,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP4,
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CVMX_PKI_BELTYPE_IP4);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP4_OPT,
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CVMX_PKI_BELTYPE_IP4);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP6,
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CVMX_PKI_BELTYPE_IP6);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP6_OPT,
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CVMX_PKI_BELTYPE_IP6);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IPSEC_ESP,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IPFRAG,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IPCOMP,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_TCP,
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CVMX_PKI_BELTYPE_TCP);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_UDP,
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CVMX_PKI_BELTYPE_UDP);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SCTP,
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CVMX_PKI_BELTYPE_SCTP);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_UDP_VXLAN,
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CVMX_PKI_BELTYPE_UDP);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_GRE,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_NVGRE,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_GTP,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SW28,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SW29,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SW30,
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CVMX_PKI_BELTYPE_MISC);
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cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SW31,
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CVMX_PKI_BELTYPE_MISC);
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}
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/** @INTERNAL
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* This function installs the default VLAN entries to identify
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* the VLAN and set WQE[vv], WQE[vs] if VLAN is found. In 78XX
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* hardware (PKI) is not hardwired to recognize any 802.1Q VLAN
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* Ethertypes
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*
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* @param node node number
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*/
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int __cvmx_helper_pki_install_dflt_vlan(int node)
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{
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struct cvmx_pki_pcam_input pcam_input;
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struct cvmx_pki_pcam_action pcam_action;
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enum cvmx_pki_term field;
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int index;
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int bank;
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u64 cl_mask = CVMX_PKI_CLUSTER_ALL;
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memset(&pcam_input, 0, sizeof(pcam_input));
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memset(&pcam_action, 0, sizeof(pcam_action));
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) {
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/* PKI-20858 */
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int i;
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for (i = 0; i < 4; i++) {
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union cvmx_pki_clx_ecc_ctl ecc_ctl;
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ecc_ctl.u64 =
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csr_rd_node(node, CVMX_PKI_CLX_ECC_CTL(i));
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ecc_ctl.s.pcam_en = 0;
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ecc_ctl.s.pcam0_cdis = 1;
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ecc_ctl.s.pcam1_cdis = 1;
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csr_wr_node(node, CVMX_PKI_CLX_ECC_CTL(i), ecc_ctl.u64);
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}
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}
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for (field = CVMX_PKI_PCAM_TERM_ETHTYPE0;
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field < CVMX_PKI_PCAM_TERM_ETHTYPE2; field++) {
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bank = field & 0x01;
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index = cvmx_pki_pcam_entry_alloc(
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node, CVMX_PKI_FIND_AVAL_ENTRY, bank, cl_mask);
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if (index < 0) {
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debug("ERROR: Allocating pcam entry node=%d bank=%d\n",
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node, bank);
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return -1;
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}
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pcam_input.style = 0;
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pcam_input.style_mask = 0;
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pcam_input.field = field;
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pcam_input.field_mask = 0xfd;
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pcam_input.data = 0x81000000;
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pcam_input.data_mask = 0xffff0000;
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pcam_action.parse_mode_chg = CVMX_PKI_PARSE_NO_CHG;
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pcam_action.layer_type_set = CVMX_PKI_LTYPE_E_VLAN;
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pcam_action.style_add = 0;
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pcam_action.pointer_advance = 4;
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cvmx_pki_pcam_write_entry(
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node, index, cl_mask, pcam_input,
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pcam_action); /*cluster_mask in pass2*/
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index = cvmx_pki_pcam_entry_alloc(
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node, CVMX_PKI_FIND_AVAL_ENTRY, bank, cl_mask);
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if (index < 0) {
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debug("ERROR: Allocating pcam entry node=%d bank=%d\n",
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node, bank);
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return -1;
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}
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pcam_input.data = 0x88a80000;
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cvmx_pki_pcam_write_entry(node, index, cl_mask, pcam_input,
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pcam_action);
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index = cvmx_pki_pcam_entry_alloc(
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node, CVMX_PKI_FIND_AVAL_ENTRY, bank, cl_mask);
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if (index < 0) {
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debug("ERROR: Allocating pcam entry node=%d bank=%d\n",
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node, bank);
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return -1;
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}
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pcam_input.data = 0x92000000;
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cvmx_pki_pcam_write_entry(
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node, index, cl_mask, pcam_input,
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pcam_action); /* cluster_mask in pass2*/
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index = cvmx_pki_pcam_entry_alloc(
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node, CVMX_PKI_FIND_AVAL_ENTRY, bank, cl_mask);
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if (index < 0) {
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debug("ERROR: Allocating pcam entry node=%d bank=%d\n",
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node, bank);
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return -1;
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}
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pcam_input.data = 0x91000000;
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cvmx_pki_pcam_write_entry(node, index, cl_mask, pcam_input,
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pcam_action);
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}
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return 0;
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}
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static int __cvmx_helper_setup_pki_cluster_groups(int node)
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{
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u64 cl_mask;
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int cl_group;
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cl_group =
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cvmx_pki_cluster_grp_alloc(node, pki_dflt_clgrp[node].grp_num);
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if (cl_group == CVMX_RESOURCE_ALLOC_FAILED)
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return -1;
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else if (cl_group == CVMX_RESOURCE_ALREADY_RESERVED) {
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if (pki_dflt_clgrp[node].grp_num == -1)
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return -1;
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else
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return 0; /* cluster already configured, share it */
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}
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cl_mask = pki_dflt_clgrp[node].cluster_mask;
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if (pki_helper_debug)
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debug("pki-helper: setup pki cluster grp %d with cl_mask 0x%llx\n",
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(int)cl_group, (unsigned long long)cl_mask);
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cvmx_pki_attach_cluster_to_group(node, cl_group, cl_mask);
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return 0;
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}
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/**
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* This function sets up pools/auras to be used by PKI
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* @param node node number
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*/
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static int __cvmx_helper_pki_setup_fpa_pools(int node)
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{
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u64 buffer_count;
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u64 buffer_size;
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if (__cvmx_fpa3_aura_valid(pki_dflt_aura[node].aura))
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return 0; /* aura already configured, share it */
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buffer_count = pki_dflt_pool[node].buffer_count;
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buffer_size = pki_dflt_pool[node].buffer_size;
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if (buffer_count != 0) {
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pki_dflt_pool[node].pool = cvmx_fpa3_setup_fill_pool(
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node, pki_dflt_pool[node].pool_num, "PKI POOL DFLT",
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buffer_size, buffer_count, NULL);
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if (!__cvmx_fpa3_pool_valid(pki_dflt_pool[node].pool)) {
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cvmx_printf("ERROR: %s: Failed to allocate pool %d\n",
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__func__, pki_dflt_pool[node].pool_num);
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return -1;
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}
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pki_dflt_pool[node].pool_num = pki_dflt_pool[node].pool.lpool;
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if (pki_helper_debug)
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debug("%s pool %d with buffer size %d cnt %d\n",
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__func__, pki_dflt_pool[node].pool_num,
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(int)buffer_size, (int)buffer_count);
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pki_dflt_aura[node].pool_num = pki_dflt_pool[node].pool_num;
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pki_dflt_aura[node].pool = pki_dflt_pool[node].pool;
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}
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buffer_count = pki_dflt_aura[node].buffer_count;
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if (buffer_count != 0) {
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pki_dflt_aura[node].aura = cvmx_fpa3_set_aura_for_pool(
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pki_dflt_aura[node].pool, pki_dflt_aura[node].aura_num,
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"PKI DFLT AURA", buffer_size, buffer_count);
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if (!__cvmx_fpa3_aura_valid(pki_dflt_aura[node].aura)) {
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debug("ERROR: %sL Failed to allocate aura %d\n",
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__func__, pki_dflt_aura[node].aura_num);
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return -1;
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}
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}
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return 0;
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}
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static int __cvmx_helper_setup_pki_qpg_table(int node)
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{
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int offset;
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offset = cvmx_pki_qpg_entry_alloc(node, pki_dflt_qpg[node].qpg_base, 1);
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if (offset == CVMX_RESOURCE_ALLOC_FAILED)
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return -1;
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else if (offset == CVMX_RESOURCE_ALREADY_RESERVED)
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return 0; /* share the qpg table entry */
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if (pki_helper_debug)
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debug("pki-helper: set qpg entry at offset %d with port add %d aura %d grp_ok %d grp_bad %d\n",
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offset, pki_dflt_qpg[node].port_add,
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pki_dflt_qpg[node].aura_num, pki_dflt_qpg[node].grp_ok,
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pki_dflt_qpg[node].grp_bad);
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cvmx_pki_write_qpg_entry(node, offset, &pki_dflt_qpg[node]);
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return 0;
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}
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int __cvmx_helper_pki_port_setup(int node, int ipd_port)
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{
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int xiface, index;
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int pknd, style_num;
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int rs;
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struct cvmx_pki_pkind_config pkind_cfg;
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if (!cvmx_pki_dflt_init[node])
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return 0;
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xiface = cvmx_helper_get_interface_num(ipd_port);
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index = cvmx_helper_get_interface_index_num(ipd_port);
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|
||||
pknd = cvmx_helper_get_pknd(xiface, index);
|
||||
style_num = pkind_style_map[node][pknd];
|
||||
|
||||
/* try to reserve the style, if it is not configured already, reserve
|
||||
and configure it */
|
||||
rs = cvmx_pki_style_alloc(node, style_num);
|
||||
if (rs < 0) {
|
||||
if (rs == CVMX_RESOURCE_ALLOC_FAILED)
|
||||
return -1;
|
||||
} else {
|
||||
if (pki_helper_debug)
|
||||
debug("pki-helper: set style %d with default parameters\n",
|
||||
style_num);
|
||||
pkind_style_map[node][pknd] = style_num;
|
||||
/* configure style with default parameters */
|
||||
cvmx_pki_write_style_config(node, style_num,
|
||||
CVMX_PKI_CLUSTER_ALL,
|
||||
&pki_dflt_style[node]);
|
||||
}
|
||||
if (pki_helper_debug)
|
||||
debug("pki-helper: set pkind %d with initial style %d\n", pknd,
|
||||
style_num);
|
||||
/* write pkind configuration */
|
||||
pkind_cfg = pki_dflt_pkind[node];
|
||||
pkind_cfg.initial_style = style_num;
|
||||
cvmx_pki_write_pkind_config(node, pknd, &pkind_cfg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __cvmx_helper_pki_global_setup(int node)
|
||||
{
|
||||
__cvmx_helper_pki_set_dflt_ltype_map(node);
|
||||
if (!cvmx_pki_dflt_init[node])
|
||||
return 0;
|
||||
/* Setup the packet pools*/
|
||||
__cvmx_helper_pki_setup_fpa_pools(node);
|
||||
/*set up default cluster*/
|
||||
__cvmx_helper_setup_pki_cluster_groups(node);
|
||||
//__cvmx_helper_pki_setup_sso_groups(node);
|
||||
__cvmx_helper_setup_pki_qpg_table(node);
|
||||
/*
|
||||
* errata PKI-19103 backward compat has only 1 aura
|
||||
* no head line blocking
|
||||
*/
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) {
|
||||
cvmx_pki_buf_ctl_t buf_ctl;
|
||||
|
||||
buf_ctl.u64 = csr_rd_node(node, CVMX_PKI_BUF_CTL);
|
||||
buf_ctl.s.fpa_wait = 1;
|
||||
csr_wr_node(node, CVMX_PKI_BUF_CTL, buf_ctl.u64);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function Enabled the PKI hardware to
|
||||
* start accepting/processing packets.
|
||||
*
|
||||
* @param node node number
|
||||
*/
|
||||
void cvmx_helper_pki_enable(int node)
|
||||
{
|
||||
if (pki_helper_debug)
|
||||
debug("enable PKI on node %d\n", node);
|
||||
__cvmx_helper_pki_install_dflt_vlan(node);
|
||||
cvmx_pki_setup_clusters(node);
|
||||
if (cvmx_pki_dflt_bp_en[node])
|
||||
cvmx_pki_enable_backpressure(node);
|
||||
cvmx_pki_parse_enable(node, 0);
|
||||
cvmx_pki_enable(node);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function setups the qos table by allocating qpg entry and writing
|
||||
* the provided parameters to that entry (offset).
|
||||
* @param node node number.
|
||||
* @param qpg_cfg pointer to struct containing qpg configuration
|
||||
*/
|
||||
int cvmx_helper_pki_set_qpg_entry(int node, struct cvmx_pki_qpg_config *qpg_cfg)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = cvmx_pki_qpg_entry_alloc(node, qpg_cfg->qpg_base, 1);
|
||||
if (pki_helper_debug)
|
||||
debug("pki-helper:set qpg entry at offset %d\n", offset);
|
||||
if (offset == CVMX_RESOURCE_ALREADY_RESERVED) {
|
||||
debug("INFO:setup_qpg_table: offset %d already reserved\n",
|
||||
qpg_cfg->qpg_base);
|
||||
return CVMX_RESOURCE_ALREADY_RESERVED;
|
||||
} else if (offset == CVMX_RESOURCE_ALLOC_FAILED) {
|
||||
debug("ERROR:setup_qpg_table: no more entries available\n");
|
||||
return CVMX_RESOURCE_ALLOC_FAILED;
|
||||
}
|
||||
qpg_cfg->qpg_base = offset;
|
||||
cvmx_pki_write_qpg_entry(node, offset, qpg_cfg);
|
||||
return offset;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function gets all the PKI parameters related to that
|
||||
* particular port from hardware.
|
||||
* @param xipd_port xipd_port port number with node to get parameter of
|
||||
* @param port_cfg pointer to structure where to store read parameters
|
||||
*/
|
||||
void cvmx_pki_get_port_config(int xipd_port,
|
||||
struct cvmx_pki_port_config *port_cfg)
|
||||
{
|
||||
int xiface, index, pknd;
|
||||
int style, cl_mask;
|
||||
cvmx_pki_icgx_cfg_t pki_cl_msk;
|
||||
struct cvmx_xport xp = cvmx_helper_ipd_port_to_xport(xipd_port);
|
||||
|
||||
/* get the pkind used by this ipd port */
|
||||
xiface = cvmx_helper_get_interface_num(xipd_port);
|
||||
index = cvmx_helper_get_interface_index_num(xipd_port);
|
||||
pknd = cvmx_helper_get_pknd(xiface, index);
|
||||
|
||||
cvmx_pki_read_pkind_config(xp.node, pknd, &port_cfg->pkind_cfg);
|
||||
style = port_cfg->pkind_cfg.initial_style;
|
||||
pki_cl_msk.u64 = csr_rd_node(
|
||||
xp.node, CVMX_PKI_ICGX_CFG(port_cfg->pkind_cfg.cluster_grp));
|
||||
cl_mask = pki_cl_msk.s.clusters;
|
||||
cvmx_pki_read_style_config(xp.node, style, cl_mask,
|
||||
&port_cfg->style_cfg);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sets all the PKI parameters related to that
|
||||
* particular port in hardware.
|
||||
* @param xipd_port ipd port number with node to get parameter of
|
||||
* @param port_cfg pointer to structure containing port parameters
|
||||
*/
|
||||
void cvmx_pki_set_port_config(int xipd_port,
|
||||
struct cvmx_pki_port_config *port_cfg)
|
||||
{
|
||||
int xiface, index, pknd;
|
||||
int style, cl_mask;
|
||||
cvmx_pki_icgx_cfg_t pki_cl_msk;
|
||||
struct cvmx_xport xp = cvmx_helper_ipd_port_to_xport(xipd_port);
|
||||
|
||||
/* get the pkind used by this ipd port */
|
||||
xiface = cvmx_helper_get_interface_num(xipd_port);
|
||||
index = cvmx_helper_get_interface_index_num(xipd_port);
|
||||
pknd = cvmx_helper_get_pknd(xiface, index);
|
||||
|
||||
if (cvmx_pki_write_pkind_config(xp.node, pknd, &port_cfg->pkind_cfg))
|
||||
return;
|
||||
style = port_cfg->pkind_cfg.initial_style;
|
||||
pki_cl_msk.u64 = csr_rd_node(
|
||||
xp.node, CVMX_PKI_ICGX_CFG(port_cfg->pkind_cfg.cluster_grp));
|
||||
cl_mask = pki_cl_msk.s.clusters;
|
||||
cvmx_pki_write_style_config(xp.node, style, cl_mask,
|
||||
&port_cfg->style_cfg);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sets up all th eports of particular interface
|
||||
* for chosen fcs mode. (only use for backward compatibility).
|
||||
* New application can control it via init_interface calls.
|
||||
* @param node node number.
|
||||
* @param interface interface number.
|
||||
* @param nports number of ports
|
||||
* @param has_fcs 1 -- enable fcs check and fcs strip.
|
||||
* 0 -- disable fcs check.
|
||||
*/
|
||||
void cvmx_helper_pki_set_fcs_op(int node, int interface, int nports,
|
||||
int has_fcs)
|
||||
{
|
||||
int xiface, index;
|
||||
int pknd;
|
||||
unsigned int cluster = 0;
|
||||
cvmx_pki_clx_pkindx_cfg_t pkind_cfg;
|
||||
|
||||
xiface = cvmx_helper_node_interface_to_xiface(node, interface);
|
||||
for (index = 0; index < nports; index++) {
|
||||
pknd = cvmx_helper_get_pknd(xiface, index);
|
||||
while (cluster < CVMX_PKI_NUM_CLUSTER) {
|
||||
/*find the cluster in use pass2*/
|
||||
pkind_cfg.u64 = csr_rd_node(
|
||||
node, CVMX_PKI_CLX_PKINDX_CFG(pknd, cluster));
|
||||
pkind_cfg.s.fcs_pres = has_fcs;
|
||||
csr_wr_node(node,
|
||||
CVMX_PKI_CLX_PKINDX_CFG(pknd, cluster),
|
||||
pkind_cfg.u64);
|
||||
cluster++;
|
||||
}
|
||||
/* make sure fcs_strip and fcs_check is also enable/disable
|
||||
* for the style used by that port
|
||||
*/
|
||||
cvmx_pki_endis_fcs_check(node, pknd, has_fcs, has_fcs);
|
||||
cluster = 0;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user