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ARM: keystone2: Use common structure for PLLs

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Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2015-07-28 14:16:45 +05:30 committed by Tom Rini
parent 7b50e1599f
commit 74af583e9f
10 changed files with 22 additions and 51 deletions
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6
arch/arm/mach-keystone/clock-k2e.c
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@ -11,12 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

8
arch/arm/mach-keystone/clock-k2hk.c
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@ -11,14 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

7
arch/arm/mach-keystone/clock-k2l.c
View File

@ -11,13 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD

8
arch/arm/mach-keystone/clock.c
View File

@ -25,6 +25,14 @@ int __weak speeds[DEVSPEED_NUMSPDS] = {
SPD800,
};
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
static void wait_for_completion(const struct pll_init_data *data)
{
int i;

8
arch/arm/mach-keystone/include/mach/clock-k2e.h
View File

@ -50,14 +50,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
CORE_PLL,
PASS_PLL,
DDR3_PLL,
TETRIS_PLL,
};
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}

9
arch/arm/mach-keystone/include/mach/clock-k2hk.h
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@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
CORE_PLL,
PASS_PLL,
TETRIS_PLL,
DDR3A_PLL,
DDR3B_PLL,
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}

8
arch/arm/mach-keystone/include/mach/clock-k2l.h
View File

@ -51,14 +51,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
CORE_PLL,
PASS_PLL,
TETRIS_PLL,
DDR3_PLL,
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}

13
arch/arm/mach-keystone/include/mach/clock.h
View File

@ -24,7 +24,8 @@
#include <asm/arch/clock-k2l.h>
#endif
#define MAIN_PLL CORE_PLL
#define CORE_PLL MAIN_PLL
#define DDR3_PLL DDR3A_PLL
#include <asm/types.h>
@ -44,6 +45,16 @@ enum {
NUM_SPDS,
};
/* PLL identifiers */
enum {
MAIN_PLL,
TETRIS_PLL,
PASS_PLL,
DDR3A_PLL,
DDR3B_PLL,
MAX_PLL_COUNT,
};
enum clk_e {
CLK_LIST(GENERATE_ENUM)
};

4
arch/arm/mach-keystone/include/mach/hardware-k2hk.h
View File

@ -15,10 +15,6 @@
/* PA SS Registers */
#define KS2_PASS_BASE 0x02000000
/* PLL control registers */
#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_MOD 0
#define KS2_LPSC_DUMMY1 1

2
arch/arm/mach-keystone/include/mach/hardware.h
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@ -165,6 +165,8 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)