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MIPS: Flush data cache upon relocation
This patch now adds a flush to the data cache upon relocation. The current implementation is missing this. Only a comment states that it should be done. So let's really do it now. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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@ -311,6 +311,7 @@ relocate_code:
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la t3, in_ram
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lw t2, -12(t3) /* t2 <-- uboot_end_data */
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move t1, a2
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move s2, a2 /* s2 <-- destination address */
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/*
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* Fix $gp:
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@ -320,13 +321,21 @@ relocate_code:
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move t6, gp
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sub gp, CONFIG_SYS_MONITOR_BASE
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add gp, a2 /* gp now adjusted */
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sub t6, gp, t6 /* t6 <-- relocation offset */
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sub s1, gp, t6 /* s1 <-- relocation offset */
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/*
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* t0 = source address
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* t1 = target address
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* t2 = source end address
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*/
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/*
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* Save destination address and size for later usage in flush_cache()
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*/
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move s0, a1 /* save gd in s0 */
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move a0, t1 /* a0 <-- destination addr */
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sub a1, t2, t0 /* a1 <-- size */
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/* On the purple board we copy the code earlier in a special way
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* in order to solve flash problems
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*/
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@ -342,9 +351,14 @@ relocate_code:
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/* If caches were enabled, we would have to flush them here.
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*/
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/* a0 & a1 are already set up for flush_cache(start, size) */
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la t9, flush_cache
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jalr t9
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nop
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/* Jump to where we've relocated ourselves.
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*/
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addi t0, a2, in_ram - _start
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addi t0, s2, in_ram - _start
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jr t0
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nop
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@ -371,7 +385,7 @@ in_ram:
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1:
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lw t1, 0(t4)
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beqz t1, 2f
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add t1, t6
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add t1, s1
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sw t1, 0(t4)
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2:
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addi t2, 1
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@ -382,8 +396,8 @@ in_ram:
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*/
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lw t1, -12(t0) /* t1 <-- uboot_end_data */
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lw t2, -8(t0) /* t2 <-- uboot_end */
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add t1, t6 /* adjust pointers */
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add t2, t6
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add t1, s1 /* adjust pointers */
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add t2, s1
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sub t1, 4
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1:
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@ -391,10 +405,10 @@ in_ram:
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bltl t1, t2, 1b
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sw zero, 0(t1) /* delay slot */
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move a0, a1
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move a0, s0 /* a0 <-- gd */
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la t9, board_init_r
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jr t9
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move a1, a2 /* delay slot */
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move a1, s2 /* delay slot */
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.end relocate_code
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