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x86: Do cache set-up by default when booting from coreboot

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A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.

If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2021-06-27 17:51:03 -06:00 committed by Bin Meng
parent 0f5ca1d1f1
commit 7052968707
1 changed files with 14 additions and 4 deletions
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18
arch/x86/lib/init_helpers.c
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@ -18,10 +18,20 @@ int init_cache_f_r(void)
IS_ENABLED(CONFIG_FSP_VERSION2);
int ret;
if (!ll_boot_init())
return 0;
do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
/*
* Supported configurations:
*
* booting from slimbootloader - in that case the MTRRs are already set
* up
* booting with FSPv1 - MTRRs are already set up
* booting with FSPv2 - MTRRs must be set here
* booting from coreboot - in this case there is no SPL, so we set up
* the MTRRs here
* Note: if there is an SPL, then it has already set up MTRRs so we
* don't need to do that here
*/
do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
!IS_ENABLED(CONFIG_FSP_VERSION1) &&
!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
if (do_mtrr) {