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arm64: zynqmp: Remove pinctrl settings
This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Michal Simek
parent
aedd54739f
commit
704744f81b
@ -13,7 +13,6 @@
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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@ -70,8 +69,6 @@
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&can1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_default>;
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};
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&dcc {
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@ -114,8 +111,6 @@
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: phy@21 {
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reg = <21>;
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ti,rx-internal-delay = <0x8>;
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@ -126,8 +121,6 @@
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&gpio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_default>;
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};
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&gpu {
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@ -137,11 +130,6 @@
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
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tca6416_u97: gpio@20 {
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compatible = "ti,tca6416";
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@ -391,11 +379,6 @@
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
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/* PL i2c via PCA9306 - u45 */
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i2c-mux@74 { /* u34 */
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@ -545,269 +528,6 @@
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};
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_i2c0_default: i2c0-default {
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mux {
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groups = "i2c0_3_grp";
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function = "i2c0";
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};
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conf {
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groups = "i2c0_3_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c0_gpio: i2c0-gpio {
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mux {
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groups = "gpio0_14_grp", "gpio0_15_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_14_grp", "gpio0_15_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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mux {
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groups = "i2c1_4_grp";
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function = "i2c1";
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};
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conf {
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groups = "i2c1_4_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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mux {
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groups = "gpio0_16_grp", "gpio0_17_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_16_grp", "gpio0_17_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_uart0_default: uart0-default {
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mux {
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groups = "uart0_4_grp";
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function = "uart0";
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};
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conf {
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groups = "uart0_4_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO18";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO19";
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bias-disable;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_5_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_5_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO21";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO20";
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bias-disable;
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};
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};
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pinctrl_usb0_default: usb0-default {
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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conf {
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groups = "usb0_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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};
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};
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pinctrl_gem3_default: gem3-default {
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mux {
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function = "ethernet3";
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groups = "ethernet3_0_grp";
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};
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conf {
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groups = "ethernet3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
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"MIO75";
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bias-high-impedance;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
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"MIO69";
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bias-disable;
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low-power-enable;
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};
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mux-mdio {
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function = "mdio3";
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groups = "mdio3_0_grp";
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};
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conf-mdio {
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groups = "mdio3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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};
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pinctrl_can1_default: can1-default {
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mux {
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function = "can1";
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groups = "can1_6_grp";
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};
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conf {
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groups = "can1_6_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO25";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO24";
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bias-disable;
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};
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};
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pinctrl_sdhci1_default: sdhci1-default {
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mux {
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groups = "sdio1_0_grp";
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function = "sdio1";
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};
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conf {
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groups = "sdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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mux-cd {
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groups = "sdio1_0_cd_grp";
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function = "sdio1_cd";
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};
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conf-cd {
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groups = "sdio1_0_cd_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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mux-wp {
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groups = "sdio1_0_wp_grp";
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function = "sdio1_wp";
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};
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conf-wp {
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groups = "sdio1_0_wp_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_gpio_default: gpio-default {
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mux-sw {
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function = "gpio0";
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groups = "gpio0_22_grp", "gpio0_23_grp";
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};
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conf-sw {
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groups = "gpio0_22_grp", "gpio0_23_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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mux-msp {
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function = "gpio0";
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groups = "gpio0_13_grp", "gpio0_38_grp";
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};
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conf-msp {
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groups = "gpio0_13_grp", "gpio0_38_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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io-standard = <IO_STANDARD_LVCMOS18>;
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};
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conf-pull-up {
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pins = "MIO22", "MIO23";
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bias-pull-up;
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};
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conf-pull-none {
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pins = "MIO13", "MIO38";
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bias-disable;
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};
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};
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};
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&pcie {
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status = "okay";
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};
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@ -864,8 +584,6 @@
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/* SD1 with level shifter */
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&sdhci1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci1_default>;
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no-1-8-v; /* for 1.0 silicon */
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xlnx,mio_bank = <1>;
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};
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@ -876,21 +594,15 @@
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&uart0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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/* ULPI SMSC USB3320 */
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&usb0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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};
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&dwc3_0 {
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@ -1,30 +0,0 @@
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/*
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* MIO pin configuration defines for Xilinx ZynqMP
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*
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* Copyright (C) 2017 Xilinx, Inc.
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* Author: Chirag Parekh <chirag.parekh@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
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#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
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/* Bit value for IO standards */
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#define IO_STANDARD_LVCMOS33 0
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#define IO_STANDARD_LVCMOS18 1
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/* Bit values for Slew Rates */
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#define SLEW_RATE_FAST 0
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#define SLEW_RATE_SLOW 1
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/* Bit values for Pin inputs */
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#define PIN_INPUT_TYPE_CMOS 0
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#define PIN_INPUT_TYPE_SCHMITT 1
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#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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