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mips: octeon: Add cvmx-helper-xaui.c
Import cvmx-helper-xaui.c from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
Stefan Roese
parent
2e86b6ca4e
commit
6fd320cd5c
518
arch/mips/mach-octeon/cvmx-helper-xaui.c
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518
arch/mips/mach-octeon/cvmx-helper-xaui.c
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@ -0,0 +1,518 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* Functions for XAUI initialization, configuration,
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* and monitoring.
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*/
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#include <time.h>
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#include <log.h>
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#include <linux/delay.h>
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#include <mach/cvmx-regs.h>
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#include <mach/cvmx-csr.h>
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#include <mach/cvmx-bootmem.h>
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#include <mach/octeon-model.h>
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#include <mach/cvmx-fuse.h>
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#include <mach/octeon-feature.h>
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#include <mach/cvmx-qlm.h>
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#include <mach/octeon_qlm.h>
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#include <mach/cvmx-pcie.h>
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#include <mach/cvmx-coremask.h>
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#include <mach/cvmx-agl-defs.h>
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#include <mach/cvmx-bgxx-defs.h>
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#include <mach/cvmx-ciu-defs.h>
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#include <mach/cvmx-gmxx-defs.h>
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#include <mach/cvmx-ipd-defs.h>
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#include <mach/cvmx-pcsx-defs.h>
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#include <mach/cvmx-pcsxx-defs.h>
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#include <mach/cvmx-pki-defs.h>
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#include <mach/cvmx-pko-defs.h>
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#include <mach/cvmx-xcv-defs.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-board.h>
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#include <mach/cvmx-helper-cfg.h>
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int __cvmx_helper_xaui_enumerate(int xiface)
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{
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struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
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int interface = xi.interface;
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union cvmx_gmxx_hg2_control gmx_hg2_control;
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if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
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enum cvmx_qlm_mode qlm_mode =
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cvmx_qlm_get_dlm_mode(0, interface);
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if (qlm_mode == CVMX_QLM_MODE_RXAUI)
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return 1;
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return 0;
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}
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/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
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gmx_hg2_control.u64 = csr_rd(CVMX_GMXX_HG2_CONTROL(interface));
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if (gmx_hg2_control.s.hg2tx_en)
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return 16;
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else
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return 1;
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}
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/**
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* @INTERNAL
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* Probe a XAUI interface and determine the number of ports
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* connected to it. The XAUI interface should still be down
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* after this call.
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*
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* @param xiface Interface to probe
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*
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* @return Number of ports on the interface. Zero to disable.
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*/
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int __cvmx_helper_xaui_probe(int xiface)
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{
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int i, ports;
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struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
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int interface = xi.interface;
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union cvmx_gmxx_inf_mode mode;
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/*
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* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis
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* be programmed.
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
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union cvmx_ciu_qlm2 ciu_qlm;
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ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM2);
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ciu_qlm.s.txbypass = 1;
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ciu_qlm.s.txdeemph = 0x5;
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ciu_qlm.s.txmargin = 0x1a;
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csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64);
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}
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/*
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* CN63XX Pass 2.x errata G-15273 requires the QLM De-emphasis
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* be programmed when using a 156.25Mhz ref clock.
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X)) {
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/* Read the QLM speed pins */
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union cvmx_mio_rst_boot mio_rst_boot;
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mio_rst_boot.u64 = csr_rd(CVMX_MIO_RST_BOOT);
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if (mio_rst_boot.cn63xx.qlm2_spd == 0xb) {
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union cvmx_ciu_qlm2 ciu_qlm;
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ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM2);
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ciu_qlm.s.txbypass = 1;
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ciu_qlm.s.txdeemph = 0xa;
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ciu_qlm.s.txmargin = 0x1f;
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csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64);
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}
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}
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/*
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* Check if QLM is configured correct for XAUI/RXAUI, verify
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* the speed as well as mode.
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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int qlm = cvmx_qlm_interface(xiface);
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enum cvmx_qlm_mode mode = cvmx_qlm_get_mode(qlm);
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if (mode != CVMX_QLM_MODE_XAUI && mode != CVMX_QLM_MODE_RXAUI)
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return 0;
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}
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ports = __cvmx_helper_xaui_enumerate(xiface);
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if (ports <= 0)
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return 0;
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/*
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* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
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* interface needs to be enabled before IPD otherwise per port
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* backpressure may not work properly.
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*/
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mode.u64 = csr_rd(CVMX_GMXX_INF_MODE(interface));
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mode.s.en = 1;
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csr_wr(CVMX_GMXX_INF_MODE(interface), mode.u64);
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if (!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
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!OCTEON_IS_MODEL(OCTEON_CN70XX)) {
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/*
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* Setup PKO to support 16 ports for HiGig2 virtual
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* ports. We're pointing all of the PKO packet ports
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* for this interface to the XAUI. This allows us to
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* use HiGig2 backpressure per port.
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*/
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for (i = 0; i < 16; i++) {
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union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
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pko_mem_port_ptrs.u64 = 0;
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/*
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* We set each PKO port to have equal priority
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* in a round robin fashion.
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*/
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pko_mem_port_ptrs.s.static_p = 0;
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pko_mem_port_ptrs.s.qos_mask = 0xff;
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/* All PKO ports map to the same XAUI hardware port */
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pko_mem_port_ptrs.s.eid = interface * 4;
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pko_mem_port_ptrs.s.pid = interface * 16 + i;
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pko_mem_port_ptrs.s.bp_port = interface * 16 + i;
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csr_wr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
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}
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}
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return ports;
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}
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/**
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* @INTERNAL
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* Bringup XAUI interface. After this call packet I/O should be
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* fully functional.
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*
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* @param interface to bring up
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*
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* @return Zero on success, negative on failure
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*/
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int __cvmx_helper_xaui_link_init(int interface)
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{
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union cvmx_gmxx_prtx_cfg gmx_cfg;
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union cvmx_pcsxx_control1_reg xaui_ctl;
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union cvmx_pcsxx_misc_ctl_reg misc_ctl;
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union cvmx_gmxx_tx_xaui_ctl tx_ctl;
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/* (1) Interface has already been enabled. */
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/* (2) Disable GMX. */
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misc_ctl.u64 = csr_rd(CVMX_PCSXX_MISC_CTL_REG(interface));
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misc_ctl.s.gmxeno = 1;
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csr_wr(CVMX_PCSXX_MISC_CTL_REG(interface), misc_ctl.u64);
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/* (3) Disable GMX and PCSX interrupts. */
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csr_wr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
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csr_wr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
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csr_wr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
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/* (4) Bring up the PCSX and GMX reconciliation layer. */
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/* (4)a Set polarity and lane swapping. */
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/* (4)b */
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tx_ctl.u64 = csr_rd(CVMX_GMXX_TX_XAUI_CTL(interface));
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/* Enable better IFG packing and improves performance */
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tx_ctl.s.dic_en = 1;
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tx_ctl.s.uni_en = 0;
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csr_wr(CVMX_GMXX_TX_XAUI_CTL(interface), tx_ctl.u64);
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/* (4)c Aply reset sequence */
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xaui_ctl.u64 = csr_rd(CVMX_PCSXX_CONTROL1_REG(interface));
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xaui_ctl.s.lo_pwr = 0;
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/*
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* Errata G-15618 requires disabling PCS soft reset in some
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* OCTEON II models.
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*/
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if (!OCTEON_IS_MODEL(OCTEON_CN63XX) &&
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!OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) &&
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!OCTEON_IS_MODEL(OCTEON_CN68XX))
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xaui_ctl.s.reset = 1;
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csr_wr(CVMX_PCSXX_CONTROL1_REG(interface), xaui_ctl.u64);
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if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X) && interface != 1) {
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/*
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* Note that GMX 1 was skipped as GMX0 is on the same
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* QLM and will always be done first
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*
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* Workaround for Errata (G-16467).
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*/
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int qlm = interface;
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#ifdef CVMX_QLM_DUMP_STATE
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debug("%s:%d: XAUI%d: Applying workaround for Errata G-16467\n",
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__func__, __LINE__, qlm);
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cvmx_qlm_display_registers(qlm);
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debug("\n");
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#endif
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/*
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* This workaround only applies to QLMs running XAUI
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* at 6.25Ghz
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*/
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if ((cvmx_qlm_get_gbaud_mhz(qlm) == 6250) &&
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(cvmx_qlm_jtag_get(qlm, 0, "clkf_byp") != 20)) {
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/* Wait 100us for links to stabalize */
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udelay(100);
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cvmx_qlm_jtag_set(qlm, -1, "clkf_byp", 20);
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/* Allow the QLM to exit reset */
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cvmx_qlm_jtag_set(qlm, -1, "cfg_rst_n_clr", 0);
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/* Wait 100us for links to stabalize */
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udelay(100);
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/* Allow TX on QLM */
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cvmx_qlm_jtag_set(qlm, -1, "cfg_tx_idle_set", 0);
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}
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#ifdef CVMX_QLM_DUMP_STATE
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debug("%s:%d: XAUI%d: Done applying workaround for Errata G-16467\n",
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__func__, __LINE__, qlm);
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cvmx_qlm_display_registers(qlm);
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debug("\n\n");
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#endif
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}
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/* Wait for PCS to come out of reset */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_CONTROL1_REG(interface),
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cvmx_pcsxx_control1_reg_t, reset, ==, 0,
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10000))
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return -1;
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/* Wait for PCS to be aligned */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_10GBX_STATUS_REG(interface),
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cvmx_pcsxx_10gbx_status_reg_t, alignd, ==, 1,
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10000))
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return -1;
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/* Wait for RX to be ready */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_RX_XAUI_CTL(interface),
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cvmx_gmxx_rx_xaui_ctl_t, status, ==, 0,
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10000))
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return -1;
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/* (6) Configure GMX */
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/* Wait for GMX RX to be idle */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface),
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cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000))
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return -1;
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/* Wait for GMX TX to be idle */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface),
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cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
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return -1;
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/* GMX configure */
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gmx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(0, interface));
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gmx_cfg.s.speed = 1;
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gmx_cfg.s.speed_msb = 0;
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gmx_cfg.s.slottime = 1;
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csr_wr(CVMX_GMXX_TX_PRTS(interface), 1);
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csr_wr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
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csr_wr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
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csr_wr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
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/* Wait for receive link */
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if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS1_REG(interface),
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cvmx_pcsxx_status1_reg_t, rcv_lnk, ==, 1,
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10000))
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return -1;
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if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface),
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cvmx_pcsxx_status2_reg_t, xmtflt, ==, 0,
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10000))
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return -1;
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if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface),
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cvmx_pcsxx_status2_reg_t, rcvflt, ==, 0,
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10000))
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return -1;
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/* (8) Enable packet reception */
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misc_ctl.s.gmxeno = 0;
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csr_wr(CVMX_PCSXX_MISC_CTL_REG(interface), misc_ctl.u64);
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/* Clear all error interrupts before enabling the interface. */
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csr_wr(CVMX_GMXX_RXX_INT_REG(0, interface), ~0x0ull);
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csr_wr(CVMX_GMXX_TX_INT_REG(interface), ~0x0ull);
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csr_wr(CVMX_PCSXX_INT_REG(interface), ~0x0ull);
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/* Enable GMX */
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gmx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(0, interface));
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gmx_cfg.s.en = 1;
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csr_wr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
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return 0;
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}
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/**
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* @INTERNAL
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* Bringup and enable a XAUI interface. After this call packet
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* I/O should be fully functional. This is called with IPD
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* enabled but PKO disabled.
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*
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* @param xiface Interface to bring up
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*
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* @return Zero on success, negative on failure
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*/
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int __cvmx_helper_xaui_enable(int xiface)
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{
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struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
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int interface = xi.interface;
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__cvmx_helper_setup_gmx(interface, 1);
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/* Setup PKND and BPID */
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if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
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union cvmx_gmxx_bpid_msk bpid_msk;
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union cvmx_gmxx_bpid_mapx bpid_map;
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union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
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union cvmx_gmxx_txx_append gmxx_txx_append_cfg;
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/* Setup PKIND */
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gmxx_prtx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(0, interface));
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gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, 0);
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csr_wr(CVMX_GMXX_PRTX_CFG(0, interface), gmxx_prtx_cfg.u64);
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/* Setup BPID */
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bpid_map.u64 = csr_rd(CVMX_GMXX_BPID_MAPX(0, interface));
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bpid_map.s.val = 1;
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bpid_map.s.bpid = cvmx_helper_get_bpid(interface, 0);
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csr_wr(CVMX_GMXX_BPID_MAPX(0, interface), bpid_map.u64);
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bpid_msk.u64 = csr_rd(CVMX_GMXX_BPID_MSK(interface));
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bpid_msk.s.msk_or |= 1;
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bpid_msk.s.msk_and &= ~1;
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csr_wr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64);
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/* CN68XX adds the padding and FCS in PKO, not GMX */
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gmxx_txx_append_cfg.u64 =
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csr_rd(CVMX_GMXX_TXX_APPEND(0, interface));
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gmxx_txx_append_cfg.s.fcs = 0;
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gmxx_txx_append_cfg.s.pad = 0;
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csr_wr(CVMX_GMXX_TXX_APPEND(0, interface),
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gmxx_txx_append_cfg.u64);
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}
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/* 70XX eval boards use Marvel phy, set disparity accordingly. */
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if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
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union cvmx_gmxx_rxaui_ctl rxaui_ctl;
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rxaui_ctl.u64 = csr_rd(CVMX_GMXX_RXAUI_CTL(interface));
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rxaui_ctl.s.disparity = 1;
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csr_wr(CVMX_GMXX_RXAUI_CTL(interface), rxaui_ctl.u64);
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}
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__cvmx_helper_xaui_link_init(interface);
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return 0;
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}
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/**
|
||||
* @INTERNAL
|
||||
* Return the link state of an IPD/PKO port as returned by
|
||||
* auto negotiation. The result of this function may not match
|
||||
* Octeon's link config if auto negotiation has changed since
|
||||
* the last call to cvmx_helper_link_set().
|
||||
*
|
||||
* @param ipd_port IPD/PKO port to query
|
||||
*
|
||||
* @return Link state
|
||||
*/
|
||||
cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
|
||||
{
|
||||
int interface = cvmx_helper_get_interface_num(ipd_port);
|
||||
union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
|
||||
union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
|
||||
union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
|
||||
cvmx_helper_link_info_t result;
|
||||
|
||||
gmxx_tx_xaui_ctl.u64 = csr_rd(CVMX_GMXX_TX_XAUI_CTL(interface));
|
||||
gmxx_rx_xaui_ctl.u64 = csr_rd(CVMX_GMXX_RX_XAUI_CTL(interface));
|
||||
pcsxx_status1_reg.u64 = csr_rd(CVMX_PCSXX_STATUS1_REG(interface));
|
||||
result.u64 = 0;
|
||||
|
||||
/* Only return a link if both RX and TX are happy */
|
||||
if (gmxx_tx_xaui_ctl.s.ls == 0 && gmxx_rx_xaui_ctl.s.status == 0 &&
|
||||
pcsxx_status1_reg.s.rcv_lnk == 1) {
|
||||
union cvmx_pcsxx_misc_ctl_reg misc_ctl;
|
||||
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 1;
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
|
||||
union cvmx_mio_qlmx_cfg qlm_cfg;
|
||||
int lanes;
|
||||
int qlm = (interface == 1) ? 0 : interface;
|
||||
|
||||
qlm_cfg.u64 = csr_rd(CVMX_MIO_QLMX_CFG(qlm));
|
||||
result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
|
||||
lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4;
|
||||
result.s.speed *= lanes;
|
||||
} else if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
|
||||
int qlm = cvmx_qlm_interface(interface);
|
||||
|
||||
result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
|
||||
result.s.speed *= 4;
|
||||
} else {
|
||||
result.s.speed = 10000;
|
||||
}
|
||||
misc_ctl.u64 = csr_rd(CVMX_PCSXX_MISC_CTL_REG(interface));
|
||||
if (misc_ctl.s.gmxeno)
|
||||
__cvmx_helper_xaui_link_init(interface);
|
||||
} else {
|
||||
/* Disable GMX and PCSX interrupts. */
|
||||
csr_wr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
|
||||
csr_wr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
|
||||
csr_wr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @INTERNAL
|
||||
* Configure an IPD/PKO port for the specified link state. This
|
||||
* function does not influence auto negotiation at the PHY level.
|
||||
* The passed link state must always match the link state returned
|
||||
* by cvmx_helper_link_get(). It is normally best to use
|
||||
* cvmx_helper_link_autoconf() instead.
|
||||
*
|
||||
* @param ipd_port IPD/PKO port to configure
|
||||
* @param link_info The new link state
|
||||
*
|
||||
* @return Zero on success, negative on failure
|
||||
*/
|
||||
int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
|
||||
{
|
||||
int interface = cvmx_helper_get_interface_num(ipd_port);
|
||||
union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
|
||||
union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
|
||||
|
||||
gmxx_tx_xaui_ctl.u64 = csr_rd(CVMX_GMXX_TX_XAUI_CTL(interface));
|
||||
gmxx_rx_xaui_ctl.u64 = csr_rd(CVMX_GMXX_RX_XAUI_CTL(interface));
|
||||
|
||||
/* If the link shouldn't be up, then just return */
|
||||
if (!link_info.s.link_up)
|
||||
return 0;
|
||||
|
||||
/* Do nothing if both RX and TX are happy */
|
||||
if (gmxx_tx_xaui_ctl.s.ls == 0 && gmxx_rx_xaui_ctl.s.status == 0)
|
||||
return 0;
|
||||
|
||||
/* Bring the link up */
|
||||
return __cvmx_helper_xaui_link_init(interface);
|
||||
}
|
||||
|
||||
/**
|
||||
* @INTERNAL
|
||||
* Configure a port for internal and/or external loopback. Internal loopback
|
||||
* causes packets sent by the port to be received by Octeon. External loopback
|
||||
* causes packets received from the wire to sent out again.
|
||||
*
|
||||
* @param ipd_port IPD/PKO port to loopback.
|
||||
* @param enable_internal
|
||||
* Non zero if you want internal loopback
|
||||
* @param enable_external
|
||||
* Non zero if you want external loopback
|
||||
*
|
||||
* @return Zero on success, negative on failure.
|
||||
*/
|
||||
extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
|
||||
int enable_internal,
|
||||
int enable_external)
|
||||
{
|
||||
int interface = cvmx_helper_get_interface_num(ipd_port);
|
||||
union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
|
||||
union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
|
||||
|
||||
/* Set the internal loop */
|
||||
pcsxx_control1_reg.u64 = csr_rd(CVMX_PCSXX_CONTROL1_REG(interface));
|
||||
pcsxx_control1_reg.s.loopbck1 = enable_internal;
|
||||
csr_wr(CVMX_PCSXX_CONTROL1_REG(interface), pcsxx_control1_reg.u64);
|
||||
|
||||
/* Set the external loop */
|
||||
gmxx_xaui_ext_loopback.u64 =
|
||||
csr_rd(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
|
||||
gmxx_xaui_ext_loopback.s.en = enable_external;
|
||||
csr_wr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
|
||||
gmxx_xaui_ext_loopback.u64);
|
||||
|
||||
/* Take the link through a reset */
|
||||
return __cvmx_helper_xaui_link_init(interface);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user