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ARM: MX5: Fix broken leftover TO-2 errata workaround

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This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.

Signed-off-by: David Jander <david@protonic.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
David Jander 2011-07-14 03:58:57 +00:00 committed by Stefano Babic
parent 9f008bb47d
commit 6e25b6ce5d
1 changed files with 5 additions and 1 deletions
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6
arch/arm/cpu/armv7/mx5/lowlevel_init.S
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@ -39,10 +39,14 @@
orr r0, r0, #(1 << 23) /* disable write allocate combine */
orr r0, r0, #(1 << 22) /* disable write allocate */
cmp r3, #0x10 /* r3 contains the silicon rev */
#if defined(CONFIG_MX51)
ldr r1, =0x0
ldr r3, [r1, #ROM_SI_REV]
cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
orrls r0, r0, #(1 << 25)
#endif
mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */