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mmc: fsl_esdhc: Fix 'Internal clock never stabilised.' error

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Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
fixed amount of time like it was before commit 6f883e501b ("mmc:
fsl_esdhc: Add emmc hs200 support").

This change fixes error 'Internal clock never stabilised.' which is printed
on P2020 board at every access to SD card.

Fixes: 6f883e501b ("mmc: fsl_esdhc: Add emmc hs200 support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Pali Rohár 2022-04-29 20:27:34 +02:00 committed by Jaehoon Chung
parent 86feeab3dc
commit 6dcf1c28dd
1 changed files with 17 additions and 0 deletions
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17
drivers/mmc/fsl_esdhc.c
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@ -504,6 +504,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
u32 time_out; u32 time_out;
u32 value; u32 value;
uint clk; uint clk;
u32 hostver;
if (clock < mmc->cfg->f_min) if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min; clock = mmc->cfg->f_min;
@ -544,6 +545,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
/* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
hostver = esdhc_read32(&priv->esdhc_regs->hostver);
if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
udelay(10000);
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
return;
}
time_out = 20; time_out = 20;
value = PRSSTAT_SDSTB; value = PRSSTAT_SDSTB;
while (!(esdhc_read32(&regs->prsstat) & value)) { while (!(esdhc_read32(&regs->prsstat) & value)) {
@ -563,6 +572,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
struct fsl_esdhc *regs = priv->esdhc_regs; struct fsl_esdhc *regs = priv->esdhc_regs;
u32 value; u32 value;
u32 time_out; u32 time_out;
u32 hostver;
value = esdhc_read32(&regs->sysctl); value = esdhc_read32(&regs->sysctl);
@ -573,6 +583,13 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
esdhc_write32(&regs->sysctl, value); esdhc_write32(&regs->sysctl, value);
/* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
hostver = esdhc_read32(&priv->esdhc_regs->hostver);
if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
udelay(10000);
return;
}
time_out = 20; time_out = 20;
value = PRSSTAT_SDSTB; value = PRSSTAT_SDSTB;
while (!(esdhc_read32(&regs->prsstat) & value)) { while (!(esdhc_read32(&regs->prsstat) & value)) {