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ARM: Tegra210: Add SoC code/include files for T210

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All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.

Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.

Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Tom Warren 2015-02-02 13:22:29 -07:00
parent 56079eccd1
commit 6c43f6c8d9
18 changed files with 3275 additions and 0 deletions
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91
arch/arm/include/asm/arch-tegra210/ahb.h Normal file
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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_AHB_H_
#define _TEGRA210_AHB_H_
struct ahb_ctlr {
u32 reserved0; /* 00h */
u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
u32 reserved6[2]; /* 18h, 1ch */
u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
u32 reserved13[2]; /* 38h, 3ch */
u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
u32 reserved15; /* 44h */
u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
u32 reserved17; /* 4ch */
u32 gizmo_se; /* _GIZMO_SE_0, 50h */
u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
u32 reserved20[3]; /* 58h, 5ch, 60h */
u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
u32 reserved22[3]; /* 68h, 6ch, 70h */
u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
u32 reserved30[13]; /* 90h ~ c0h */
u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
u32 reserved32[5]; /* c8h ~ d8h */
u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
u32 arbitration_ahb_mem_wrque_mst_id;
u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
u32 reserved46[4]; /* 110h ~ 11ch */
u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
u32 axicif_fastsync0_cpuclk_to_mcclk;
/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
u32 axicif_fastsync1_cpuclk_to_mcclk;
/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
u32 axicif_fastsync2_cpuclk_to_mcclk;
/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
u32 axicif_fastsync0_mcclk_to_cpuclk;
/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
u32 axicif_fastsync1_mcclk_to_cpuclk;
/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
u32 axicif_fastsync2_mcclk_to_cpuclk;
};
#define PPSB_STOPCLK_ENABLE (1 << 2)
#define GIZ_ENABLE_SPLIT (1 << 0)
#define GIZ_ENB_FAST_REARB (1 << 2)
#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
#define GIZ_USB_IMMEDIATE (1 << 18)
/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
#endif /* _TEGRA210_AHB_H_ */

566
arch/arm/include/asm/arch-tegra210/clock-tables.h Normal file
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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 clock PLL tables */
#ifndef _TEGRA210_CLOCK_TABLES_H_
#define _TEGRA210_CLOCK_TABLES_H_
/* The PLLs supported by the hardware */
enum clock_id {
CLOCK_ID_FIRST,
CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
CLOCK_ID_MEMORY,
CLOCK_ID_PERIPH,
CLOCK_ID_AUDIO,
CLOCK_ID_USB,
CLOCK_ID_DISPLAY,
/* now the simple ones */
CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_COUNT, /* number of PLLs */
/*
* These are clock IDs that are used in table clock_source[][]
* but will not be assigned as a clock source for any peripheral.
*/
CLOCK_ID_DISPLAY2,
CLOCK_ID_CGENERAL_0,
CLOCK_ID_CGENERAL_1,
CLOCK_ID_CGENERAL2,
CLOCK_ID_CGENERAL3,
CLOCK_ID_CGENERAL4_0,
CLOCK_ID_CGENERAL4_1,
CLOCK_ID_CGENERAL4_2,
CLOCK_ID_MEMORY2,
CLOCK_ID_SRC2,
CLOCK_ID_NONE = -1,
};
/* The clocks supported by the hardware */
enum periph_id {
PERIPH_ID_FIRST,
/* Low word: 31:0 (DEVICES_L) */
PERIPH_ID_CPU = PERIPH_ID_FIRST,
PERIPH_ID_COP,
PERIPH_ID_TRIGSYS,
PERIPH_ID_ISPB,
PERIPH_ID_RESERVED4,
PERIPH_ID_TMR,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
/* 8 */
PERIPH_ID_GPIO,
PERIPH_ID_SDMMC2,
PERIPH_ID_SPDIF,
PERIPH_ID_I2S2,
PERIPH_ID_I2C1,
PERIPH_ID_RESERVED13,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC4,
/* 16 */
PERIPH_ID_TCW,
PERIPH_ID_PWM,
PERIPH_ID_I2S3,
PERIPH_ID_RESERVED19,
PERIPH_ID_VI,
PERIPH_ID_RESERVED21,
PERIPH_ID_USBD,
PERIPH_ID_ISP,
/* 24 */
PERIPH_ID_RESERVED24,
PERIPH_ID_RESERVED25,
PERIPH_ID_DISP2,
PERIPH_ID_DISP1,
PERIPH_ID_HOST1X,
PERIPH_ID_VCP,
PERIPH_ID_I2S1,
PERIPH_ID_CACHE2,
/* Middle word: 63:32 (DEVICES_H) */
PERIPH_ID_MEM,
PERIPH_ID_AHBDMA,
PERIPH_ID_APBDMA,
PERIPH_ID_RESERVED35,
PERIPH_ID_RESERVED36,
PERIPH_ID_STAT_MON,
PERIPH_ID_RESERVED38,
PERIPH_ID_FUSE,
/* 40 */
PERIPH_ID_KFUSE,
PERIPH_ID_SBC1,
PERIPH_ID_SNOR,
PERIPH_ID_RESERVED43,
PERIPH_ID_SBC2,
PERIPH_ID_XIO,
PERIPH_ID_SBC3,
PERIPH_ID_I2C5,
/* 48 */
PERIPH_ID_DSI,
PERIPH_ID_RESERVED49,
PERIPH_ID_HSI,
PERIPH_ID_HDMI,
PERIPH_ID_CSI,
PERIPH_ID_RESERVED53,
PERIPH_ID_I2C2,
PERIPH_ID_UART3,
/* 56 */
PERIPH_ID_MIPI_CAL,
PERIPH_ID_EMC,
PERIPH_ID_USB2,
PERIPH_ID_USB3,
PERIPH_ID_RESERVED60,
PERIPH_ID_VDE,
PERIPH_ID_BSEA,
PERIPH_ID_BSEV,
/* Upper word 95:64 (DEVICES_U) */
PERIPH_ID_RESERVED64,
PERIPH_ID_UART4,
PERIPH_ID_UART5,
PERIPH_ID_I2C3,
PERIPH_ID_SBC4,
PERIPH_ID_SDMMC3,
PERIPH_ID_PCIE,
PERIPH_ID_OWR,
/* 72 */
PERIPH_ID_AFI,
PERIPH_ID_CORESIGHT,
PERIPH_ID_PCIEXCLK,
PERIPH_ID_AVPUCQ,
PERIPH_ID_LA,
PERIPH_ID_TRACECLKIN,
PERIPH_ID_SOC_THERM,
PERIPH_ID_DTV,
/* 80 */
PERIPH_ID_RESERVED80,
PERIPH_ID_I2CSLOW,
PERIPH_ID_DSIB,
PERIPH_ID_TSEC,
PERIPH_ID_RESERVED84,
PERIPH_ID_RESERVED85,
PERIPH_ID_RESERVED86,
PERIPH_ID_EMUCIF,
/* 88 */
PERIPH_ID_RESERVED88,
PERIPH_ID_XUSB_HOST,
PERIPH_ID_RESERVED90,
PERIPH_ID_MSENC,
PERIPH_ID_RESERVED92,
PERIPH_ID_RESERVED93,
PERIPH_ID_RESERVED94,
PERIPH_ID_XUSB_DEV,
PERIPH_ID_VW_FIRST,
/* V word: 31:0 */
PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
PERIPH_ID_CPULP,
PERIPH_ID_V_RESERVED2,
PERIPH_ID_MSELECT,
PERIPH_ID_V_RESERVED4,
PERIPH_ID_I2S4,
PERIPH_ID_I2S5,
PERIPH_ID_I2C4,
/* 104 */
PERIPH_ID_SBC5,
PERIPH_ID_SBC6,
PERIPH_ID_AHUB,
PERIPH_ID_APB2APE,
PERIPH_ID_V_RESERVED12,
PERIPH_ID_V_RESERVED13,
PERIPH_ID_V_RESERVED14,
PERIPH_ID_HDA2CODEC2X,
/* 112 */
PERIPH_ID_ATOMICS,
PERIPH_ID_V_RESERVED17,
PERIPH_ID_V_RESERVED18,
PERIPH_ID_V_RESERVED19,
PERIPH_ID_V_RESERVED20,
PERIPH_ID_V_RESERVED21,
PERIPH_ID_V_RESERVED22,
PERIPH_ID_ACTMON,
/* 120 */
PERIPH_ID_EXTPERIPH1,
PERIPH_ID_EXTPERIPH2,
PERIPH_ID_EXTPERIPH3,
PERIPH_ID_OOB,
PERIPH_ID_SATA,
PERIPH_ID_HDA,
PERIPH_ID_V_RESERVED30,
PERIPH_ID_V_RESERVED31,
/* W word: 31:0 */
PERIPH_ID_HDA2HDMICODEC,
PERIPH_ID_SATACOLD,
PERIPH_ID_W_RESERVED2,
PERIPH_ID_W_RESERVED3,
PERIPH_ID_W_RESERVED4,
PERIPH_ID_W_RESERVED5,
PERIPH_ID_W_RESERVED6,
PERIPH_ID_W_RESERVED7,
/* 136 */
PERIPH_ID_CEC,
PERIPH_ID_W_RESERVED9,
PERIPH_ID_W_RESERVED10,
PERIPH_ID_W_RESERVED11,
PERIPH_ID_W_RESERVED12,
PERIPH_ID_W_RESERVED13,
PERIPH_ID_XUSB_PADCTL,
PERIPH_ID_W_RESERVED15,
/* 144 */
PERIPH_ID_W_RESERVED16,
PERIPH_ID_W_RESERVED17,
PERIPH_ID_W_RESERVED18,
PERIPH_ID_W_RESERVED19,
PERIPH_ID_W_RESERVED20,
PERIPH_ID_ENTROPY,
PERIPH_ID_DDS,
PERIPH_ID_W_RESERVED23,
/* 152 */
PERIPH_ID_W_RESERVED24,
PERIPH_ID_W_RESERVED25,
PERIPH_ID_W_RESERVED26,
PERIPH_ID_DVFS,
PERIPH_ID_XUSB_SS,
PERIPH_ID_W_RESERVED29,
PERIPH_ID_W_RESERVED30,
PERIPH_ID_W_RESERVED31,
PERIPH_ID_X_FIRST,
/* X word: 31:0 */
PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
PERIPH_ID_X_RESERVED1,
PERIPH_ID_X_RESERVED2,
PERIPH_ID_X_RESERVED3,
PERIPH_ID_CAM_MCLK,
PERIPH_ID_CAM_MCLK2,
PERIPH_ID_I2C6,
PERIPH_ID_X_RESERVED7,
/* 168 */
PERIPH_ID_X_RESERVED8,
PERIPH_ID_X_RESERVED9,
PERIPH_ID_X_RESERVED10,
PERIPH_ID_VIM2_CLK,
PERIPH_ID_X_RESERVED12,
PERIPH_ID_X_RESERVED13,
PERIPH_ID_EMC_DLL,
PERIPH_ID_X_RESERVED15,
/* 176 */
PERIPH_ID_HDMI_AUDIO,
PERIPH_ID_CLK72MHZ,
PERIPH_ID_VIC,
PERIPH_ID_X_RESERVED19,
PERIPH_ID_X_RESERVED20,
PERIPH_ID_DPAUX,
PERIPH_ID_SOR0,
PERIPH_ID_X_RESERVED23,
/* 184 */
PERIPH_ID_GPU,
PERIPH_ID_X_RESERVED25,
PERIPH_ID_X_RESERVED26,
PERIPH_ID_X_RESERVED27,
PERIPH_ID_X_RESERVED28,
PERIPH_ID_X_RESERVED29,
PERIPH_ID_X_RESERVED30,
PERIPH_ID_X_RESERVED31,
PERIPH_ID_Y_FIRST,
/* Y word: 31:0 (192:223) */
PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
PERIPH_ID_Y_RESERVED1,
PERIPH_ID_Y_RESERVED2,
PERIPH_ID_Y_RESERVED3,
PERIPH_ID_Y_RESERVED4,
PERIPH_ID_Y_RESERVED5,
PERIPH_ID_APE,
PERIPH_ID_Y_RESERVED7,
/* 200 */
PERIPH_ID_MC_CDPA,
PERIPH_ID_Y_RESERVED9,
PERIPH_ID_Y_RESERVED10,
PERIPH_ID_Y_RESERVED11,
PERIPH_ID_Y_RESERVED12,
PERIPH_ID_PEX_USB_UPHY,
PERIPH_ID_Y_RESERVED14,
PERIPH_ID_Y_RESERVED15,
/* 208 */
PERIPH_ID_VI_I2C,
PERIPH_ID_Y_RESERVED17,
PERIPH_ID_Y_RESERVED18,
PERIPH_ID_QSPI,
PERIPH_ID_Y_RESERVED20,
PERIPH_ID_Y_RESERVED21,
PERIPH_ID_Y_RESERVED22,
PERIPH_ID_Y_RESERVED23,
/* 216 */
PERIPH_ID_Y_RESERVED24,
PERIPH_ID_Y_RESERVED25,
PERIPH_ID_Y_RESERVED26,
PERIPH_ID_Y_RESERVED27,
PERIPH_ID_Y_RESERVED28,
PERIPH_ID_Y_RESERVED29,
PERIPH_ID_Y_RESERVED30,
PERIPH_ID_Y_RESERVED31,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
enum pll_out_id {
PLL_OUT1,
PLL_OUT2,
PLL_OUT3,
PLL_OUT4
};
/*
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
* confusion bewteen PERIPH_ID_... and PERIPHC_...
*
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
* confusing.
*/
enum periphc_internal_id {
/* 0x00 */
PERIPHC_I2S2,
PERIPHC_I2S3,
PERIPHC_SPDIF_OUT,
PERIPHC_SPDIF_IN,
PERIPHC_PWM,
PERIPHC_05h,
PERIPHC_SBC2,
PERIPHC_SBC3,
/* 0x08 */
PERIPHC_08h,
PERIPHC_I2C1,
PERIPHC_I2C5,
PERIPHC_0bh,
PERIPHC_0ch,
PERIPHC_SBC1,
PERIPHC_DISP1,
PERIPHC_DISP2,
/* 0x10 */
PERIPHC_10h,
PERIPHC_11h,
PERIPHC_VI,
PERIPHC_13h,
PERIPHC_SDMMC1,
PERIPHC_SDMMC2,
PERIPHC_G3D,
PERIPHC_G2D,
/* 0x18 */
PERIPHC_18h,
PERIPHC_SDMMC4,
PERIPHC_VFIR,
PERIPHC_1Bh,
PERIPHC_1Ch,
PERIPHC_HSI,
PERIPHC_UART1,
PERIPHC_UART2,
/* 0x20 */
PERIPHC_HOST1X,
PERIPHC_21h,
PERIPHC_22h,
PERIPHC_HDMI,
PERIPHC_24h,
PERIPHC_25h,
PERIPHC_I2C2,
PERIPHC_EMC,
/* 0x28 */
PERIPHC_UART3,
PERIPHC_29h,
PERIPHC_VI_SENSOR,
PERIPHC_2bh,
PERIPHC_2ch,
PERIPHC_SBC4,
PERIPHC_I2C3,
PERIPHC_SDMMC3,
/* 0x30 */
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_VDE,
PERIPHC_OWR,
PERIPHC_NOR,
PERIPHC_CSITE,
PERIPHC_I2S1,
PERIPHC_DTV,
/* 0x38 */
PERIPHC_38h,
PERIPHC_39h,
PERIPHC_3ah,
PERIPHC_3bh,
PERIPHC_MSENC,
PERIPHC_TSEC,
PERIPHC_3eh,
PERIPHC_OSC,
PERIPHC_VW_FIRST,
/* 0x40 */
PERIPHC_40h = PERIPHC_VW_FIRST,
PERIPHC_MSELECT,
PERIPHC_TSENSOR,
PERIPHC_I2S4,
PERIPHC_I2S5,
PERIPHC_I2C4,
PERIPHC_SBC5,
PERIPHC_SBC6,
/* 0x48 */
PERIPHC_AUDIO,
PERIPHC_49h,
PERIPHC_4ah,
PERIPHC_4bh,
PERIPHC_4ch,
PERIPHC_HDA2CODEC2X,
PERIPHC_ACTMON,
PERIPHC_EXTPERIPH1,
/* 0x50 */
PERIPHC_EXTPERIPH2,
PERIPHC_EXTPERIPH3,
PERIPHC_52h,
PERIPHC_I2CSLOW,
PERIPHC_SYS,
PERIPHC_55h,
PERIPHC_56h,
PERIPHC_57h,
/* 0x58 */
PERIPHC_58h,
PERIPHC_59h,
PERIPHC_5ah,
PERIPHC_5bh,
PERIPHC_SATAOOB,
PERIPHC_SATA,
PERIPHC_HDA, /* 0x428 */
PERIPHC_5fh,
PERIPHC_X_FIRST,
/* 0x60 */
PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
PERIPHC_XUSB_FALCON,
PERIPHC_XUSB_FS,
PERIPHC_XUSB_CORE_DEV,
PERIPHC_XUSB_SS,
PERIPHC_CILAB,
PERIPHC_CILCD,
PERIPHC_CILE,
/* 0x68 */
PERIPHC_DSIA_LP,
PERIPHC_DSIB_LP,
PERIPHC_ENTROPY,
PERIPHC_DVFS_REF,
PERIPHC_DVFS_SOC,
PERIPHC_TRACECLKIN,
PERIPHC_6Eh,
PERIPHC_6Fh,
/* 0x70 */
PERIPHC_EMC_LATENCY,
PERIPHC_SOC_THERM,
PERIPHC_72h,
PERIPHC_73h,
PERIPHC_74h,
PERIPHC_75h,
PERIPHC_VI_SENSOR2,
PERIPHC_I2C6,
/* 0x78 */
PERIPHC_78h,
PERIPHC_EMC_DLL,
PERIPHC_7ah,
PERIPHC_CLK72MHZ,
PERIPHC_7ch,
PERIPHC_7dh,
PERIPHC_VIC,
PERIPHC_7fh,
PERIPHC_Y_FIRST,
/* 0x80 */
PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */
PERIPHC_NVDEC, /* 0x698 */
PERIPHC_NVJPG, /* 0x69c */
PERIPHC_NVENC, /* 0x6a0 */
PERIPHC_84h,
PERIPHC_85h,
PERIPHC_86h,
PERIPHC_87h,
/* 0x88 */
PERIPHC_88h,
PERIPHC_89h,
PERIPHC_DMIC3, /* 0x6bc: */
PERIPHC_APE, /* 0x6c0: */
PERIPHC_QSPI, /* 0x6c4: */
PERIPHC_VI_I2C, /* 0x6c8: */
PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */
PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */
/* 0x90 */
PERIPHC_MAUD, /* 0x6d4: */
PERIPHC_TSECB, /* 0x6d8: */
PERIPHC_COUNT,
PERIPHC_NONE = -1,
};
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
#define PERIPH_REG(id) \
(id < PERIPH_ID_VW_FIRST) ? \
((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
/* return 1 if a PLL ID is in range */
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
(id) < PERIPH_ID_COUNT)
#endif /* _TEGRA210_CLOCK_TABLES_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 clock control definitions */
#ifndef _TEGRA210_CLOCK_H_
#define _TEGRA210_CLOCK_H_
#include <asm/arch-tegra/clock.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
/* PLL bits that differ from generic clk_rst.h */
#define PLLC_RESET 30
#define PLLC_IDDQ 27
#define PLLD_ENABLE_CLK 21
#define PLLD_EN_LCKDET 28
int tegra_plle_enable(void);
#endif /* _TEGRA210_CLOCK_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_FLOW_H_
#define _TEGRA210_FLOW_H_
struct flow_ctlr {
u32 halt_cpu_events; /* offset 0x00 */
u32 halt_cop_events; /* offset 0x04 */
u32 cpu_csr; /* offset 0x08 */
u32 cop_csr; /* offset 0x0c */
u32 xrq_events; /* offset 0x10 */
u32 halt_cpu1_events; /* offset 0x14 */
u32 cpu1_csr; /* offset 0x18 */
u32 halt_cpu2_events; /* offset 0x1c */
u32 cpu2_csr; /* offset 0x20 */
u32 halt_cpu3_events; /* offset 0x24 */
u32 cpu3_csr; /* offset 0x28 */
u32 cluster_control; /* offset 0x2c */
u32 halt_cop1_events; /* offset 0x30 */
u32 halt_cop1_csr; /* offset 0x34 */
u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
};
/* HALT_COP_EVENTS_0, 0x04 */
#define EVENT_MSEC (1 << 24)
#define EVENT_USEC (1 << 25)
#define EVENT_JTAG (1 << 28)
#define EVENT_MODE_STOP (2 << 29)
/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
#define ACTIVE_LP (1 << 0)
/* CPUn_CSR_0 */
#define CSR_ENABLE (1 << 0)
#define CSR_IMMEDIATE_WAKE (1 << 3)
#define CSR_WAIT_WFI_SHIFT 8
#endif /* _TEGRA210_FLOW_H_ */

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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 high-level function multiplexing */
#ifndef _TEGRA210_FUNCMUX_H_
#define _TEGRA210_FUNCMUX_H_
#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
FUNCMUX_DEFAULT = 0, /* default config */
/* UART configs */
FUNCMUX_UART1_UART1 = 0,
FUNCMUX_UART4_UART4 = 0,
};
#endif /* _TEGRA210_FUNCMUX_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_GP_PADCTRL_H_
#define _TEGRA210_GP_PADCTRL_H_
#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
u32 reserved0[22]; /* 0x08 - 0x5C: */
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
u32 reserved1; /* 0x8C: */
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
u32 reserved2[3]; /* 0xA4 - 0xAC: */
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
u32 reserved3[9]; /* 0xC8-0xE8: */
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
u32 reserved4[3]; /* 0xF0-0xF8: */
u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
u32 reserved5[3]; /* 0x104-0x10C: */
u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
u32 reserved6; /* 0x128: */
u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
u32 reserved7[2]; /* 0x130 - 0x134: */
u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
u32 reserved8[22]; /* 0x13C - 0x190: */
u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
/* SDMMC1/3 settings from section 27.5 of T114 TRM */
#define SDIOCFG_DRVUP_SLWF 0
#define SDIOCFG_DRVDN_SLWR 0
#define SDIOCFG_DRVUP 0x24
#define SDIOCFG_DRVDN 0x14
#endif /* _TEGRA210_GP_PADCTRL_H_ */

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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_GPIO_H_
#define _TEGRA210_GPIO_H_
/*
* The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
* each with 8 GPIOs.
*/
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
#define TEGRA_GPIO_BANKS 8 /* number of banks */
#include <asm/arch-tegra/gpio.h>
/* GPIO Controller registers for a single bank */
struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];
uint gpio_dir_out[TEGRA_GPIO_PORTS];
uint gpio_out[TEGRA_GPIO_PORTS];
uint gpio_in[TEGRA_GPIO_PORTS];
uint gpio_int_status[TEGRA_GPIO_PORTS];
uint gpio_int_enable[TEGRA_GPIO_PORTS];
uint gpio_int_level[TEGRA_GPIO_PORTS];
uint gpio_int_clear[TEGRA_GPIO_PORTS];
uint gpio_masked_config[TEGRA_GPIO_PORTS];
uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
uint gpio_masked_out[TEGRA_GPIO_PORTS];
uint gpio_masked_in[TEGRA_GPIO_PORTS];
uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
};
struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
enum gpio_pin {
GPIO_PA0 = 0, /* pin 0 */
GPIO_PA1,
GPIO_PA2,
GPIO_PA3,
GPIO_PA4,
GPIO_PA5,
GPIO_PA6,
GPIO_PA7,
GPIO_PB0, /* pin 8 */
GPIO_PB1,
GPIO_PB2,
GPIO_PB3,
GPIO_PB4,
GPIO_PB5,
GPIO_PB6,
GPIO_PB7,
GPIO_PC0, /* pin 16 */
GPIO_PC1,
GPIO_PC2,
GPIO_PC3,
GPIO_PC4,
GPIO_PC5,
GPIO_PC6,
GPIO_PC7,
GPIO_PD0, /* pin 24 */
GPIO_PD1,
GPIO_PD2,
GPIO_PD3,
GPIO_PD4,
GPIO_PD5,
GPIO_PD6,
GPIO_PD7,
GPIO_PE0, /* pin 32 */
GPIO_PE1,
GPIO_PE2,
GPIO_PE3,
GPIO_PE4,
GPIO_PE5,
GPIO_PE6,
GPIO_PE7,
GPIO_PF0, /* pin 40 */
GPIO_PF1,
GPIO_PF2,
GPIO_PF3,
GPIO_PF4,
GPIO_PF5,
GPIO_PF6,
GPIO_PF7,
GPIO_PG0, /* pin 48 */
GPIO_PG1,
GPIO_PG2,
GPIO_PG3,
GPIO_PG4,
GPIO_PG5,
GPIO_PG6,
GPIO_PG7,
GPIO_PH0, /* pin 56 */
GPIO_PH1,
GPIO_PH2,
GPIO_PH3,
GPIO_PH4,
GPIO_PH5,
GPIO_PH6,
GPIO_PH7,
GPIO_PI0, /* pin 64 */
GPIO_PI1,
GPIO_PI2,
GPIO_PI3,
GPIO_PI4,
GPIO_PI5,
GPIO_PI6,
GPIO_PI7,
GPIO_PJ0, /* pin 72 */
GPIO_PJ1,
GPIO_PJ2,
GPIO_PJ3,
GPIO_PJ4,
GPIO_PJ5,
GPIO_PJ6,
GPIO_PJ7,
GPIO_PK0, /* pin 80 */
GPIO_PK1,
GPIO_PK2,
GPIO_PK3,
GPIO_PK4,
GPIO_PK5,
GPIO_PK6,
GPIO_PK7,
GPIO_PL0, /* pin 88 */
GPIO_PL1,
GPIO_PL2,
GPIO_PL3,
GPIO_PL4,
GPIO_PL5,
GPIO_PL6,
GPIO_PL7,
GPIO_PM0, /* pin 96 */
GPIO_PM1,
GPIO_PM2,
GPIO_PM3,
GPIO_PM4,
GPIO_PM5,
GPIO_PM6,
GPIO_PM7,
GPIO_PN0, /* pin 104 */
GPIO_PN1,
GPIO_PN2,
GPIO_PN3,
GPIO_PN4,
GPIO_PN5,
GPIO_PN6,
GPIO_PN7,
GPIO_PO0, /* pin 112 */
GPIO_PO1,
GPIO_PO2,
GPIO_PO3,
GPIO_PO4,
GPIO_PO5,
GPIO_PO6,
GPIO_PO7,
GPIO_PP0, /* pin 120 */
GPIO_PP1,
GPIO_PP2,
GPIO_PP3,
GPIO_PP4,
GPIO_PP5,
GPIO_PP6,
GPIO_PP7,
GPIO_PQ0, /* pin 128 */
GPIO_PQ1,
GPIO_PQ2,
GPIO_PQ3,
GPIO_PQ4,
GPIO_PQ5,
GPIO_PQ6,
GPIO_PQ7,
GPIO_PR0, /* pin 136 */
GPIO_PR1,
GPIO_PR2,
GPIO_PR3,
GPIO_PR4,
GPIO_PR5,
GPIO_PR6,
GPIO_PR7,
GPIO_PS0, /* pin 144 */
GPIO_PS1,
GPIO_PS2,
GPIO_PS3,
GPIO_PS4,
GPIO_PS5,
GPIO_PS6,
GPIO_PS7,
GPIO_PT0, /* pin 152 */
GPIO_PT1,
GPIO_PT2,
GPIO_PT3,
GPIO_PT4,
GPIO_PT5,
GPIO_PT6,
GPIO_PT7,
GPIO_PU0, /* pin 160 */
GPIO_PU1,
GPIO_PU2,
GPIO_PU3,
GPIO_PU4,
GPIO_PU5,
GPIO_PU6,
GPIO_PU7,
GPIO_PV0, /* pin 168 */
GPIO_PV1,
GPIO_PV2,
GPIO_PV3,
GPIO_PV4,
GPIO_PV5,
GPIO_PV6,
GPIO_PV7,
GPIO_PW0, /* pin 176 */
GPIO_PW1,
GPIO_PW2,
GPIO_PW3,
GPIO_PW4,
GPIO_PW5,
GPIO_PW6,
GPIO_PW7,
GPIO_PX0, /* pin 184 */
GPIO_PX1,
GPIO_PX2,
GPIO_PX3,
GPIO_PX4,
GPIO_PX5,
GPIO_PX6,
GPIO_PX7,
GPIO_PY0, /* pin 192 */
GPIO_PY1,
GPIO_PY2,
GPIO_PY3,
GPIO_PY4,
GPIO_PY5,
GPIO_PY6,
GPIO_PY7,
GPIO_PZ0, /* pin 200 */
GPIO_PZ1,
GPIO_PZ2,
GPIO_PZ3,
GPIO_PZ4,
GPIO_PZ5,
GPIO_PZ6,
GPIO_PZ7,
GPIO_PAA0, /* pin 208 */
GPIO_PAA1,
GPIO_PAA2,
GPIO_PAA3,
GPIO_PAA4,
GPIO_PAA5,
GPIO_PAA6,
GPIO_PAA7,
GPIO_PBB0, /* pin 216 */
GPIO_PBB1,
GPIO_PBB2,
GPIO_PBB3,
GPIO_PBB4,
GPIO_PBB5,
GPIO_PBB6,
GPIO_PBB7,
GPIO_PCC0, /* pin 224 */
GPIO_PCC1,
GPIO_PCC2,
GPIO_PCC3,
GPIO_PCC4,
GPIO_PCC5,
GPIO_PCC6,
GPIO_PCC7,
GPIO_PDD0, /* pin 232 */
GPIO_PDD1,
GPIO_PDD2,
GPIO_PDD3,
GPIO_PDD4,
GPIO_PDD5,
GPIO_PDD6,
GPIO_PDD7,
GPIO_PEE0, /* pin 240 */
GPIO_PEE1,
GPIO_PEE2,
GPIO_PEE3,
GPIO_PEE4,
GPIO_PEE5,
GPIO_PEE6,
GPIO_PEE7,
GPIO_PFF0, /* pin 248 */
GPIO_PFF1,
GPIO_PFF2,
GPIO_PFF3,
GPIO_PFF4,
GPIO_PFF5,
GPIO_PFF6,
GPIO_PFF7, /* pin 255 */
};
#endif /* _TEGRA210_GPIO_H_ */

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/*
* Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_MC_H_
#define _TEGRA210_MC_H_
/**
* Defines the memory controller registers we need/care about
*/
struct mc_ctlr {
u32 reserved0[4]; /* offset 0x00 - 0x0C */
u32 mc_smmu_config; /* offset 0x10 */
u32 mc_smmu_tlb_config; /* offset 0x14 */
u32 mc_smmu_ptc_config; /* offset 0x18 */
u32 mc_smmu_ptb_asid; /* offset 0x1C */
u32 mc_smmu_ptb_data; /* offset 0x20 */
u32 reserved1[3]; /* offset 0x24 - 0x2C */
u32 mc_smmu_tlb_flush; /* offset 0x30 */
u32 mc_smmu_ptc_flush; /* offset 0x34 */
u32 reserved2[6]; /* offset 0x38 - 0x4C */
u32 mc_emem_cfg; /* offset 0x50 */
u32 mc_emem_adr_cfg; /* offset 0x54 */
u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
u32 reserved3[4]; /* offset 0x60 - 0x6C */
u32 mc_security_cfg0; /* offset 0x70 */
u32 mc_security_cfg1; /* offset 0x74 */
u32 reserved4[6]; /* offset 0x7C - 0x8C */
u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
u32 reserved5[74]; /* offset 0x100 - 0x224 */
u32 mc_smmu_translation_enable_0; /* offset 0x228 */
u32 mc_smmu_translation_enable_1; /* offset 0x22C */
u32 mc_smmu_translation_enable_2; /* offset 0x230 */
u32 mc_smmu_translation_enable_3; /* offset 0x234 */
u32 mc_smmu_afi_asid; /* offset 0x238 */
u32 mc_smmu_avpc_asid; /* offset 0x23C */
u32 mc_smmu_dc_asid; /* offset 0x240 */
u32 mc_smmu_dcb_asid; /* offset 0x244 */
u32 reserved6[2]; /* offset 0x248 - 0x24C */
u32 mc_smmu_hc_asid; /* offset 0x250 */
u32 mc_smmu_hda_asid; /* offset 0x254 */
u32 mc_smmu_isp2_asid; /* offset 0x258 */
u32 reserved7[2]; /* offset 0x25C - 0x260 */
u32 mc_smmu_msenc_asid; /* offset 0x264 */
u32 mc_smmu_nv_asid; /* offset 0x268 */
u32 mc_smmu_nv2_asid; /* offset 0x26C */
u32 mc_smmu_ppcs_asid; /* offset 0x270 */
u32 mc_smmu_sata_asid; /* offset 0x274 */
u32 reserved8[1]; /* offset 0x278 */
u32 mc_smmu_vde_asid; /* offset 0x27C */
u32 mc_smmu_vi_asid; /* offset 0x280 */
u32 mc_smmu_vic_asid; /* offset 0x284 */
u32 mc_smmu_xusb_host_asid; /* offset 0x288 */
u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */
u32 reserved9[1]; /* offset 0x290 */
u32 mc_smmu_tsec_asid; /* offset 0x294 */
u32 mc_smmu_ppcs1_asid; /* offset 0x298 */
u32 reserved10[235]; /* offset 0x29C - 0x644 */
u32 mc_video_protect_bom; /* offset 0x648 */
u32 mc_video_protect_size_mb; /* offset 0x64c */
u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
};
#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
#endif /* _TEGRA210_MC_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_PMU_H_
#define _TEGRA210_PMU_H_
/* Set core and CPU voltages to nominal levels */
int pmu_set_nominal(void);
#endif /* _TEGRA210_PMU_H_ */

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/*
* Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_POWERGATE_H_
#define _TEGRA210_POWERGATE_H_
#include <asm/arch-tegra/powergate.h>
#endif /* _TEGRA210_POWERGATE_H_ */

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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_SYSCTR_H_
#define _TEGRA210_SYSCTR_H_
struct sysctr_ctlr {
u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
u32 reserved1[4]; /* 0x10 - 0x1C */
u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
u32 reserved2[1002]; /* 0x28 - 0xFCC */
u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
};
#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
#endif /* _TEGRA210_SYSCTR_H_ */

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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_TEGRA_H_
#define _TEGRA210_TEGRA_H_
#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */
#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */
#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
#define NV_PA_SDRAM_BASE 0x80000000
#include <asm/arch-tegra/tegra.h>
#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */
#undef NVBOOTINFOTABLE_BCTSIZE
#undef NVBOOTINFOTABLE_BCTPTR
#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
#define MAX_NUM_CPU 4
#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
#define TEGRA_USB1_BASE 0x7D000000
#endif /* _TEGRA210_TEGRA_H_ */

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if TEGRA210
choice
prompt "Tegra210 board select"
endchoice
config SYS_SOC
default "tegra210"
endif

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#
# (C) Copyright 2013-2015
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
obj-y += xusb-padctl.o

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arch/arm/mach-tegra/tegra210/clock.c Normal file
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arch/arm/mach-tegra/tegra210/funcmux.c Normal file
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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config)
{
int bad_config = config != FUNCMUX_DEFAULT;
switch (id) {
/*
* Add other periph IDs here as needed.
* Note that all pinmux/pads should have already
* been set up in the board pinmux table in
* pinmux-config-<board>.h for all periphs.
* Leave this in for the odd case where a mux
* needs to be changed on-the-fly.
*/
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
}
if (bad_config) {
debug("%s: invalid config %d for periph_id %d", __func__,
config, id);
return -1;
}
return 0;
}

495
arch/arm/mach-tegra/tegra210/xusb-padctl.c Normal file
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/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/xusb-padctl.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
struct tegra_xusb_phy_ops {
int (*prepare)(struct tegra_xusb_phy *phy);
int (*enable)(struct tegra_xusb_phy *phy);
int (*disable)(struct tegra_xusb_phy *phy);
int (*unprepare)(struct tegra_xusb_phy *phy);
};
struct tegra_xusb_phy {
const struct tegra_xusb_phy_ops *ops;
struct tegra_xusb_padctl *padctl;
};
struct tegra_xusb_padctl {
struct fdt_resource regs;
unsigned int enable;
struct tegra_xusb_phy phys[2];
};
static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
unsigned long offset)
{
u32 value = readl(padctl->regs.start + offset);
debug("padctl: %08lx > %08x\n", offset, value);
return value;
}
static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
u32 value, unsigned long offset)
{
debug("padctl: %08lx < %08x\n", offset, value);
writel(value, padctl->regs.start + offset);
}
#define XUSB_PADCTL_ELPG_PROGRAM 0x024
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
{
u32 value;
if (padctl->enable++ > 0)
return 0;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
return 0;
}
static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
{
u32 value;
if (padctl->enable == 0) {
error("unbalanced enable/disable");
return 0;
}
if (--padctl->enable > 0)
return 0;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
return 0;
}
static int phy_prepare(struct tegra_xusb_phy *phy)
{
int err;
err = tegra_xusb_padctl_enable(phy->padctl);
if (err < 0)
return err;
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
return 0;
}
static int phy_unprepare(struct tegra_xusb_phy *phy)
{
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
return tegra_xusb_padctl_disable(phy->padctl);
}
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
#define CLK_RST_XUSBIO_PLL_CFG0 0x51c
#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
static int pcie_phy_enable(struct tegra_xusb_phy *phy)
{
struct tegra_xusb_padctl *padctl = phy->padctl;
unsigned long start;
u32 value;
debug("> %s(phy=%p)\n", __func__, phy);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
udelay(1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
debug(" waiting for calibration\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
debug(" waiting for calibration to stop\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
debug(" waiting for PLL to lock...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
debug(" waiting for register calibration...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
debug(" waiting for register calibration to stop...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
udelay(1);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
debug("< %s()\n", __func__);
return 0;
}
static int pcie_phy_disable(struct tegra_xusb_phy *phy)
{
return 0;
}
static const struct tegra_xusb_phy_ops pcie_phy_ops = {
.prepare = phy_prepare,
.enable = pcie_phy_enable,
.disable = pcie_phy_disable,
.unprepare = phy_unprepare,
};
static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
.phys = {
[0] = {
.ops = &pcie_phy_ops,
},
},
};
static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
const void *fdt, int node)
{
int err;
err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
if (err < 0) {
error("registers not found");
return err;
}
debug("regs: %pa-%pa\n", &padctl->regs.start,
&padctl->regs.end);
return 0;
}
static int process_nodes(const void *fdt, int nodes[], unsigned int count)
{
unsigned int i;
int err;
debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes,
count);
for (i = 0; i < count; i++) {
enum fdt_compat_id id;
if (!fdtdec_get_is_enabled(fdt, nodes[i]))
continue;
id = fdtdec_lookup(fdt, nodes[i]);
switch (id) {
case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL:
break;
default:
error("unsupported compatible: %s",
fdtdec_get_compatible(id));
continue;
}
err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
if (err < 0) {
error("failed to parse DT: %d",
err);
continue;
}
/* deassert XUSB padctl reset */
reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
/* only a single instance is supported */
break;
}
debug("< %s()\n", __func__);
return 0;
}
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
{
struct tegra_xusb_phy *phy = NULL;
switch (type) {
case TEGRA_XUSB_PADCTL_PCIE:
phy = &padctl->phys[0];
phy->padctl = padctl;
break;
}
return phy;
}
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->prepare)
return phy->ops->prepare(phy);
return phy ? -ENOSYS : -EINVAL;
}
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->enable)
return phy->ops->enable(phy);
return phy ? -ENOSYS : -EINVAL;
}
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->disable)
return phy->ops->disable(phy);
return phy ? -ENOSYS : -EINVAL;
}
int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->unprepare)
return phy->ops->unprepare(phy);
return phy ? -ENOSYS : -EINVAL;
}
void tegra_xusb_padctl_init(const void *fdt)
{
int count, nodes[1];
debug("> %s(fdt=%p)\n", __func__, fdt);
count = fdtdec_find_aliases_for_id(fdt, "padctl",
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
nodes, ARRAY_SIZE(nodes));
if (process_nodes(fdt, nodes, count))
return;
count = fdtdec_find_aliases_for_id(fdt, "padctl",
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
nodes, ARRAY_SIZE(nodes));
if (process_nodes(fdt, nodes, count))
return;
debug("< %s()\n", __func__);
}

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include/dt-bindings/clock/tegra210-car.h Normal file
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/*
* This header provides Tegra210-specific constants for binding
* nvidia,tegra210-car.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA210_CLK_ISPB 3
#define TEGRA210_CLK_RTC 4
#define TEGRA210_CLK_TIMER 5
#define TEGRA210_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA210_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA210_CLK_I2S1 11
#define TEGRA210_CLK_I2C1 12
/* 13 */
#define TEGRA210_CLK_SDMMC1 14
#define TEGRA210_CLK_SDMMC4 15
/* 16 */
#define TEGRA210_CLK_PWM 17
#define TEGRA210_CLK_I2S2 18
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA210_CLK_USBD 22
#define TEGRA210_CLK_ISP 23
/* 26 */
/* 25 */
#define TEGRA210_CLK_DISP2 26
#define TEGRA210_CLK_DISP1 27
#define TEGRA210_CLK_HOST1X 28
#define TEGRA210_CLK_VCP 29
#define TEGRA210_CLK_I2S0 30
/* 31 */
#define TEGRA210_CLK_MC 32
/* 33 */
#define TEGRA210_CLK_APBDMA 34
/* 35 */
#define TEGRA210_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA210_CLK_KFUSE 40
#define TEGRA210_CLK_SBC1 41
#define TEGRA210_CLK_NOR 42
/* 43 */
#define TEGRA210_CLK_SBC2 44
/* 45 */
#define TEGRA210_CLK_SBC3 46
#define TEGRA210_CLK_I2C5 47
#define TEGRA210_CLK_DSIA 48
/* 49 */
#define TEGRA210_CLK_MIPI 50
#define TEGRA210_CLK_HDMI 51
#define TEGRA210_CLK_CSI 52
/* 53 */
#define TEGRA210_CLK_I2C2 54
#define TEGRA210_CLK_UARTC 55
#define TEGRA210_CLK_MIPI_CAL 56
#define TEGRA210_CLK_EMC 57
#define TEGRA210_CLK_USB2 58
#define TEGRA210_CLK_USB3 59
/* 60 */
#define TEGRA210_CLK_VDE 61
#define TEGRA210_CLK_BSEA 62
#define TEGRA210_CLK_BSEV 63
/* 64 */
#define TEGRA210_CLK_UARTD 65
/* 66 */
#define TEGRA210_CLK_I2C3 67
#define TEGRA210_CLK_SBC4 68
#define TEGRA210_CLK_SDMMC3 69
#define TEGRA210_CLK_PCIE 70
#define TEGRA210_CLK_OWR 71
#define TEGRA210_CLK_AFI 72
#define TEGRA210_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA210_CLK_LA 76
#define TEGRA210_CLK_TRACE 77
#define TEGRA210_CLK_SOC_THERM 78
#define TEGRA210_CLK_DTV 79
/* 80 */
#define TEGRA210_CLK_I2CSLOW 81
#define TEGRA210_CLK_DSIB 82
#define TEGRA210_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA210_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA210_CLK_MSENC 91
#define TEGRA210_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA210_CLK_MSELECT 99
#define TEGRA210_CLK_TSENSOR 100
#define TEGRA210_CLK_I2S3 101
#define TEGRA210_CLK_I2S4 102
#define TEGRA210_CLK_I2C4 103
#define TEGRA210_CLK_SBC5 104
#define TEGRA210_CLK_SBC6 105
#define TEGRA210_CLK_D_AUDIO 106
#define TEGRA210_CLK_APBIF 107
#define TEGRA210_CLK_DAM0 108
#define TEGRA210_CLK_DAM1 109
#define TEGRA210_CLK_DAM2 110
#define TEGRA210_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA210_CLK_AUDIO0_2X 113
#define TEGRA210_CLK_AUDIO1_2X 114
#define TEGRA210_CLK_AUDIO2_2X 115
#define TEGRA210_CLK_AUDIO3_2X 116
#define TEGRA210_CLK_AUDIO4_2X 117
#define TEGRA210_CLK_SPDIF_2X 118
#define TEGRA210_CLK_ACTMON 119
#define TEGRA210_CLK_EXTERN1 120
#define TEGRA210_CLK_EXTERN2 121
#define TEGRA210_CLK_EXTERN3 122
#define TEGRA210_CLK_SATA_OOB 123
#define TEGRA210_CLK_SATA 124
#define TEGRA210_CLK_HDA 125
/* 126 */
#define TEGRA210_CLK_SE 127
#define TEGRA210_CLK_HDA2HDMI 128
#define TEGRA210_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA210_CLK_CILAB 144
#define TEGRA210_CLK_CILCD 145
#define TEGRA210_CLK_CILE 146
#define TEGRA210_CLK_DSIALP 147
#define TEGRA210_CLK_DSIBLP 148
#define TEGRA210_CLK_ENTROPY 149
#define TEGRA210_CLK_DDS 150
/* 151 */
#define TEGRA210_CLK_DP2 152
#define TEGRA210_CLK_AMX 153
#define TEGRA210_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA210_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
#define TEGRA210_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA210_CLK_VIM2_CLK 171
/* 172 */
/* 173 */
/* 174 */
/* 175 */
#define TEGRA210_CLK_HDMI_AUDIO 176
#define TEGRA210_CLK_CLK72MHZ 177
#define TEGRA210_CLK_VIC03 178
/* 179 */
#define TEGRA210_CLK_ADX1 180
#define TEGRA210_CLK_DPAUX 181
#define TEGRA210_CLK_SOR0 182
/* 183 */
#define TEGRA210_CLK_GPU 184
#define TEGRA210_CLK_AMX1 185
/* 186 */
/* 187 */
/* 188 */
/* 189 */
/* 190 */
/* 191 */
#define TEGRA210_CLK_UARTB 192
#define TEGRA210_CLK_VFIR 193
#define TEGRA210_CLK_SPDIF_IN 194
#define TEGRA210_CLK_SPDIF_OUT 195
#define TEGRA210_CLK_VI 196
#define TEGRA210_CLK_VI_SENSOR 197
#define TEGRA210_CLK_FUSE 198
#define TEGRA210_CLK_FUSE_BURN 199
#define TEGRA210_CLK_CLK_32K 200
#define TEGRA210_CLK_CLK_M 201
#define TEGRA210_CLK_CLK_M_DIV2 202
#define TEGRA210_CLK_CLK_M_DIV4 203
#define TEGRA210_CLK_PLL_REF 204
#define TEGRA210_CLK_PLL_C 205
#define TEGRA210_CLK_PLL_C_OUT1 206
#define TEGRA210_CLK_PLL_C2 207
#define TEGRA210_CLK_PLL_C3 208
#define TEGRA210_CLK_PLL_M 209
#define TEGRA210_CLK_PLL_M_OUT1 210
#define TEGRA210_CLK_PLL_P 211
#define TEGRA210_CLK_PLL_P_OUT1 212
#define TEGRA210_CLK_PLL_P_OUT2 213
#define TEGRA210_CLK_PLL_P_OUT3 214
#define TEGRA210_CLK_PLL_P_OUT4 215
#define TEGRA210_CLK_PLL_A 216
#define TEGRA210_CLK_PLL_A_OUT0 217
#define TEGRA210_CLK_PLL_D 218
#define TEGRA210_CLK_PLL_D_OUT0 219
#define TEGRA210_CLK_PLL_D2 220
#define TEGRA210_CLK_PLL_D2_OUT0 221
#define TEGRA210_CLK_PLL_U 222
#define TEGRA210_CLK_PLL_U_480M 223
#define TEGRA210_CLK_PLL_U_60M 224
#define TEGRA210_CLK_PLL_U_48M 225
#define TEGRA210_CLK_PLL_U_12M 226
/* 227 */
/* 228 */
#define TEGRA210_CLK_PLL_RE_VCO 229
#define TEGRA210_CLK_PLL_RE_OUT 230
#define TEGRA210_CLK_PLL_E 231
#define TEGRA210_CLK_SPDIF_IN_SYNC 232
#define TEGRA210_CLK_I2S0_SYNC 233
#define TEGRA210_CLK_I2S1_SYNC 234
#define TEGRA210_CLK_I2S2_SYNC 235
#define TEGRA210_CLK_I2S3_SYNC 236
#define TEGRA210_CLK_I2S4_SYNC 237
#define TEGRA210_CLK_VIMCLK_SYNC 238
#define TEGRA210_CLK_AUDIO0 239
#define TEGRA210_CLK_AUDIO1 240
#define TEGRA210_CLK_AUDIO2 241
#define TEGRA210_CLK_AUDIO3 242
#define TEGRA210_CLK_AUDIO4 243
#define TEGRA210_CLK_SPDIF 244
#define TEGRA210_CLK_CLK_OUT_1 245
#define TEGRA210_CLK_CLK_OUT_2 246
#define TEGRA210_CLK_CLK_OUT_3 247
#define TEGRA210_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA210_CLK_XUSB_HOST_SRC 252
#define TEGRA210_CLK_XUSB_FALCON_SRC 253
#define TEGRA210_CLK_XUSB_FS_SRC 254
#define TEGRA210_CLK_XUSB_SS_SRC 255
#define TEGRA210_CLK_XUSB_DEV_SRC 256
#define TEGRA210_CLK_XUSB_DEV 257
#define TEGRA210_CLK_XUSB_HS_SRC 258
#define TEGRA210_CLK_SCLK 259
#define TEGRA210_CLK_HCLK 260
#define TEGRA210_CLK_PCLK 261
/* 262 */
/* 263 */
#define TEGRA210_CLK_DFLL_REF 264
#define TEGRA210_CLK_DFLL_SOC 265
#define TEGRA210_CLK_VI_SENSOR2 266
#define TEGRA210_CLK_PLL_P_OUT5 267
#define TEGRA210_CLK_CML0 268
#define TEGRA210_CLK_CML1 269
#define TEGRA210_CLK_PLL_C4 270
#define TEGRA210_CLK_PLL_DP 271
#define TEGRA210_CLK_PLL_E_MUX 272
#define TEGRA210_CLK_PLLD_DSI 273
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA210_CLK_AUDIO0_MUX 300
#define TEGRA210_CLK_AUDIO1_MUX 301
#define TEGRA210_CLK_AUDIO2_MUX 302
#define TEGRA210_CLK_AUDIO3_MUX 303
#define TEGRA210_CLK_AUDIO4_MUX 304
#define TEGRA210_CLK_SPDIF_MUX 305
#define TEGRA210_CLK_CLK_OUT_1_MUX 306
#define TEGRA210_CLK_CLK_OUT_2_MUX 307
#define TEGRA210_CLK_CLK_OUT_3_MUX 308
/* 309 */
/* 310 */
#define TEGRA210_CLK_SOR0_LVDS 311
#define TEGRA210_CLK_XUSB_SS_DIV2 312
#define TEGRA210_CLK_PLL_M_UD 313
#define TEGRA210_CLK_PLL_C_UD 314
#define TEGRA210_CLK_PLL_X 227
#define TEGRA210_CLK_PLL_X_OUT0 228
#define TEGRA210_CLK_CCLK_G 262
#define TEGRA210_CLK_CCLK_LP 263
#define TEGRA210_CLK_CLK_MAX 315
#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */