mirror of
https://github.com/u-boot/u-boot.git
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ppc: Remove MPC8323ERDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
139ff3be23
commit
6c332e2b8c
@ -8,10 +8,6 @@ choice
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prompt "Target select"
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optional
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config TARGET_MPC8323ERDB
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bool "Support MPC8323ERDB"
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select ARCH_MPC832X
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config TARGET_MPC832XEMDS
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bool "Support MPC832XEMDS"
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select ARCH_MPC832X
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@ -252,7 +248,6 @@ endmenu
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config FSL_ELBC
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bool
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source "board/freescale/mpc8323erdb/Kconfig"
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source "board/freescale/mpc832xemds/Kconfig"
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source "board/freescale/mpc8349emds/Kconfig"
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source "board/freescale/mpc837xerdb/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_MPC8323ERDB
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config SYS_BOARD
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default "mpc8323erdb"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8323ERDB"
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endif
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@ -1,6 +0,0 @@
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MPC8323ERDB BOARD
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#M: Michael Barkowski <michael.barkowski@freescale.com>
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S: Orphan (since 2018-05)
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F: board/freescale/mpc8323erdb/
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F: include/configs/MPC8323ERDB.h
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F: configs/MPC8323ERDB_defconfig
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@ -1,6 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y := mpc8323erdb.o
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@ -1,71 +0,0 @@
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Freescale MPC8323ERDB Board
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-----------------------------------------
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1. Memory Map
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The memory map looks like this:
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0x0000_0000 0x03ff_ffff DDR 64M
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0x8000_0000 0x8fff_ffff PCI MEM 256M
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0x9000_0000 0x9fff_ffff PCI_MMIO 256M
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0xe000_0000 0xe00f_ffff IMMR 1M
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0xd000_0000 0xd3ff_ffff PCI IO 64M
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0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M
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2. Compilation
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Assuming you're using BASH (or similar) as your shell:
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export CROSS_COMPILE=your-cross-compiler-prefix-
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make distclean
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make MPC8323ERDB_config
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make
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3. Downloading and Flashing Images
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3.1 Reflash U-Boot Image using U-Boot
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N.b, have an alternate means of programming
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the flash available if the new U-Boot doesn't boot.
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First try a:
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tftpboot $loadaddr $uboot
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to make sure that the TFTP load will succeed before
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an erase goes ahead and wipes out your current firmware.
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Then do a:
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run tftpflash
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which is a shorter version of the manual sequence:
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tftp $loadaddr u-boot.bin
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protect off fe000000 +$filesize
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erase fe000000 +$filesize
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cp.b $loadaddr fe000000 $filesize
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To keep your old U-Boot's environment variables, do a:
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saveenv
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prior to resetting the board.
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3.2 Downloading and Booting Linux Kernel
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Ensure that all networking-related environment variables are set
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properly (including ipaddr, serverip, gatewayip (if needed),
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netmask, ethaddr, eth1addr, rootpath (if using NFS root),
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fdtfile, and bootfile).
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Then, do one of the following, depending on whether you
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want an NFS root or a ramdisk root:
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run nfsboot
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or
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run ramboot
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4 Notes
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The console baudrate for MPC8323ERDB is 115200bps.
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@ -1,233 +0,0 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Michael Barkowski <michael.barkowski@freescale.com>
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* Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <common.h>
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#include <eeprom.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <command.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <u-boot/crc.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#include <asm/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* UCC3 */
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{1, 0, 1, 0, 1}, /* TxD0 */
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{1, 1, 1, 0, 1}, /* TxD1 */
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{1, 2, 1, 0, 1}, /* TxD2 */
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{1, 3, 1, 0, 1}, /* TxD3 */
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{1, 9, 1, 0, 1}, /* TxER */
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{1, 12, 1, 0, 1}, /* TxEN */
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{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
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{1, 4, 2, 0, 1}, /* RxD0 */
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{1, 5, 2, 0, 1}, /* RxD1 */
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{1, 6, 2, 0, 1}, /* RxD2 */
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{1, 7, 2, 0, 1}, /* RxD3 */
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{1, 8, 2, 0, 1}, /* RxER */
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{1, 10, 2, 0, 1}, /* RxDV */
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{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
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{1, 11, 2, 0, 1}, /* COL */
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{1, 13, 2, 0, 1}, /* CRS */
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/* UCC2 */
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{0, 18, 1, 0, 1}, /* TxD0 */
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{0, 19, 1, 0, 1}, /* TxD1 */
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{0, 20, 1, 0, 1}, /* TxD2 */
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{0, 21, 1, 0, 1}, /* TxD3 */
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{0, 27, 1, 0, 1}, /* TxER */
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{0, 30, 1, 0, 1}, /* TxEN */
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{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
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{0, 22, 2, 0, 1}, /* RxD0 */
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{0, 23, 2, 0, 1}, /* RxD1 */
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{0, 24, 2, 0, 1}, /* RxD2 */
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{0, 25, 2, 0, 1}, /* RxD3 */
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{0, 26, 1, 0, 1}, /* RxER */
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{0, 28, 2, 0, 1}, /* Rx_DV */
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{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
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{0, 29, 2, 0, 1}, /* COL */
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{0, 31, 2, 0, 1}, /* CRS */
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{3, 4, 3, 0, 2}, /* MDIO */
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{3, 5, 1, 0, 2}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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int fixed_sdram(void);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -ENXIO;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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/* set total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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__asm__ __volatile__ ("sync");
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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__asm__ __volatile__ ("sync");
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return msize;
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}
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int checkboard(void)
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{
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puts("Board: Freescale MPC8323ERDB\n");
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
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int mac_read_from_eeprom(void)
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{
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uchar buf[28];
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char str[18];
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int i = 0;
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unsigned int crc = 0;
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unsigned char enetvar[32];
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/* Read MAC addresses from EEPROM */
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if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
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printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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} else {
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uint32_t crc_buf;
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memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
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if (crc32(crc, buf, 24) == crc_buf) {
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printf("Reading MAC from EEPROM\n");
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for (i = 0; i < 4; i++) {
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if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
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sprintf(str,
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"%02X:%02X:%02X:%02X:%02X:%02X",
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buf[i * 6], buf[i * 6 + 1],
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buf[i * 6 + 2], buf[i * 6 + 3],
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buf[i * 6 + 4], buf[i * 6 + 5]);
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sprintf((char *)enetvar,
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i ? "eth%daddr" : "ethaddr", i);
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env_set((char *)enetvar, str);
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}
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}
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}
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}
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return 0;
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}
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#endif /* CONFIG_I2C_MAC_OFFSET */
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@ -1,115 +0,0 @@
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CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0xFE000000
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_SYS_CLK_FREQ=66666667
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CONFIG_MPC83xx=y
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CONFIG_HIGH_BATS=y
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CONFIG_TARGET_MPC8323ERDB=y
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CONFIG_CORE_PLL_RATIO_25_1=y
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CONFIG_QUICC_MULT_FACTOR_3=y
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CONFIG_PCI_HOST_MODE_ENABLE=y
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CONFIG_PCI_INT_ARBITER1_ENABLE=y
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CONFIG_BOOT_MEMORY_SPACE_LOW=y
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CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
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CONFIG_BAT0=y
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CONFIG_BAT0_NAME="SDRAM"
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CONFIG_BAT0_BASE=0x00000000
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CONFIG_BAT0_LENGTH_256_MBYTES=y
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CONFIG_BAT0_ACCESS_RW=y
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CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_USER_MODE_VALID=y
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CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT1=y
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CONFIG_BAT1_NAME="IMMR"
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CONFIG_BAT1_BASE=0xE0000000
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CONFIG_BAT1_LENGTH_4_MBYTES=y
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CONFIG_BAT1_ACCESS_RW=y
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CONFIG_BAT1_ICACHE_INHIBITED=y
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CONFIG_BAT1_ICACHE_GUARDED=y
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CONFIG_BAT1_DCACHE_INHIBITED=y
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CONFIG_BAT1_DCACHE_GUARDED=y
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CONFIG_BAT1_USER_MODE_VALID=y
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CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT2=y
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CONFIG_BAT2_NAME="FLASH"
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CONFIG_BAT2_BASE=0xFE000000
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CONFIG_BAT2_LENGTH_32_MBYTES=y
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CONFIG_BAT2_ACCESS_RW=y
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CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT2_DCACHE_INHIBITED=y
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CONFIG_BAT2_DCACHE_GUARDED=y
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CONFIG_BAT2_USER_MODE_VALID=y
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CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT4=y
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CONFIG_BAT4_NAME="STACK_IN_DCACHE"
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CONFIG_BAT4_BASE=0xE6000000
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CONFIG_BAT4_ACCESS_RW=y
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CONFIG_BAT4_USER_MODE_VALID=y
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CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT5=y
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CONFIG_BAT5_NAME="PCI_MEM_PHYS"
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CONFIG_BAT5_BASE=0x80000000
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CONFIG_BAT5_LENGTH_256_MBYTES=y
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CONFIG_BAT5_ACCESS_RW=y
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CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT5_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT5_USER_MODE_VALID=y
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CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT6=y
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CONFIG_BAT6_NAME="PCI1_MMIO_PHYS"
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CONFIG_BAT6_BASE=0x90000000
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CONFIG_BAT6_LENGTH_256_MBYTES=y
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CONFIG_BAT6_ACCESS_RW=y
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CONFIG_BAT6_ICACHE_INHIBITED=y
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CONFIG_BAT6_ICACHE_GUARDED=y
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CONFIG_BAT6_DCACHE_INHIBITED=y
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CONFIG_BAT6_DCACHE_GUARDED=y
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CONFIG_BAT6_USER_MODE_VALID=y
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CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
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CONFIG_LBLAW0=y
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CONFIG_LBLAW0_BASE=0xFE000000
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CONFIG_LBLAW0_NAME="FLASH"
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CONFIG_LBLAW0_LENGTH_32_MBYTES=y
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CONFIG_ELBC_BR0_OR0=y
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CONFIG_BR0_OR0_NAME="FLASH"
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CONFIG_BR0_OR0_BASE=0xFE000000
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CONFIG_BR0_PORTSIZE_16BIT=y
|
||||
CONFIG_OR0_AM_16_MBYTES=y
|
||||
CONFIG_OR0_XAM_SET=y
|
||||
CONFIG_OR0_SCY_15=y
|
||||
CONFIG_OR0_CSNT_EARLIER=y
|
||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
||||
CONFIG_OR0_XACS_EXTENDED=y
|
||||
CONFIG_OR0_TRLX_RELAXED=y
|
||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
||||
CONFIG_OR0_EAD_EXTRA=y
|
||||
CONFIG_HID0_FINAL_EMCP=y
|
||||
CONFIG_HID0_FINAL_ICE=y
|
||||
CONFIG_HID2_HBE=y
|
||||
CONFIG_ACR_PIPE_DEP_4=y
|
||||
CONFIG_ACR_RPTCNT_4=y
|
||||
CONFIG_SPCR_OPT_SPEC_READ=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=6
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_ADDR=0xFE080000
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,309 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1 /* E300 family */
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CONFIG_SYS_SICRL 0x00000000
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
|
||||
#undef CONFIG_SPD_EEPROM
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
/* Determine DDR configuration from I2C interface
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
|
||||
#else
|
||||
/* Manually set up DDR parameters
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_SIZE 64 /* MB */
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
|
||||
| CSCONFIG_ROW_BIT_13 \
|
||||
| CSCONFIG_COL_BIT_9)
|
||||
/* 0x80010101 */
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
|
||||
/* 0x00220802 */
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
|
||||
| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (3 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT))
|
||||
/* 0x26253222 */
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
|
||||
| (31 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
|
||||
/* 0x1f9048c7 */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
/* 0x02000000 */
|
||||
#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
|
||||
| (0x0232 << SDRAM_MODE_SD_SHIFT))
|
||||
/* 0x44480232 */
|
||||
#define CONFIG_SYS_DDR_MODE2 0x8000c000
|
||||
#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
|
||||
| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
|
||||
/* 0x03200064 */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE)
|
||||
/* 0x43080000 */
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
|
||||
|
||||
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Config on-board EEPROM
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCI_SKIP_HOST_BRIDGE
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#define CONFIG_ETHPRIME "UEC0"
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* ETH3 */
|
||||
|
||||
#ifdef CONFIG_UEC_ETH1
|
||||
#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
|
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
|
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 4
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
||||
#endif
|
||||
|
||||
#define CONFIG_UEC_ETH2 /* ETH4 */
|
||||
|
||||
#ifdef CONFIG_UEC_ETH2
|
||||
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
|
||||
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
|
||||
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
|
||||
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC2_PHY_ADDR 0
|
||||
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
|
||||
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
/* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if (CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
||||
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
||||
|
||||
/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
|
||||
* (see CONFIG_SYS_I2C_EEPROM) */
|
||||
/* MAC address offset in I2C EEPROM */
|
||||
#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
|
||||
|
||||
#define CONFIG_NETDEV "eth1"
|
||||
|
||||
#define CONFIG_HOSTNAME "mpc8323erdb"
|
||||
#define CONFIG_ROOTPATH "/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
/* U-Boot image on TFTP server */
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin"
|
||||
#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
|
||||
#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 800000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" CONFIG_NETDEV "\0" \
|
||||
"uboot=" CONFIG_UBOOTPATH "\0" \
|
||||
"tftpflash=tftp $loadaddr $uboot;" \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize\0" \
|
||||
"fdtaddr=780000\0" \
|
||||
"fdtfile=" CONFIG_FDTFILE "\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
|
||||
"$netdev:off "\
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user