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arm: socfpga: Add onchip RAM size macro

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Add OCRAM size macro for Gen5 and Arria 10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan 2020-03-06 16:55:18 +08:00 committed by Marek Vasut
parent 93330d4ce4
commit 69f9c8bab8
2 changed files with 4 additions and 0 deletions
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2
arch/arm/mach-socfpga/include/mach/base_addr_a10.h
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@ -47,4 +47,6 @@
#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000
#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */

2
arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
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@ -59,4 +59,6 @@
#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000
#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */