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ddr: marvell: a38x: fix write leveling suplementary algo

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commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
This commit is contained in:
Moti Buskila 2021-02-19 17:11:09 +01:00 committed by Stefan Roese
parent 2ca5b190c3
commit 69f084f5c6
1 changed files with 4 additions and 1 deletions
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5
drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
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@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
}
for (pattern = 0; pattern < PATTERN_LAST; pattern++)
for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
if (pattern == PATTERN_TEST)
continue;
ddr3_tip_load_pattern_to_mem(dev_num, pattern);
}
return MV_OK;
}