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mmc: mtk-sd: Adjust the mmc tuning flow
1.Support cmd response and data tuning together. 2.Support hs400 cmd responese tuning. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
This commit is contained in:
mingming lee
Tom Rini
parent
9072400775
commit
69373bd44a
@ -125,6 +125,9 @@
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#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
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#define MSDC_PAD_TUNE_DATWRDLY_S 0
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#define PAD_CMD_TUNE_RX_DLY3 0x3E
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#define PAD_CMD_TUNE_RX_DLY3_S 1
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/* EMMC50_CFG0 */
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#define EMMC50_CFG_CFCSTS_SEL BIT(4)
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@ -209,7 +212,8 @@ struct mtk_sd_regs {
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u32 eco_ver;
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u32 reserved6[27];
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u32 pad_ds_tune;
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u32 reserved7[31];
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u32 pad_cmd_tune;
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u32 reserved7[30];
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u32 emmc50_cfg0;
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u32 reserved8[7];
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u32 sdc_fifo_cfg;
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@ -240,6 +244,7 @@ struct msdc_plat {
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struct msdc_tune_para {
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u32 iocon;
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u32 pad_tune;
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u32 pad_cmd_tune;
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};
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struct msdc_host {
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@ -364,6 +369,8 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
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case MMC_CMD_WRITE_SINGLE_BLOCK:
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case MMC_CMD_READ_SINGLE_BLOCK:
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case SD_CMD_APP_SEND_SCR:
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case MMC_CMD_SEND_TUNING_BLOCK:
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case MMC_CMD_SEND_TUNING_BLOCK_HS200:
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dtype = 1;
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break;
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case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
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@ -469,6 +476,14 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
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if (!msdc_cmd_is_ready(host))
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return -EIO;
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if ((readl(&host->base->msdc_fifocs) &
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MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
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(readl(&host->base->msdc_fifocs) &
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MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
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pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
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msdc_reset_hw(host);
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}
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msdc_fifo_clr(host);
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host->last_resp_type = cmd->resp_type;
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@ -652,14 +667,22 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct msdc_host *host = dev_get_priv(dev);
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int ret;
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int cmd_ret, data_ret;
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ret = msdc_start_command(host, cmd, data);
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if (ret)
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return ret;
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cmd_ret = msdc_start_command(host, cmd, data);
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if (cmd_ret &&
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!(cmd_ret == -EIO &&
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(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
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cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
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return cmd_ret;
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if (data)
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return msdc_start_data(host, data);
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if (data) {
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data_ret = msdc_start_data(host, data);
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if (cmd_ret)
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return cmd_ret;
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else
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return data_ret;
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}
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return 0;
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}
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@ -941,6 +964,56 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
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return delay_phase;
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}
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static int hs400_tune_response(struct udevice *dev, u32 opcode)
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{
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struct msdc_plat *plat = dev_get_platdata(dev);
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struct msdc_host *host = dev_get_priv(dev);
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struct mmc *mmc = &plat->mmc;
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u32 cmd_delay = 0;
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struct msdc_delay_phase final_cmd_delay = { 0, };
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u8 final_delay;
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void __iomem *tune_reg = &host->base->pad_cmd_tune;
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int cmd_err;
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int i, j;
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setbits_le32(&host->base->pad_cmd_tune, BIT(0));
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if (mmc->selected_mode == MMC_HS_200 ||
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mmc->selected_mode == UHS_SDR104)
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
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host->hs200_cmd_int_delay <<
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MSDC_PAD_TUNE_CMDRRDLY_S);
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if (host->r_smpl)
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
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else
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
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i << PAD_CMD_TUNE_RX_DLY3_S);
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for (j = 0; j < 3; j++) {
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mmc_send_tuning(mmc, opcode, &cmd_err);
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if (!cmd_err) {
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cmd_delay |= (1 << i);
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} else {
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cmd_delay &= ~(1 << i);
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break;
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}
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}
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}
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final_cmd_delay = get_best_delay(host, cmd_delay);
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clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
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final_cmd_delay.final_phase <<
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PAD_CMD_TUNE_RX_DLY3_S);
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final_delay = final_cmd_delay.final_phase;
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dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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}
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static int msdc_tune_response(struct udevice *dev, u32 opcode)
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{
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struct msdc_plat *plat = dev_get_platdata(dev);
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@ -1132,34 +1205,138 @@ skip_fall:
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return final_delay == 0xff ? -EIO : 0;
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}
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/*
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* MSDC IP which supports data tune + async fifo can do CMD/DAT tune
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* together, which can save the tuning time.
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*/
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static int msdc_tune_together(struct udevice *dev, u32 opcode)
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{
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struct msdc_plat *plat = dev_get_platdata(dev);
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struct msdc_host *host = dev_get_priv(dev);
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struct mmc *mmc = &plat->mmc;
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
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u8 final_delay, final_maxlen;
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void __iomem *tune_reg = &host->base->pad_tune;
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int i, ret;
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if (host->dev_comp->pad_tune0)
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tune_reg = &host->base->pad_tune0;
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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i << MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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i << MSDC_PAD_TUNE_DATRRDLY_S);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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}
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final_rise_delay = get_best_delay(host, rise_delay);
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if (final_rise_delay.maxlen >= 12 ||
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(final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
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goto skip_fall;
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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i << MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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i << MSDC_PAD_TUNE_DATRRDLY_S);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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}
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final_fall_delay = get_best_delay(host, fall_delay);
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skip_fall:
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final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
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if (final_maxlen == final_rise_delay.maxlen) {
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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final_rise_delay.final_phase <<
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MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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final_rise_delay.final_phase <<
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MSDC_PAD_TUNE_DATRRDLY_S);
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final_delay = final_rise_delay.final_phase;
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} else {
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
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setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
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final_fall_delay.final_phase <<
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MSDC_PAD_TUNE_CMDRDLY_S);
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clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
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final_fall_delay.final_phase <<
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MSDC_PAD_TUNE_DATRRDLY_S);
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final_delay = final_fall_delay.final_phase;
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}
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dev_err(dev, "Final pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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}
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static int msdc_execute_tuning(struct udevice *dev, uint opcode)
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{
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struct msdc_plat *plat = dev_get_platdata(dev);
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struct msdc_host *host = dev_get_priv(dev);
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struct mmc *mmc = &plat->mmc;
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int ret;
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int ret = 0;
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if (mmc->selected_mode == MMC_HS_400) {
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writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
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/* for hs400 mode it must be set to 0 */
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clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
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host->hs400_mode = true;
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if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
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ret = msdc_tune_together(dev, opcode);
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if (ret == -EIO) {
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dev_err(dev, "Tune fail!\n");
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return ret;
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}
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if (mmc->selected_mode == MMC_HS_400) {
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clrbits_le32(&host->base->msdc_iocon,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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clrsetbits_le32(&host->base->pad_tune,
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MSDC_PAD_TUNE_DATRRDLY_M, 0);
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writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
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/* for hs400 mode it must be set to 0 */
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clrbits_le32(&host->base->patch_bit2,
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MSDC_PB2_CFGCRCSTS);
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host->hs400_mode = true;
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}
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goto tune_done;
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}
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ret = msdc_tune_response(dev, opcode);
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if (mmc->selected_mode == MMC_HS_400)
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ret = hs400_tune_response(dev, opcode);
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else
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ret = msdc_tune_response(dev, opcode);
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if (ret == -EIO) {
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dev_err(dev, "Tune response fail!\n");
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return ret;
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}
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if (!host->hs400_mode) {
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if (mmc->selected_mode != MMC_HS_400) {
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ret = msdc_tune_data(dev, opcode);
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if (ret == -EIO)
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if (ret == -EIO) {
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dev_err(dev, "Tune data fail!\n");
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return ret;
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}
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}
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tune_done:
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host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
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host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
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host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
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return ret;
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}
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