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arm: da830: moved pinmux configurations to the arch tree
Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
This commit is contained in:
Vishwanathrao Badarkhe, Manish
Tom Rini
parent
cf32b53b97
commit
68cd4a4c9f
@ -33,6 +33,7 @@ COBJS-$(CONFIG_SOC_DM355) += dm355.o
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COBJS-$(CONFIG_SOC_DM365) += dm365.o
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COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
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COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
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COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o
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COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o
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COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
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151
arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
Normal file
151
arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
Normal file
@ -0,0 +1,151 @@
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/*
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* Pinmux configurations for the DA830 SoCs
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <asm/arch/davinci_misc.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/pinmux_defs.h>
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/* SPI0 pin muxer settings */
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const struct pinmux_config spi0_pins_base[] = {
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{ pinmux(7), 1, 3 }, /* SPI0_SOMI */
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{ pinmux(7), 1, 4 }, /* SPI0_SIMO */
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{ pinmux(7), 1, 6 } /* SPI0_CLK */
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};
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const struct pinmux_config spi0_pins_scs0[] = {
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{ pinmux(7), 1, 7 } /* SPI0_SCS[0] */
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};
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const struct pinmux_config spi0_pins_ena[] = {
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{ pinmux(7), 1, 5 } /* SPI0_ENA */
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};
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/* NAND pin muxer settings */
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const struct pinmux_config emifa_pins_cs0[] = {
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{ pinmux(18), 1, 2 } /* EMA_CS[0] */
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};
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const struct pinmux_config emifa_pins_cs2[] = {
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{ pinmux(18), 1, 3 } /* EMA_CS[2] */
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};
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const struct pinmux_config emifa_pins_cs3[] = {
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{ pinmux(18), 1, 4 } /* EMA_CS[3] */
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};
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#ifdef CONFIG_USE_NAND
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const struct pinmux_config emifa_pins[] = {
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{ pinmux(13), 1, 6 }, /* EMA_D[0] */
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{ pinmux(13), 1, 7 }, /* EMA_D[1] */
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{ pinmux(14), 1, 0 }, /* EMA_D[2] */
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{ pinmux(14), 1, 1 }, /* EMA_D[3] */
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{ pinmux(14), 1, 2 }, /* EMA_D[4] */
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{ pinmux(14), 1, 3 }, /* EMA_D[5] */
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{ pinmux(14), 1, 4 }, /* EMA_D[6] */
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{ pinmux(14), 1, 5 }, /* EMA_D[7] */
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{ pinmux(14), 1, 6 }, /* EMA_D[8] */
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{ pinmux(14), 1, 7 }, /* EMA_D[9] */
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{ pinmux(15), 1, 0 }, /* EMA_D[10] */
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{ pinmux(15), 1, 1 }, /* EMA_D[11] */
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{ pinmux(15), 1, 2 }, /* EMA_D[12] */
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{ pinmux(15), 1, 3 }, /* EMA_D[13] */
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{ pinmux(15), 1, 4 }, /* EMA_D[14] */
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{ pinmux(15), 1, 5 }, /* EMA_D[15] */
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{ pinmux(15), 1, 6 }, /* EMA_A[0] */
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{ pinmux(15), 1, 7 }, /* EMA_A[1] */
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{ pinmux(16), 1, 0 }, /* EMA_A[2] */
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{ pinmux(16), 1, 1 }, /* EMA_A[3] */
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{ pinmux(16), 1, 2 }, /* EMA_A[4] */
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{ pinmux(16), 1, 3 }, /* EMA_A[5] */
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{ pinmux(16), 1, 4 }, /* EMA_A[6] */
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{ pinmux(16), 1, 5 }, /* EMA_A[7] */
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{ pinmux(16), 1, 6 }, /* EMA_A[8] */
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{ pinmux(16), 1, 7 }, /* EMA_A[9] */
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{ pinmux(17), 1, 0 }, /* EMA_A[10] */
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{ pinmux(17), 1, 1 }, /* EMA_A[11] */
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{ pinmux(17), 1, 2 }, /* EMA_A[12] */
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{ pinmux(17), 1, 3 }, /* EMA_BA[1] */
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{ pinmux(17), 1, 4 }, /* EMA_BA[0] */
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{ pinmux(17), 1, 5 }, /* EMA_CLK */
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{ pinmux(17), 1, 6 }, /* EMA_SDCKE */
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{ pinmux(17), 1, 7 }, /* EMA_CAS */
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{ pinmux(18), 1, 0 }, /* EMA_CAS */
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{ pinmux(18), 1, 1 }, /* EMA_WE */
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{ pinmux(18), 1, 5 }, /* EMA_OE */
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{ pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */
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{ pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */
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{ pinmux(10), 1, 0 } /* Tristate */
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};
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#endif
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/* EMAC PHY interface pins */
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const struct pinmux_config emac_pins_rmii[] = {
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{ pinmux(10), 2, 1 }, /* RMII_TXD[0] */
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{ pinmux(10), 2, 2 }, /* RMII_TXD[1] */
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{ pinmux(10), 2, 3 }, /* RMII_TXEN */
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{ pinmux(10), 2, 4 }, /* RMII_CRS_DV */
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{ pinmux(10), 2, 5 }, /* RMII_RXD[0] */
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{ pinmux(10), 2, 6 }, /* RMII_RXD[1] */
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{ pinmux(10), 2, 7 } /* RMII_RXER */
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};
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const struct pinmux_config emac_pins_mdio[] = {
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{ pinmux(11), 2, 0 }, /* MDIO_CLK */
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{ pinmux(11), 2, 1 } /* MDIO_D */
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};
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const struct pinmux_config emac_pins_rmii_clk_source[] = {
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{ pinmux(9), 0, 5 } /* ref.clk from external source */
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};
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/* UART2 pin muxer settings */
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const struct pinmux_config uart2_pins_txrx[] = {
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{ pinmux(8), 2, 7 }, /* UART2_RXD */
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{ pinmux(9), 2, 0 } /* UART2_TXD */
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};
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/* I2C0 pin muxer settings */
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const struct pinmux_config i2c0_pins[] = {
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{ pinmux(8), 2, 3 }, /* I2C0_SDA */
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{ pinmux(8), 2, 4 } /* I2C0_SCL */
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};
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/* USB0_DRVVBUS pin muxer settings */
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const struct pinmux_config usb_pins[] = {
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{ pinmux(9), 1, 1 } /* USB0_DRVVBUS */
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};
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#ifdef CONFIG_DAVINCI_MMC
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/* MMC0 pin muxer settings */
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const struct pinmux_config mmc0_pins_8bit[] = {
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{ pinmux(15), 2, 7 }, /* MMCSD0_CLK */
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{ pinmux(16), 2, 0 }, /* MMCSD0_CMD */
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{ pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
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{ pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
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{ pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
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{ pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
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{ pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
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{ pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
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{ pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
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{ pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */
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/* DA830 supports 8-bit mode */
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};
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#endif
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@ -22,8 +22,14 @@
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#define __ASM_ARCH_PINMUX_DEFS_H
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#include <asm/arch/davinci_misc.h>
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#include <config.h>
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/* SPI pin muxer settings */
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/* SPI0 pin muxer settings */
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extern const struct pinmux_config spi0_pins_base[3];
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extern const struct pinmux_config spi0_pins_scs0[1];
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extern const struct pinmux_config spi0_pins_ena[1];
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/* SPI1 pin muxer settings */
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extern const struct pinmux_config spi1_pins_base[3];
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extern const struct pinmux_config spi1_pins_scs0[1];
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@ -35,6 +41,7 @@ extern const struct pinmux_config uart2_pins_rtscts[2];
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/* EMAC pin muxer settings*/
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extern const struct pinmux_config emac_pins_rmii[7];
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extern const struct pinmux_config emac_pins_rmii_clk_source[1];
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extern const struct pinmux_config emac_pins_mii[15];
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extern const struct pinmux_config emac_pins_mdio[2];
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@ -43,13 +50,19 @@ extern const struct pinmux_config i2c0_pins[2];
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extern const struct pinmux_config i2c1_pins[2];
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/* EMIFA pin muxer settings */
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extern const struct pinmux_config emifa_pins[40];
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extern const struct pinmux_config emifa_pins_cs0[1];
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extern const struct pinmux_config emifa_pins_cs2[1];
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extern const struct pinmux_config emifa_pins_cs3[1];
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extern const struct pinmux_config emifa_pins_cs4[1];
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extern const struct pinmux_config emifa_pins_nand[12];
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extern const struct pinmux_config emifa_pins_nor[43];
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/* USB pin mux setting */
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extern const struct pinmux_config usb_pins[1];
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/* MMC pin muxer settings */
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extern const struct pinmux_config mmc0_pins_8bit[10];
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extern const struct pinmux_config mmc0_pins[6];
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#endif
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@ -39,6 +39,7 @@
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#include <asm/arch/hardware.h>
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#include <asm/arch/emif_defs.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/arch/pinmux_defs.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/arch/nand_defs.h>
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@ -51,148 +52,30 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* SPI0 pin muxer settings */
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static const struct pinmux_config spi0_pins[] = {
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{ pinmux(7), 1, 3 },
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{ pinmux(7), 1, 4 },
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{ pinmux(7), 1, 5 },
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{ pinmux(7), 1, 6 },
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{ pinmux(7), 1, 7 }
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};
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/* EMIF-A bus pins for 8-bit NAND support on CS3 */
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static const struct pinmux_config emifa_nand_pins[] = {
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{ pinmux(13), 1, 6 },
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{ pinmux(13), 1, 7 },
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{ pinmux(14), 1, 0 },
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{ pinmux(14), 1, 1 },
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{ pinmux(14), 1, 2 },
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{ pinmux(14), 1, 3 },
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{ pinmux(14), 1, 4 },
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{ pinmux(14), 1, 5 },
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{ pinmux(15), 1, 7 },
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{ pinmux(16), 1, 0 },
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{ pinmux(18), 1, 1 },
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{ pinmux(18), 1, 4 },
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{ pinmux(18), 1, 5 },
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};
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/* EMAC PHY interface pins */
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static const struct pinmux_config emac_pins[] = {
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{ pinmux(9), 0, 5 },
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{ pinmux(10), 2, 1 },
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{ pinmux(10), 2, 2 },
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{ pinmux(10), 2, 3 },
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{ pinmux(10), 2, 4 },
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{ pinmux(10), 2, 5 },
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{ pinmux(10), 2, 6 },
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{ pinmux(10), 2, 7 },
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{ pinmux(11), 2, 0 },
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{ pinmux(11), 2, 1 },
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};
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/* UART pin muxer settings */
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static const struct pinmux_config uart_pins[] = {
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{ pinmux(8), 2, 7 },
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{ pinmux(9), 2, 0 }
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};
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/* I2C pin muxer settings */
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static const struct pinmux_config i2c_pins[] = {
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{ pinmux(8), 2, 3 },
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{ pinmux(8), 2, 4 }
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};
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#ifdef CONFIG_USE_NAND
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/* NAND pin muxer settings */
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const struct pinmux_config aemif_pins[] = {
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{ pinmux(13), 1, 6 },
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{ pinmux(13), 1, 7 },
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{ pinmux(14), 1, 0 },
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{ pinmux(14), 1, 1 },
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{ pinmux(14), 1, 2 },
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{ pinmux(14), 1, 3 },
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{ pinmux(14), 1, 4 },
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{ pinmux(14), 1, 5 },
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{ pinmux(14), 1, 6 },
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{ pinmux(14), 1, 7 },
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{ pinmux(15), 1, 0 },
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{ pinmux(15), 1, 1 },
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{ pinmux(15), 1, 2 },
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{ pinmux(15), 1, 3 },
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{ pinmux(15), 1, 4 },
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{ pinmux(15), 1, 5 },
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{ pinmux(15), 1, 6 },
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{ pinmux(15), 1, 7 },
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{ pinmux(16), 1, 0 },
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{ pinmux(16), 1, 1 },
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{ pinmux(16), 1, 2 },
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{ pinmux(16), 1, 3 },
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{ pinmux(16), 1, 4 },
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{ pinmux(16), 1, 5 },
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{ pinmux(16), 1, 6 },
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{ pinmux(16), 1, 7 },
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{ pinmux(17), 1, 0 },
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{ pinmux(17), 1, 1 },
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{ pinmux(17), 1, 2 },
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{ pinmux(17), 1, 3 },
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{ pinmux(17), 1, 4 },
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{ pinmux(17), 1, 5 },
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{ pinmux(17), 1, 6 },
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{ pinmux(17), 1, 7 },
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{ pinmux(18), 1, 0 },
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{ pinmux(18), 1, 1 },
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{ pinmux(18), 1, 2 },
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{ pinmux(18), 1, 3 },
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{ pinmux(18), 1, 4 },
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{ pinmux(18), 1, 5 },
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{ pinmux(18), 1, 6 },
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{ pinmux(18), 1, 7 },
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{ pinmux(10), 1, 0 }
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};
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#endif
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/* USB0_DRVVBUS pin muxer settings */
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static const struct pinmux_config usb_pins[] = {
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{ pinmux(9), 1, 1 }
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};
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#ifdef CONFIG_DAVINCI_MMC
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/* MMC0 pin muxer settings */
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const struct pinmux_config mmc0_pins[] = {
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{ pinmux(15), 2, 7 }, /* MMCSD0_CLK */
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{ pinmux(16), 2, 0 }, /* MMCSD0_CMD */
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{ pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
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{ pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
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{ pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
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{ pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
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{ pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
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{ pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
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{ pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
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{ pinmux(14), 2, 5 }, /* MMCSD0_DAT_7 */
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/* DA830 supports 8-bit mode */
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};
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#endif
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static const struct pinmux_resource pinmuxes[] = {
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#ifdef CONFIG_SPI_FLASH
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PINMUX_ITEM(spi0_pins),
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PINMUX_ITEM(spi0_pins_base),
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PINMUX_ITEM(spi0_pins_scs0),
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PINMUX_ITEM(spi0_pins_ena),
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#endif
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PINMUX_ITEM(uart_pins),
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PINMUX_ITEM(i2c_pins),
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PINMUX_ITEM(uart2_pins_txrx),
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PINMUX_ITEM(i2c0_pins),
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#ifdef CONFIG_USB_DA8XX
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PINMUX_ITEM(usb_pins),
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#endif
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#ifdef CONFIG_USE_NAND
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PINMUX_ITEM(emifa_nand_pins),
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PINMUX_ITEM(aemif_pins),
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PINMUX_ITEM(emifa_pins),
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PINMUX_ITEM(emifa_pins_cs0),
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PINMUX_ITEM(emifa_pins_cs2),
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PINMUX_ITEM(emifa_pins_cs3),
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#endif
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#if defined(CONFIG_DRIVER_TI_EMAC)
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PINMUX_ITEM(emac_pins),
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PINMUX_ITEM(emac_pins_rmii),
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PINMUX_ITEM(emac_pins_mdio),
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PINMUX_ITEM(emac_pins_rmii_clk_source),
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#endif
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#ifdef CONFIG_DAVINCI_MMC
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PINMUX_ITEM(mmc0_pins),
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PINMUX_ITEM(mmc0_pins_8bit)
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#endif
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};
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@ -36,6 +36,7 @@
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#define CONFIG_MACH_DAVINCI_DA830_EVM
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA830 /* TI DA830 SoC */
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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