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ARM: mxs: Added application UART driver
The driver makes it possible to use an application UART as the U-Boot output console for Freescale i.MX23/i.MX28 devices. Signed-off-by: Andreas Wass <andreas.wass@dalelven.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Andreas Wass
Stefano Babic
parent
8907c2c504
commit
661edaafd4
220
arch/arm/include/asm/arch-mxs/regs-uartapp.h
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220
arch/arm/include/asm/arch-mxs/regs-uartapp.h
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@ -0,0 +1,220 @@
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/*
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* Freescale MXS UARTAPP Register Definitions
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*
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* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_ARM___MXS_UARTAPP_H
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#define __ARCH_ARM___MXS_UARTAPP_H
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#include <asm/imx-common/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_uartapp_regs {
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mxs_reg_32(hw_uartapp_ctrl0)
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mxs_reg_32(hw_uartapp_ctrl1)
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mxs_reg_32(hw_uartapp_ctrl2)
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mxs_reg_32(hw_uartapp_linectrl)
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mxs_reg_32(hw_uartapp_linectrl2)
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mxs_reg_32(hw_uartapp_intr)
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mxs_reg_32(hw_uartapp_data)
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mxs_reg_32(hw_uartapp_stat)
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mxs_reg_32(hw_uartapp_debug)
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mxs_reg_32(hw_uartapp_version)
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mxs_reg_32(hw_uartapp_autobaud)
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};
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#endif
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#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
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#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
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#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
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#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
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#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
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#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
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#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
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#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
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#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
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#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
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#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
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#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
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#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
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#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
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#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
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#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
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#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
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#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
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#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
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#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
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#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
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#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
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#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
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#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
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#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
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#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
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#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
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#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
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#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
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#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
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#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
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#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
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#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
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#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
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#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
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#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
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#define UARTAPP_CTRL2_UARTEN_MASK 0x01
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#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
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#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
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#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
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#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
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#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
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#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
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#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
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#define UARTAPP_LINECTRL_WLEN_OFFSET 5
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#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
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#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
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#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
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#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
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#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
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#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
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#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
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#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
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#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
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#define UARTAPP_LINECTRL_BRK_MASK 1
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#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
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#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
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#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
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#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
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#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
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#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
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#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
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#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
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#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
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#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
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#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
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#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
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#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
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#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
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#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
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#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
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#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
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#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
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#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
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#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
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#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
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#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
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#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
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#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
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#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
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#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
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#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
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#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
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#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
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#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
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#define UARTAPP_INTR_OEIS_MASK (1 << 10)
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#define UARTAPP_INTR_BEIS_MASK (1 << 9)
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#define UARTAPP_INTR_PEIS_MASK (1 << 8)
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#define UARTAPP_INTR_FEIS_MASK (1 << 7)
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#define UARTAPP_INTR_RTIS_MASK (1 << 6)
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#define UARTAPP_INTR_TXIS_MASK (1 << 5)
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#define UARTAPP_INTR_RXIS_MASK (1 << 4)
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#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
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#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
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#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
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#define UARTAPP_INTR_RIMIS_MASK 0x1
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#define UARTAPP_DATA_DATA_OFFSET 0
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#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
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#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
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#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
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#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
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#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
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#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
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#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
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#define UARTAPP_STAT_BUSY_MASK (1 << 29)
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#define UARTAPP_STAT_CTS_MASK (1 << 28)
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#define UARTAPP_STAT_TXFE_MASK (1 << 27)
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#define UARTAPP_STAT_RXFF_MASK (1 << 26)
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#define UARTAPP_STAT_TXFF_MASK (1 << 25)
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#define UARTAPP_STAT_RXFE_MASK (1 << 24)
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#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
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#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
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#define UARTAPP_STAT_OERR_MASK (1 << 19)
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#define UARTAPP_STAT_BERR_MASK (1 << 18)
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#define UARTAPP_STAT_PERR_MASK (1 << 17)
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#define UARTAPP_STAT_FERR_MASK (1 << 16)
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#define UARTAPP_STAT_RXCOUNT_OFFSET 0
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#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
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#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
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#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
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#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
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#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
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#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
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#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
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#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
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#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
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#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
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#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
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#define UARTAPP_VERSION_MAJOR_OFFSET 24
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#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
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#define UARTAPP_VERSION_MINOR_OFFSET 16
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#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
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#define UARTAPP_VERSION_STEP_OFFSET 0
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#define UARTAPP_VERSION_STEP_MASK 0xFFFF
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#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
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#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
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#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
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#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
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#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
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#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
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#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
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#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
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#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
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#endif /* __ARCH_ARM___UARTAPP_H */
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@ -38,6 +38,7 @@ COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
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COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
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COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
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COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
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COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o
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ifndef CONFIG_SPL_BUILD
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COBJS-$(CONFIG_USB_TTY) += usbtty.o
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151
drivers/serial/mxs_auart.c
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151
drivers/serial/mxs_auart.c
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/*
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* Freescale i.MX23/i.MX28 AUART driver
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*
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* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
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*
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* Based on the MXC serial driver:
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*
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* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* Further based on the Linux mxs-auart.c driver:
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*
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* Freescale STMP37XX/STMP38X Application UART drkiver
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include <asm/arch/regs-base.h>
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#include <asm/arch/regs-uartapp.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_MXS_AUART_BASE
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#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use"
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#endif
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/* AUART clock always supplied by XTAL and always 24MHz */
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#define MXS_AUART_CLK 24000000
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static struct mxs_uartapp_regs *get_uartapp_registers(void)
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{
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return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE;
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}
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/**
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* Sets the baud rate and settings.
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* The settings are: 8 data bits, no parit and 1 stop bit.
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*/
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void mxs_auart_setbrg(void)
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{
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u32 div;
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u32 linectrl = 0;
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struct mxs_uartapp_regs *regs = get_uartapp_registers();
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if (!gd->baudrate)
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gd->baudrate = CONFIG_BAUDRATE;
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/*
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* From i.MX28 datasheet:
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* div is calculated by calculating UARTCLK*32/baudrate, rounded to int
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* div must be between 0xEC and 0x003FFFC0 inclusive
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* Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register
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* Next 16 bits goes in BAUD_DIVINT part of LINECTRL register
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*/
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div = (MXS_AUART_CLK * 32) / gd->baudrate;
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if (div < 0xEC || div > 0x003FFFC0)
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return;
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linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) <<
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UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) &
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UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK;
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linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) <<
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UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) &
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UARTAPP_LINECTRL_BAUD_DIVINT_MASK;
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/* Word length: 8 bits */
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linectrl |= UARTAPP_LINECTRL_WLEN_8BITS;
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/* Enable FIFOs. */
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linectrl |= UARTAPP_LINECTRL_FEN_MASK;
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/* Write above settings, no parity, 1 stop bit */
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writel(linectrl, ®s->hw_uartapp_linectrl);
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}
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int mxs_auart_init(void)
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{
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struct mxs_uartapp_regs *regs = get_uartapp_registers();
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/* Reset everything */
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mxs_reset_block(®s->hw_uartapp_ctrl0_reg);
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/* Disable interrupts */
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writel(0, ®s->hw_uartapp_intr);
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/* Set baud rate and settings */
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serial_setbrg();
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/* Disable RTS and CTS, ignore LINECTRL2 register */
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writel(UARTAPP_CTRL2_RTSEN_MASK |
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UARTAPP_CTRL2_CTSEN_MASK |
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UARTAPP_CTRL2_USE_LCR2_MASK,
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®s->hw_uartapp_ctrl2_clr);
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/* Enable receiver, transmitter and UART */
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writel(UARTAPP_CTRL2_RXE_MASK |
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UARTAPP_CTRL2_TXE_MASK |
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UARTAPP_CTRL2_UARTEN_MASK,
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®s->hw_uartapp_ctrl2_set);
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return 0;
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}
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void mxs_auart_putc(const char c)
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{
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struct mxs_uartapp_regs *regs = get_uartapp_registers();
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/* Wait in loop while the transmit FIFO is full */
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while (readl(®s->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK)
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;
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writel(c, ®s->hw_uartapp_data);
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if (c == '\n')
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mxs_auart_putc('\r');
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}
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int mxs_auart_tstc(void)
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{
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struct mxs_uartapp_regs *regs = get_uartapp_registers();
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/* Checks if receive FIFO is empty */
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return !(readl(®s->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK);
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}
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int mxs_auart_getc(void)
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{
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struct mxs_uartapp_regs *regs = get_uartapp_registers();
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/* Wait until a character is available to read */
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while (!mxs_auart_tstc())
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;
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/* Read the character from the data register */
|
||||
return readl(®s->hw_uartapp_data) & 0xFF;
|
||||
}
|
||||
|
||||
static struct serial_device mxs_auart_drv = {
|
||||
.name = "mxs_auart_serial",
|
||||
.start = mxs_auart_init,
|
||||
.stop = NULL,
|
||||
.setbrg = mxs_auart_setbrg,
|
||||
.putc = mxs_auart_putc,
|
||||
.puts = default_serial_puts,
|
||||
.getc = mxs_auart_getc,
|
||||
.tstc = mxs_auart_tstc,
|
||||
};
|
||||
|
||||
void mxs_auart_initialize(void)
|
||||
{
|
||||
serial_register(&mxs_auart_drv);
|
||||
}
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &mxs_auart_drv;
|
||||
}
|
||||
@ -159,6 +159,7 @@ serial_initfunc(pl01x_serial_initialize);
|
||||
serial_initfunc(s3c44b0_serial_initialize);
|
||||
serial_initfunc(sa1100_serial_initialize);
|
||||
serial_initfunc(sh_serial_initialize);
|
||||
serial_initfunc(mxs_auart_initialize);
|
||||
|
||||
/**
|
||||
* serial_register() - Register serial driver with serial driver core
|
||||
@ -251,6 +252,7 @@ void serial_initialize(void)
|
||||
s3c44b0_serial_initialize();
|
||||
sa1100_serial_initialize();
|
||||
sh_serial_initialize();
|
||||
mxs_auart_initialize();
|
||||
|
||||
serial_assign(default_serial_console()->name);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user