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tny_a9260/tny_a9g20: update board to the new AT91 organization
Cc: Albin Tonnerre <tonnerrealbin@gmail.com> CC: Gregory Hermant <gregory.hermant@calao-systems.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This commit is contained in:
Thomas Petazzoni
Albert ARIBAUD
parent
6785c7c84a
commit
65b0f87a80
2
MAKEALL
2
MAKEALL
@ -446,8 +446,6 @@ LIST_ARMV7=" \
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LIST_at91="$(boards_by_soc at91)\
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at91sam9m10g45ek \
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pm9g45 \
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TNY_A9260 \
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TNY_A9G20 \
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"
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#########################################################################
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10
Makefile
10
Makefile
@ -827,16 +827,6 @@ pm9g45_config : unconfig
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@mkdir -p $(obj)include
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@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
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TNY_A9G20_NANDFLASH_config \
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TNY_A9G20_EEPROM_config \
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TNY_A9G20_config \
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TNY_A9260_NANDFLASH_config \
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TNY_A9260_EEPROM_config \
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TNY_A9260_config : unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
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@$(MKCONFIG) -n $@ -a tny_a9260 arm arm926ejs tny_a9260 calao at91
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########################################################################
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## ARM Integrator boards - see doc/README-integrator for more info.
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integratorap_config \
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@ -26,14 +26,12 @@
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -45,33 +43,36 @@ DECLARE_GLOBAL_DATA_PTR;
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static void tny_a9260_nand_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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@ -91,9 +92,9 @@ int board_init(void)
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gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_serial_hw_init();
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at91_seriald_hw_init();
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tny_a9260_nand_hw_init();
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at91_spi0_hw_init(1 << 5);
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return 0;
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@ -101,10 +102,8 @@ int board_init(void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
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return -1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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@ -104,6 +104,10 @@ snapper9260 arm arm926ejs - bluewat
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snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
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sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
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sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
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tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH
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tny_a9g20_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_EEPROM
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tny_a9260_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH
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tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM
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cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
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cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT
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cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M
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@ -30,19 +30,11 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
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#define CONFIG_TNY_A9260
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#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
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#define CONFIG_TNY_A9G20
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#endif
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#ifdef CONFIG_TNY_A9260
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#define CONFIG_AT91SAM9260
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#else
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#define CONFIG_AT91SAM9G20
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#endif
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
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#define CONFIG_ENV_IS_IN_NAND
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@ -50,29 +42,36 @@
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#define CONFIG_ENV_IS_IN_EEPROM
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#endif
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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/* Define actual evaluation board type from used processor type */
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#ifdef CONFIG_AT91SAM9G20
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# define CONFIG_TNY_A9G20
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#else
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# define CONFIG_TNY_A9260
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#endif
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_ATMEL_USART 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1 /* USART 3 is DBGU */
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#define CONFIG_ATMEL_LEGACY
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#define CONFIG_AT91_GPIO
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_BOOTDELAY 3
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@ -86,13 +85,16 @@
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SOURCE
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#undef CONFIG_CMD_USB
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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# define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
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/* SPI EEPROM */
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#define CONFIG_SPI
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@ -109,8 +111,8 @@
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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@ -119,27 +121,27 @@
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
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/* NOR flash - no real flash on this board */
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#define CONFIG_SYS_NO_FLASH 1
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_CMD_FAT 1
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_FAT
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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/* Env in EEPROM, bootstrap + u-boot in NAND*/
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_OFFSET 0x20
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_SIZE 0x1000
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#endif
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/* Env, bootstrap and u-boot in NAND */
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#ifdef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000
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#endif
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#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
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@ -149,15 +151,12 @@
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"120M(rootfs),-(other) " \
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"rw rootfstype=jffs2"
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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/*
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* Size of malloc() pool
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