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Merge branch 'master' of http://git.denx.de/u-boot-samsung
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commit
64f41212d8
@ -195,8 +195,8 @@ static void board_clock_init(void)
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while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
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continue;
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/* Set MPLL to 880MHz */
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set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1);
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/* Set MPLL to 800MHz */
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set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
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clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
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@ -220,15 +220,15 @@ static void board_clock_init(void)
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DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
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/*
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* For:
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* MOUTdmc = 880 MHz
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* MOUTdphy = 880 MHz
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* MOUTdmc = 800 MHz
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* MOUTdphy = 800 MHz
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*
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* aclk_acp = MOUTdmc / (ratio + 1) = 220 (3)
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* pclk_acp = aclk_acp / (ratio + 1) = 110 (1)
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* sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1)
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* sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1)
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* aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1)
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* aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1)
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* aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
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* pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
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* sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
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* sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
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* aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
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* aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
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*/
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set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
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DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
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@ -244,13 +244,13 @@ static void board_clock_init(void)
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C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
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/*
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* For:
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* MOUTg2d = 880 MHz
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* MOUTc2c = 880 Mhz
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* MOUTg2d = 800 MHz
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* MOUTc2c = 800 Mhz
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* MOUTpwi = 108 MHz
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*
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* sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1)
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* sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1)
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* aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1)
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* sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
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* sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
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* aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
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* sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
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*/
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set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
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@ -282,9 +282,9 @@ static void board_clock_init(void)
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clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
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UART3_RATIO(15) | UART4_RATIO(15);
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/*
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* For MOUTuart0-4: 880MHz
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* For MOUTuart0-4: 800MHz
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*
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* SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7)
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* SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
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*/
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set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
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UART3_RATIO(7) | UART4_RATIO(7);
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@ -298,12 +298,12 @@ static void board_clock_init(void)
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clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
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MMC1_PRE_RATIO(255);
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/*
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* For MOUTmmc0-3 = 880 MHz (MPLL)
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* For MOUTmmc0-3 = 800 MHz (MPLL)
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*
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* DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7)
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* sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1)
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* DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7)
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* sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1)
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* DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
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* sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
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* DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
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* sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
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*/
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set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
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MMC1_PRE_RATIO(1);
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@ -318,12 +318,12 @@ static void board_clock_init(void)
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clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
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MMC3_PRE_RATIO(255);
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/*
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* For MOUTmmc0-3 = 880 MHz (MPLL)
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* For MOUTmmc0-3 = 800 MHz (MPLL)
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*
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* DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7)
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* sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1)
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* DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7)
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* sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1)
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* DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
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* sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
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* DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
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* sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
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*/
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set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
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MMC3_PRE_RATIO(1);
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@ -337,10 +337,10 @@ static void board_clock_init(void)
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/* CLK_DIV_FSYS3 */
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clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
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/*
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* For MOUTmmc4 = 880 MHz (MPLL)
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* For MOUTmmc4 = 800 MHz (MPLL)
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*
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* DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7)
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* sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0)
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* DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
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* sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
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*/
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set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
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