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board: freescale: t208xrdb: enable Power-On Reset for rev D boards
Starting with board revision D, the MISCCSR CPLD register needs to be configured to enable Power-on Reset for software reset commands. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014 Freescale Semiconductor
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* Copyright 2021 NXP
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*/
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/*
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@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value);
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/* RSTCON Register */
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#define CPLD_RSTCON_EDC_RST 0x04
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/* MISCCSR Register */
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#define CPLD_MISC_POR_EN 0x30
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@ -128,6 +128,13 @@ int misc_init_r(void)
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reg |= CPLD_RSTCON_EDC_RST;
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CPLD_WRITE(reset_ctl, reg);
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/* Enable POR for boards revisions D and up */
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if (get_hw_revision() >= 'D') {
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reg = CPLD_READ(misc_csr);
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reg |= CPLD_MISC_POR_EN;
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CPLD_WRITE(misc_csr, reg);
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}
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return 0;
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}
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