From 217c9faa060e09cf3da3741dc07617c0697b559e Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Thu, 15 Apr 2021 08:59:18 +0200 Subject: [PATCH 001/250] configs: gardena-smart-gateway-at91sam: Adjust to production values This commit updates the default config with the values that are actually used "in the wild" and which are close to what is used on the MediaTek MT7688 based, 2nd generation of the GARDENA smart gateway: - Reduce startup time by setting bootdelay to 0 (still allows accessing the shell, one just has to send a key press quicker) - Adjusting U-Boot environment volume names and MTD partitions to the actual layout Signed-off-by: Reto Schneider Reviewed-by: Stefan Roese --- configs/gardena-smart-gateway-at91sam_defconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index e3d5bc47d6b..40fe0f150e1 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -21,7 +21,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway" CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=3 +CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -46,8 +46,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand0" -CONFIG_MTDPARTS_DEFAULT="nand0:1536k(uboot),1024k(unused),512k(dtb_old),4608k(kernel_old),86528k(ubi),-(rootfs_old)" +CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" +CONFIG_MTDPARTS_DEFAULT="atmel_nand:1536k(uboot),10752k(unused),-(ubi)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -55,8 +55,8 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt CONFIG_ENV_IS_IN_UBI=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_UBI_PART="ubi" -CONFIG_ENV_UBI_VOLUME="env" -CONFIG_ENV_UBI_VOLUME_REDUND="env_r" +CONFIG_ENV_UBI_VOLUME="uboot_env0" +CONFIG_ENV_UBI_VOLUME_REDUND="uboot_env1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y From f822b62c0238e108446a42c6ad2683e790162e84 Mon Sep 17 00:00:00 2001 From: Ilko Iliev Date: Fri, 23 Apr 2021 15:06:02 +0200 Subject: [PATCH 002/250] board: pm9261: remove network support The network support is removed because there is no DM for Davicom DM9000. Signed-off-by: Ilko Iliev --- board/ronetix/pm9261/pm9261.c | 54 ----------------------------------- configs/pm9261_defconfig | 4 +-- include/configs/pm9261.h | 9 ------ 3 files changed, 2 insertions(+), 65 deletions(-) diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 5be2c5e192b..fe52c7c1764 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -20,10 +20,6 @@ #include #include #include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) -#include -#endif -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -80,36 +76,6 @@ static void pm9261_nand_hw_init(void) } #endif - -#ifdef CONFIG_DRIVER_DM9000 -static void pm9261_dm9000_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - /* Configure SMC CS2 for DM9000 */ - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[2].setup); - - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), - &smc->cs[2].pulse); - - writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), - &smc->cs[2].cycle); - - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | - AT91_SMC_MODE_TDF_CYCLE(1), - &smc->cs[2].mode); - - /* Configure Interrupt pin as input, no pull-up */ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_set_pio_input(AT91_PIO_PORTA, 24, 0); -} -#endif - int board_early_init_f(void) { return 0; @@ -132,13 +98,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -155,19 +114,6 @@ int dram_init_banksize(void) return 0; } -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -#ifdef CONFIG_DRIVER_DM9000 - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(); -#endif -} -#endif - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard (void) { diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index e0a2ae18c61..b27fc8dbc1a 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -25,8 +25,6 @@ CONFIG_SYS_PROMPT="pm9261> " CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0,nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),-(rootfs);nand:-(nand)" @@ -34,6 +32,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x10040000 +# CONFIG_NET is not set CONFIG_DM=y CONFIG_BLK=y CONFIG_CLK=y @@ -62,3 +61,4 @@ CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_LCD=y +CONFIG_REGEX=y diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 2cc47d12379..382d19a241b 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -173,15 +173,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* Ethernet */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x30000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_DM9000_USE_16BIT 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 - /* USB */ #define CONFIG_USB_ATMEL #define CONFIG_USB_ATMEL_CLK_SEL_PLLB From 8ad3a77a74093406257acdb3842c94cf80737735 Mon Sep 17 00:00:00 2001 From: Ilko Iliev Date: Fri, 23 Apr 2021 15:41:21 +0200 Subject: [PATCH 003/250] board: pm9263: switch to use DM_ETH Enable CONFIG_DM_ETH in configs/pm9263_defconfig Drop legacy initialization in board/ronetix/pm9263.c Remove network related setting from include/configs/pm9263.h Signed-off-by: Ilko Iliev --- board/ronetix/pm9263/pm9263.c | 57 ----------------------------------- configs/pm9263_defconfig | 2 ++ include/configs/pm9263.h | 6 ---- 3 files changed, 2 insertions(+), 63 deletions(-) diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 95c0dec4db5..46494b043fa 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -19,10 +19,6 @@ #include #include #include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -73,41 +69,6 @@ static void pm9263_nand_hw_init(void) } #endif -#ifdef CONFIG_MACB -static void pm9263_macb_hw_init(void) -{ - /* - * PB27 enables the 50MHz oscillator for Ethernet PHY - * 1 - enable - * 0 - disable - */ - at91_set_pio_output(AT91_PIO_PORTB, 27, 1); - at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PC25) => PHY normal mode (not Test mode) - * ERX0 (PE25) => PHY ADDR0 - * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - - at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); - at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); - at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); - - /* Re-enable pull-up */ - at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); - at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); - at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); - - at91_macb_hw_init(); -} -#endif - #ifdef CONFIG_LCD #ifdef CONFIG_LCD_IN_PSRAM @@ -233,9 +194,6 @@ int board_init(void) #ifdef CONFIG_CMD_NAND pm9263_nand_hw_init(); #endif -#ifdef CONFIG_MACB - pm9263_macb_hw_init(); -#endif #ifdef CONFIG_USB_OHCI_NEW at91_uhp_hw_init(); #endif @@ -261,21 +219,6 @@ int dram_init_banksize(void) return 0; } -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); -#endif - return rc; -} - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard (void) { diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 817a9847beb..ef18e742d27 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -50,6 +50,8 @@ CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_DM_ETH=y +CONFIG_MACB=y CONFIG_DM_SERIAL=y CONFIG_ATMEL_USART=y CONFIG_SPI=y diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 6c882b6ff94..7b028751bda 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -204,12 +204,6 @@ AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) -/* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 - /* USB */ #define CONFIG_USB_ATMEL #define CONFIG_USB_ATMEL_CLK_SEL_PLLB From 4bf3a3fc391661a96026e81553d58a562c2f03c7 Mon Sep 17 00:00:00 2001 From: Ilko Iliev Date: Fri, 23 Apr 2021 15:41:34 +0200 Subject: [PATCH 004/250] board: pm9263: fix some typos in comments Fix comment typos Signed-off-by: Ilko Iliev --- board/ronetix/pm9263/pm9263.c | 10 +++++----- include/configs/pm9263.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 46494b043fa..6dc080ac2c3 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; /* ------------------------------------------------------------------------- */ /* - * Miscelaneous platform dependent initialisations + * Miscellaneous platform dependent initializations */ #ifdef CONFIG_CMD_NAND @@ -166,7 +166,7 @@ static void pm9263_lcd_hw_init(void) at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ #ifdef CONFIG_LCD_IN_PSRAM - /* initialize te PSRAM */ + /* initialize the PSRAM */ int stat = pm9263_lcd_hw_psram_init(); gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; @@ -185,10 +185,10 @@ int board_early_init_f(void) int board_init(void) { - /* arch number of AT91SAM9263EK-Board */ + /* arch number of PM9263 Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9263; - /* adress of boot parameters */ + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_CMD_NAND @@ -205,7 +205,7 @@ int board_init(void) int dram_init(void) { - /* dram_init must store complete ramsize in gd->ram_size */ + /* dram_init must store complete RAM size in gd->ram_size */ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 7b028751bda..e825270de8a 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -5,7 +5,7 @@ * Lead Tech Design * Ilko Iliev * - * Configuation settings for the RONETIX PM9263 board. + * Configuration settings for the RONETIX PM9263 board. */ #ifndef __CONFIG_H From 0b4f0081746369bb1954cfeb1cfb1d3b4ff3e6b0 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 29 Apr 2021 14:58:21 +0300 Subject: [PATCH 005/250] configs: sama7g5ek: increase bootm len Increase the BOOTM_LEN to 32M . This would allow a bigger kernel image to be booted, for example the multi_v7_defconfig. Loading Kernel Image Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover resetting ... Signed-off-by: Eugen Hristev --- include/configs/sama7g5ek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index ef3bfa36fd4..96db82e9d46 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -11,7 +11,7 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ - +#define CONFIG_SYS_BOOTM_LEN SZ_32M /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 From a1c93bde36fa05edb2f481e83f92800805b3085d Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 18 May 2021 11:58:42 +0300 Subject: [PATCH 006/250] configs: sama5d27_wlsom1_ek_mmc: add default bootargs Add default bootarguments with booting from mmc0 for this configuration. This will allow a default Linux boot for this board. Suggested-by: Jarvis Chen Signed-off-by: Eugen Hristev --- configs/sama5d27_wlsom1_ek_mmc_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index b7624beb4ce..f019e073aba 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y From 55661ee0e3cf518e1b89939f00fda50b326d3139 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 21 May 2021 11:52:04 +0300 Subject: [PATCH 007/250] Revert "sama5d3: Fix Galois Field Table offsets" This reverts commit 786f888b743e9b83c9095cb9b5548ebe2e29afc5. Looks like the datasheet at https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D3-Series-Data-sheet-DS60001609b.pdf is wrong, and the testing was poorly done, because the PMECC did not raise any error, but also didn't correct any bitflips. Restoring the offsets as they were before, makes the PMECC on sama5d3x capable of correcting bitflips. Fixes: 786f888b74 ("sama5d3: Fix Galois Field Table offsets") Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/include/mach/sama5d3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index f4f05676f72..83f18a8148f 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -190,8 +190,8 @@ /* * PMECC table in ROM */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 /* * SAMA5D3 specific prototypes From 32cc2368f816bf21e5e5ffc6070a8abcd8d3e02d Mon Sep 17 00:00:00 2001 From: "Kai Stuhlemmer (ebee Engineering)" Date: Fri, 21 May 2021 11:52:06 +0300 Subject: [PATCH 008/250] nand: atmel: Correct bitflips in erased pages Not correcting anything in case of empty ECC data area is not an appropriate strategy, because an uncorrected bit-flip in an empty sector may cause upper layers (namely UBI) fail to work properly. Therefore the approach chosen in Linux kernel and other u-boot mtd drivers has been adopted, where a heuristic implemented by nand_check_erased_ecc_chunk() is used in order to detect and correct empty sectors. Tested with sama5d3_xplained and sam9x60-ek. Signed-off-by: Kai Stuhlemmer (ebee Engineering) Tested-by: Tudor Ambarus [ta: reorder if conditions, change commit subject, s/uint8_t/u8.] Signed-off-by: Tudor Ambarus --- drivers/mtd/nand/raw/atmel_nand.c | 37 +++++++++++++++---------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index abc432c8626..6541c3bea85 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -493,21 +493,9 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, { struct nand_chip *nand_chip = mtd_to_nand(mtd); struct atmel_nand_host *host = nand_get_controller_data(nand_chip); - int i, err_nbr, eccbytes; - uint8_t *buf_pos; + int i, err_nbr; + u8 *buf_pos, *ecc_pos; - /* SAMA5D4 PMECC IP can correct errors for all 0xff page */ - if (host->pmecc_version >= PMECC_VERSION_SAMA5D4) - goto normal_check; - - eccbytes = nand_chip->ecc.bytes; - for (i = 0; i < eccbytes; i++) - if (ecc[i] != 0xff) - goto normal_check; - /* Erased page, return OK */ - return 0; - -normal_check: for (i = 0; i < host->pmecc_sector_number; i++) { err_nbr = 0; if (pmecc_stat & 0x1) { @@ -518,15 +506,26 @@ normal_check: pmecc_get_sigma(mtd); err_nbr = pmecc_err_location(mtd); - if (err_nbr == -1) { + if (err_nbr >= 0) { + pmecc_correct_data(mtd, buf_pos, ecc, i, + host->pmecc_bytes_per_sector, + err_nbr); + } else if (host->pmecc_version < PMECC_VERSION_SAMA5D4) { + ecc_pos = ecc + i * host->pmecc_bytes_per_sector; + + err_nbr = nand_check_erased_ecc_chunk( + buf_pos, host->pmecc_sector_size, + ecc_pos, host->pmecc_bytes_per_sector, + NULL, 0, host->pmecc_corr_cap); + } + + if (err_nbr < 0) { dev_err(mtd->dev, "PMECC: Too many errors\n"); mtd->ecc_stats.failed++; return -EBADMSG; - } else { - pmecc_correct_data(mtd, buf_pos, ecc, i, - host->pmecc_bytes_per_sector, err_nbr); - mtd->ecc_stats.corrected += err_nbr; } + + mtd->ecc_stats.corrected += err_nbr; } pmecc_stat >>= 1; } From 4e89e4fc18c7278f70fdcec5045aa68b7598185e Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 21 May 2021 11:52:05 +0300 Subject: [PATCH 009/250] configs: sam9x60ek: Enable NAND on mmc defconfig Enable NAND on mmc defconfig for greater flexibility and for consistency reasons. All our other boards that have a NAND flash integrated, enable NAND regardless of the type of the defconfig. Signed-off-by: Tudor Ambarus --- configs/sam9x60ek_mmc_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index e97b20aeb33..e5edf45fee5 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -25,6 +25,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -48,6 +50,11 @@ CONFIG_MICROCHIP_FLEXCOM=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=8 CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y From 59c0ea5df33fc4d9b62226d29e3b5c61d639303f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:29 +0200 Subject: [PATCH 010/250] lmb: Add support of flags for no-map properties Add "flags" in lmb_property to save the "no-map" property of reserved region and a new function lmb_reserve_flags() to check this flag. The default allocation use flags = LMB_NONE. The adjacent reserved memory region are merged only when they have the same flags value. This patch is partially based on flags support done in Linux kernel mm/memblock .c (previously lmb.c); it is why LMB_NOMAP = 0x4, it is aligned with MEMBLOCK_NOMAP value. Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- include/lmb.h | 29 +++++++++++++++++++++++++++ lib/lmb.c | 54 +++++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 73 insertions(+), 10 deletions(-) diff --git a/include/lmb.h b/include/lmb.h index 541e17093c6..e900b3dd65c 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -12,6 +12,16 @@ * Copyright (C) 2001 Peter Bergner, IBM Corp. */ +/** + * enum lmb_flags - definition of memory region attributes + * @LMB_NONE: no special request + * @LMB_NOMAP: don't add to mmu configuration + */ +enum lmb_flags { + LMB_NONE = 0x0, + LMB_NOMAP = 0x4, +}; + /** * struct lmb_property - Description of one region. * @@ -21,6 +31,7 @@ struct lmb_property { phys_addr_t base; phys_size_t size; + enum lmb_flags flags; }; /** @@ -69,6 +80,17 @@ extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, phys_size_t size, void *fdt_blob); extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); +/** + * lmb_reserve_flags - Reserve one region with a specific flags bitfield. + * + * @lmb the logical memory block struct + * @base base address of the memory region + * @size size of the memory region + * @flags flags for the memory region + * @return 0 if OK, > 0 for coalesced region or a negative error code. + */ +long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, + phys_size_t size, enum lmb_flags flags); extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr); @@ -92,6 +114,13 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) void board_lmb_reserve(struct lmb *lmb); void arch_lmb_reserve(struct lmb *lmb); +/* Low level functions */ + +static inline bool lmb_is_nomap(struct lmb_property *m) +{ + return m->flags & LMB_NOMAP; +} + #endif /* __KERNEL__ */ #endif /* _LINUX_LMB_H */ diff --git a/lib/lmb.c b/lib/lmb.c index c08c4d942b7..69700bf9baf 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -25,6 +25,8 @@ void lmb_dump_all_force(struct lmb *lmb) (unsigned long long)lmb->memory.region[i].base); printf(" .size = 0x%llx\n", (unsigned long long)lmb->memory.region[i].size); + printf(" .flags = 0x%x\n", + lmb->memory.region[i].flags); } printf("\n reserved.cnt = 0x%lx\n", lmb->reserved.cnt); @@ -33,6 +35,8 @@ void lmb_dump_all_force(struct lmb *lmb) (unsigned long long)lmb->reserved.region[i].base); printf(" .size = 0x%llx\n", (unsigned long long)lmb->reserved.region[i].size); + printf(" .flags = 0x%x\n", + lmb->reserved.region[i].flags); } } @@ -81,6 +85,7 @@ static void lmb_remove_region(struct lmb_region *rgn, unsigned long r) for (i = r; i < rgn->cnt - 1; i++) { rgn->region[i].base = rgn->region[i + 1].base; rgn->region[i].size = rgn->region[i + 1].size; + rgn->region[i].flags = rgn->region[i + 1].flags; } rgn->cnt--; } @@ -144,7 +149,8 @@ void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, } /* This routine called with relocation disabled. */ -static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) +static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, + phys_size_t size, enum lmb_flags flags) { unsigned long coalesced = 0; long adjacent, i; @@ -152,6 +158,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t if (rgn->cnt == 0) { rgn->region[0].base = base; rgn->region[0].size = size; + rgn->region[0].flags = flags; rgn->cnt = 1; return 0; } @@ -160,18 +167,27 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t for (i = 0; i < rgn->cnt; i++) { phys_addr_t rgnbase = rgn->region[i].base; phys_size_t rgnsize = rgn->region[i].size; + phys_size_t rgnflags = rgn->region[i].flags; - if ((rgnbase == base) && (rgnsize == size)) - /* Already have this region, so we're done */ - return 0; + if (rgnbase == base && rgnsize == size) { + if (flags == rgnflags) + /* Already have this region, so we're done */ + return 0; + else + return -1; /* regions with new flags */ + } adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); if (adjacent > 0) { + if (flags != rgnflags) + break; rgn->region[i].base -= size; rgn->region[i].size += size; coalesced++; break; } else if (adjacent < 0) { + if (flags != rgnflags) + break; rgn->region[i].size += size; coalesced++; break; @@ -182,8 +198,10 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t } if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) { - lmb_coalesce_regions(rgn, i, i + 1); - coalesced++; + if (rgn->region[i].flags == rgn->region[i + 1].flags) { + lmb_coalesce_regions(rgn, i, i + 1); + coalesced++; + } } if (coalesced) @@ -196,9 +214,11 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t if (base < rgn->region[i].base) { rgn->region[i + 1].base = rgn->region[i].base; rgn->region[i + 1].size = rgn->region[i].size; + rgn->region[i + 1].flags = rgn->region[i].flags; } else { rgn->region[i + 1].base = base; rgn->region[i + 1].size = size; + rgn->region[i + 1].flags = flags; break; } } @@ -206,6 +226,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t if (base < rgn->region[0].base) { rgn->region[0].base = base; rgn->region[0].size = size; + rgn->region[0].flags = flags; } rgn->cnt++; @@ -213,6 +234,12 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t return 0; } +static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, + phys_size_t size) +{ + return lmb_add_region_flags(rgn, base, size, LMB_NONE); +} + /* This routine may be called with relocation disabled. */ long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) { @@ -267,14 +294,21 @@ long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) * beginging of the hole and add the region after hole. */ rgn->region[i].size = base - rgn->region[i].base; - return lmb_add_region(rgn, end + 1, rgnend - end); + return lmb_add_region_flags(rgn, end + 1, rgnend - end, + rgn->region[i].flags); +} + +long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size, + enum lmb_flags flags) +{ + struct lmb_region *_rgn = &(lmb->reserved); + + return lmb_add_region_flags(_rgn, base, size, flags); } long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) { - struct lmb_region *_rgn = &(lmb->reserved); - - return lmb_add_region(_rgn, base, size); + return lmb_reserve_flags(lmb, base, size, LMB_NONE); } static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, From e359a4a5c1f01add83b8f39f5da0c61ce51e918a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:30 +0200 Subject: [PATCH 011/250] lmb: add lmb_is_reserved_flags Add a new function lmb_is_reserved_flags to check if an address is reserved with a specific flags. This function can be used to check if an address was reserved with no-map flags with: lmb_is_reserved_flags(lmb, addr, LMB_NOMAP); Signed-off-by: Patrick Delaunay --- include/lmb.h | 9 +++++++++ lib/lmb.c | 9 +++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/lmb.h b/include/lmb.h index e900b3dd65c..3c4afdf9f06 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -100,6 +100,15 @@ extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr); extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); +/** + * lmb_is_reserved_flags - test if tha address is in reserved region with a bitfield flag + * + * @lmb the logical memory block struct + * @addr address to be tested + * @flags flags bitfied to be tested + * @return 0 if not reserved or reserved without the requested flag else 1 + */ +int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags); extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern void lmb_dump_all(struct lmb *lmb); diff --git a/lib/lmb.c b/lib/lmb.c index 69700bf9baf..a0fb8c7e88d 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -443,7 +443,7 @@ phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr) return 0; } -int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) +int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags) { int i; @@ -451,11 +451,16 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) phys_addr_t upper = lmb->reserved.region[i].base + lmb->reserved.region[i].size - 1; if ((addr >= lmb->reserved.region[i].base) && (addr <= upper)) - return 1; + return (lmb->reserved.region[i].flags & flags) == flags; } return 0; } +int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) +{ + return lmb_is_reserved_flags(lmb, addr, LMB_NONE); +} + __weak void board_lmb_reserve(struct lmb *lmb) { /* please define platform specific board_lmb_reserve() */ From 358c7789afb8b1723be596040fbfb4964cc3f703 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:31 +0200 Subject: [PATCH 012/250] lmb: add lmb_dump_region() function Add lmb_dump_region() function, to simplify lmb_dump_all_force(). This patch is based on Linux memblock dump function. An example of bdinfo output is: ..... fdt_size = 0x000146a0 FB base = 0xfdd00000 lmb_dump_all: memory.cnt = 0x1 memory[0] [0xc0000000-0xffffffff], 0x40000000 bytes flags: 0 reserved.cnt = 0x6 reserved[0] [0x10000000-0x10045fff], 0x00046000 bytes flags: 4 reserved[1] [0x30000000-0x3003ffff], 0x00040000 bytes flags: 4 reserved[2] [0x38000000-0x3800ffff], 0x00010000 bytes flags: 4 reserved[3] [0xe8000000-0xefffffff], 0x08000000 bytes flags: 4 reserved[4] [0xfbaea344-0xfdffffff], 0x02515cbc bytes flags: 0 reserved[5] [0xfe000000-0xffffffff], 0x02000000 bytes flags: 4 arch_number = 0x00000000 TLB addr = 0xfdff0000 .... Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- lib/lmb.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/lib/lmb.c b/lib/lmb.c index a0fb8c7e88d..7bd1255f7a4 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -14,30 +14,30 @@ #define LMB_ALLOC_ANYWHERE 0 +static void lmb_dump_region(struct lmb_region *rgn, char *name) +{ + unsigned long long base, size, end; + enum lmb_flags flags; + int i; + + printf(" %s.cnt = 0x%lx\n", name, rgn->cnt); + + for (i = 0; i < rgn->cnt; i++) { + base = rgn->region[i].base; + size = rgn->region[i].size; + end = base + size - 1; + flags = rgn->region[i].flags; + + printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x\n", + name, i, base, end, size, flags); + } +} + void lmb_dump_all_force(struct lmb *lmb) { - unsigned long i; - printf("lmb_dump_all:\n"); - printf(" memory.cnt = 0x%lx\n", lmb->memory.cnt); - for (i = 0; i < lmb->memory.cnt; i++) { - printf(" memory.reg[0x%lx].base = 0x%llx\n", i, - (unsigned long long)lmb->memory.region[i].base); - printf(" .size = 0x%llx\n", - (unsigned long long)lmb->memory.region[i].size); - printf(" .flags = 0x%x\n", - lmb->memory.region[i].flags); - } - - printf("\n reserved.cnt = 0x%lx\n", lmb->reserved.cnt); - for (i = 0; i < lmb->reserved.cnt; i++) { - printf(" reserved.reg[0x%lx].base = 0x%llx\n", i, - (unsigned long long)lmb->reserved.region[i].base); - printf(" .size = 0x%llx\n", - (unsigned long long)lmb->reserved.region[i].size); - printf(" .flags = 0x%x\n", - lmb->reserved.region[i].flags); - } + lmb_dump_region(&lmb->memory, "memory"); + lmb_dump_region(&lmb->reserved, "reserved"); } void lmb_dump_all(struct lmb *lmb) From 7d08a3dd02125f2d2a49c0f99ad901e2c3db3389 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:32 +0200 Subject: [PATCH 013/250] test: lmb: add test for lmb_reserve_flags Add a test to check the management of reserved region with flags. Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- test/lib/lmb.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 0d8963fcbf3..b2c2b99ef19 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -723,3 +723,92 @@ static int lib_test_lmb_max_regions(struct unit_test_state *uts) DM_TEST(lib_test_lmb_max_regions, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +static int lib_test_lmb_flags(struct unit_test_state *uts) +{ + const phys_addr_t ram = 0x40000000; + const phys_size_t ram_size = 0x20000000; + struct lmb lmb; + long ret; + + lmb_init(&lmb); + + ret = lmb_add(&lmb, ram, ram_size); + ut_asserteq(ret, 0); + + /* reserve, same flag */ + ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 0); + ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + 0, 0, 0, 0); + + /* reserve again, same flag */ + ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 0); + ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + 0, 0, 0, 0); + + /* reserve again, new flag */ + ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NONE); + ut_asserteq(ret, -1); + ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + 0, 0, 0, 0); + + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + + /* merge after */ + ret = lmb_reserve_flags(&lmb, 0x40020000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 1); + ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x20000, + 0, 0, 0, 0); + + /* merge before */ + ret = lmb_reserve_flags(&lmb, 0x40000000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 1); + ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x30000, + 0, 0, 0, 0); + + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + + ret = lmb_reserve_flags(&lmb, 0x40030000, 0x10000, LMB_NONE); + ut_asserteq(ret, 0); + ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000, + 0x40030000, 0x10000, 0, 0); + + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); + + /* test that old API use LMB_NONE */ + ret = lmb_reserve(&lmb, 0x40040000, 0x10000); + ut_asserteq(ret, 1); + ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000, + 0x40030000, 0x20000, 0, 0); + + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); + + ret = lmb_reserve_flags(&lmb, 0x40070000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 0); + ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000, + 0x40030000, 0x20000, 0x40070000, 0x10000); + + ret = lmb_reserve_flags(&lmb, 0x40050000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 0); + ASSERT_LMB(&lmb, ram, ram_size, 4, 0x40000000, 0x30000, + 0x40030000, 0x20000, 0x40050000, 0x10000); + + /* merge with 2 adjacent regions */ + ret = lmb_reserve_flags(&lmb, 0x40060000, 0x10000, LMB_NOMAP); + ut_asserteq(ret, 2); + ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000, + 0x40030000, 0x20000, 0x40050000, 0x30000); + + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); + ut_asserteq(lmb_is_nomap(&lmb.reserved.region[2]), 1); + + return 0; +} + +DM_TEST(lib_test_lmb_flags, + UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From f46959cef4360960103d84467b82a56d56152fe4 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:33 +0200 Subject: [PATCH 014/250] image-fdt: save no-map parameter of reserve-memory Save the 'no-map' information present in 'reserved-memory' node to allow correct handling when the MMU is configured in board to avoid speculative access. This binding is defined in doc/device-tree-bindings/reserved-memory/reserved-memory.txt Additional properties: ... no-map (optional) - empty property - Indicates the operating system must not create a virtual mapping of the region as part of its standard mapping of system memory, nor permit speculative access to it under any circumstances other than under the control of the device driver using the region. Signed-off-by: Patrick Delaunay --- common/image-fdt.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index d50e1ba3feb..06dce92a28a 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -75,18 +75,20 @@ static const image_header_t *image_get_fdt(ulong fdt_addr) #endif static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr, - uint64_t size) + uint64_t size, enum lmb_flags flags) { long ret; - ret = lmb_reserve(lmb, addr, size); + ret = lmb_reserve_flags(lmb, addr, size, flags); if (ret >= 0) { - debug(" reserving fdt memory region: addr=%llx size=%llx\n", - (unsigned long long)addr, (unsigned long long)size); + debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", + (unsigned long long)addr, + (unsigned long long)size, flags); } else { puts("ERROR: reserving fdt memory region failed "); - printf("(addr=%llx size=%llx)\n", - (unsigned long long)addr, (unsigned long long)size); + printf("(addr=%llx size=%llx flags=%x)\n", + (unsigned long long)addr, + (unsigned long long)size, flags); } } @@ -106,6 +108,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) int i, total, ret; int nodeoffset, subnode; struct fdt_resource res; + enum lmb_flags flags; if (fdt_check_header(fdt_blob) != 0) return; @@ -115,7 +118,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) for (i = 0; i < total; i++) { if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) continue; - boot_fdt_reserve_region(lmb, addr, size); + boot_fdt_reserve_region(lmb, addr, size, LMB_NONE); } /* process reserved-memory */ @@ -127,9 +130,13 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) ret = fdt_get_resource(fdt_blob, subnode, "reg", 0, &res); if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) { + flags = LMB_NONE; + if (fdtdec_get_bool(fdt_blob, subnode, + "no-map")) + flags = LMB_NOMAP; addr = res.start; size = res.end - res.start + 1; - boot_fdt_reserve_region(lmb, addr, size); + boot_fdt_reserve_region(lmb, addr, size, flags); } subnode = fdt_next_subnode(fdt_blob, subnode); From 7dc6068fc10d699558176da364a3e7a6cfccdaa1 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:34 +0200 Subject: [PATCH 015/250] stm32mp: Increase the reserved memory in board_get_usable_ram_top Add 8M for the U-Boot reserved memory (display, fdt, gd, ...) mapped cacheable before relocation. Without this patch the device tree, located before the MALLOC area is not tagged cacheable just after relocation, before mmu reconfiguration. This patch reduces the duration for device tree parsing in lmb_init_and_reserve. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/dram_init.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 66e81baccaf..3c097029bda 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -50,13 +50,16 @@ ulong board_get_usable_ram_top(ulong total_size) lmb_init(&lmb); lmb_add(&lmb, gd->ram_base, gd->ram_size); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); - size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), + /* add 8M for reserved memory for display, fdt, gd,... */ + size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); if (!reg) reg = gd->ram_top - size; - mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); + /* before relocation, mark the U-Boot memory as cacheable by default */ + if (!(gd->flags & GD_FLG_RELOC)) + mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); return reg + size; } From ade4e0428f4d85454fdb3818702facc7728a274a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 May 2021 14:50:35 +0200 Subject: [PATCH 016/250] stm32mp: don't map the reserved region with no-map property No more map the reserved region with "no-map" property by marking the corresponding TLB entries with invalid entry (=0) to avoid speculative access. The device tree parsing done in lmb_init_and_reserve() takes a long time when it is executed without data cache, so it is called in enable_caches() before to disable it. This patch fixes an issue where predictive read access on secure DDR OP-TEE reserved area are caught by firewall. Series-cc: marex Series-cc: pch Series-cc: marek.bykowski@gmail.com Series-cc: Ard Biesheuvel Series-cc: Etienne Carriere Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cpu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 8115d58b199..592bfd413df 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -90,6 +91,8 @@ */ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); +struct lmb lmb; + #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) #ifndef CONFIG_TFABOOT static void security_init(void) @@ -221,6 +224,8 @@ void dram_bank_mmu_setup(int bank) int i; phys_addr_t start; phys_size_t size; + bool use_lmb = false; + enum dcache_option option; if (IS_ENABLED(CONFIG_SPL_BUILD)) { start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); @@ -229,6 +234,7 @@ void dram_bank_mmu_setup(int bank) /* bd->bi_dram is available only after relocation */ start = bd->bi_dram[bank].start; size = bd->bi_dram[bank].size; + use_lmb = true; } else { /* mark cacheable and executable the beggining of the DDR */ start = STM32_DDR_BASE; @@ -237,8 +243,12 @@ void dram_bank_mmu_setup(int bank) for (i = start >> MMU_SECTION_SHIFT; i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); - i++) - set_section_dcache(i, DCACHE_DEFAULT_OPTION); + i++) { + option = DCACHE_DEFAULT_OPTION; + if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) + option = 0; /* INVALID ENTRY in TLB */ + set_section_dcache(i, option); + } } /* * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage @@ -302,6 +312,9 @@ int arch_cpu_init(void) void enable_caches(void) { + /* parse device tree when data cache is still activated */ + lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + /* I-cache is already enabled in start.S: icache_enable() not needed */ /* deactivate the data cache, early enabled in arch_cpu_init() */ From c1a2bb4f836a1c96c8e39a67be9795d462ec3356 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 06:59:56 -0600 Subject: [PATCH 017/250] console: Report an error when output buffer is exhausted If the console output buffer is exhausted, characters are silently dropped from the end. Detect this condition and report an error when reading back the characters. Signed-off-by: Simon Glass --- common/console.c | 18 +++++++++++---- include/asm-generic/global_data.h | 16 ++++++++----- include/console.h | 3 ++- test/ut.c | 37 ++++++++++++++++++++++++++----- 4 files changed, 58 insertions(+), 16 deletions(-) diff --git a/common/console.c b/common/console.c index 561cdf36a74..73edb287992 100644 --- a/common/console.c +++ b/common/console.c @@ -95,16 +95,22 @@ static void console_record_putc(const char c) { if (!(gd->flags & GD_FLG_RECORD)) return; - if (gd->console_out.start) - membuff_putbyte((struct membuff *)&gd->console_out, c); + if (gd->console_out.start && + !membuff_putbyte((struct membuff *)&gd->console_out, c)) + gd->flags |= GD_FLG_RECORD_OVF; } static void console_record_puts(const char *s) { if (!(gd->flags & GD_FLG_RECORD)) return; - if (gd->console_out.start) - membuff_put((struct membuff *)&gd->console_out, s, strlen(s)); + if (gd->console_out.start) { + int len = strlen(s); + + if (membuff_put((struct membuff *)&gd->console_out, s, len) != + len) + gd->flags |= GD_FLG_RECORD_OVF; + } } static int console_record_getc(void) @@ -742,6 +748,7 @@ void console_record_reset(void) { membuff_purge((struct membuff *)&gd->console_out); membuff_purge((struct membuff *)&gd->console_in); + gd->flags &= ~GD_FLG_RECORD_OVF; } int console_record_reset_enable(void) @@ -754,6 +761,9 @@ int console_record_reset_enable(void) int console_record_readline(char *str, int maxlen) { + if (gd->flags & GD_FLG_RECORD_OVF) + return -ENOSPC; + return membuff_readline((struct membuff *)&gd->console_out, str, maxlen, ' '); } diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 47921d27b13..e278d4c9413 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -571,30 +571,34 @@ enum gd_flags { * @GD_FLG_RECORD: record console */ GD_FLG_RECORD = 0x01000, + /** + * @GD_FLG_RECORD_OVF: record console overflow + */ + GD_FLG_RECORD_OVF = 0x02000, /** * @GD_FLG_ENV_DEFAULT: default variable flag */ - GD_FLG_ENV_DEFAULT = 0x02000, + GD_FLG_ENV_DEFAULT = 0x04000, /** * @GD_FLG_SPL_EARLY_INIT: early SPL initialization is done */ - GD_FLG_SPL_EARLY_INIT = 0x04000, + GD_FLG_SPL_EARLY_INIT = 0x08000, /** * @GD_FLG_LOG_READY: log system is ready for use */ - GD_FLG_LOG_READY = 0x08000, + GD_FLG_LOG_READY = 0x10000, /** * @GD_FLG_WDT_READY: watchdog is ready for use */ - GD_FLG_WDT_READY = 0x10000, + GD_FLG_WDT_READY = 0x20000, /** * @GD_FLG_SKIP_LL_INIT: don't perform low-level initialization */ - GD_FLG_SKIP_LL_INIT = 0x20000, + GD_FLG_SKIP_LL_INIT = 0x40000, /** * @GD_FLG_SMP_READY: SMP initialization is complete */ - GD_FLG_SMP_READY = 0x40000, + GD_FLG_SMP_READY = 0x80000, }; #endif /* __ASSEMBLY__ */ diff --git a/include/console.h b/include/console.h index 7e628c0cf83..f848bcbf037 100644 --- a/include/console.h +++ b/include/console.h @@ -72,7 +72,8 @@ int console_record_reset_enable(void); * * @str: Place to put string * @maxlen: Maximum length of @str including nul terminator - * @return length of string returned + * @return length of string returned, or -ENOSPC if the console buffer was + * overflowed by the output */ int console_record_readline(char *str, int maxlen); diff --git a/test/ut.c b/test/ut.c index ea0af153e4a..a0fe5facac7 100644 --- a/test/ut.c +++ b/test/ut.c @@ -51,14 +51,31 @@ long ut_check_delta(ulong last) return ut_check_free() - last; } +static int readline_check(struct unit_test_state *uts) +{ + int ret; + + ret = console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + if (ret == -ENOSPC) { + ut_fail(uts, __FILE__, __LINE__, __func__, + "Console record buffer too small - increase CONFIG_CONSOLE_RECORD_OUT_SIZE"); + return ret; + } + + return 0; +} + int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...) { va_list args; + int ret; va_start(args, fmt); vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); va_end(args); - console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + ret = readline_check(uts); + if (ret < 0) + return ret; return strcmp(uts->expect_str, uts->actual_str); } @@ -66,11 +83,14 @@ int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...) int ut_check_console_linen(struct unit_test_state *uts, const char *fmt, ...) { va_list args; + int ret; va_start(args, fmt); vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); va_end(args); - console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + ret = readline_check(uts); + if (ret < 0) + return ret; return strncmp(uts->expect_str, uts->actual_str, strlen(uts->expect_str)); @@ -78,19 +98,26 @@ int ut_check_console_linen(struct unit_test_state *uts, const char *fmt, ...) int ut_check_skipline(struct unit_test_state *uts) { + int ret; + if (!console_record_avail()) return -ENFILE; - console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + ret = readline_check(uts); + if (ret < 0) + return ret; return 0; } int ut_check_console_end(struct unit_test_state *uts) { + int ret; + if (!console_record_avail()) return 0; - - console_record_readline(uts->actual_str, sizeof(uts->actual_str)); + ret = readline_check(uts); + if (ret < 0) + return ret; return 1; } From 090d664eac6ff3bdb39c871bb9079df8e22873fc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 06:59:57 -0600 Subject: [PATCH 018/250] test: Detect when expect_str is too small If a line of more than 256 bytes is generated, the test will fail but the reason is not clear. Add a check for this condition and print a helpful message. Signed-off-by: Simon Glass --- test/ut.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/test/ut.c b/test/ut.c index a0fe5facac7..350509a2926 100644 --- a/test/ut.c +++ b/test/ut.c @@ -68,11 +68,17 @@ static int readline_check(struct unit_test_state *uts) int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...) { va_list args; + int len; int ret; va_start(args, fmt); - vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); + len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); va_end(args); + if (len >= sizeof(uts->expect_str)) { + ut_fail(uts, __FILE__, __LINE__, __func__, + "unit_test_state->expect_str too small"); + return -EOVERFLOW; + } ret = readline_check(uts); if (ret < 0) return ret; @@ -83,11 +89,17 @@ int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...) int ut_check_console_linen(struct unit_test_state *uts, const char *fmt, ...) { va_list args; + int len; int ret; va_start(args, fmt); - vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); + len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); va_end(args); + if (len >= sizeof(uts->expect_str)) { + ut_fail(uts, __FILE__, __LINE__, __func__, + "unit_test_state->expect_str too small"); + return -EOVERFLOW; + } ret = readline_check(uts); if (ret < 0) return ret; From fbb99dcec099254f77efd7e16cdc5b31c46cc888 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 06:59:58 -0600 Subject: [PATCH 019/250] test: Convert print tests to use ut framework This test predates the test framework in U-Boot. It uses #define DEBUG and assert() to check the result. Update it to use the framework so it can report failure constitent with other tests. Signed-off-by: Simon Glass --- include/test/suites.h | 1 + test/cmd_ut.c | 2 + test/print_ut.c | 113 ++++++++++++++++++++++-------------------- 3 files changed, 61 insertions(+), 55 deletions(-) diff --git a/include/test/suites.h b/include/test/suites.h index f5d8e139cee..80b41f188c7 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -41,6 +41,7 @@ int do_ut_mem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_overlay(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_setexpr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_str(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/test/cmd_ut.c b/test/cmd_ut.c index b9c166045da..6f174c6a07f 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -51,6 +51,7 @@ static struct cmd_tbl cmd_ut_sub[] = { U_BOOT_CMD_MKENT(setexpr, CONFIG_SYS_MAXARGS, 1, do_ut_setexpr, "", ""), #endif + U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_ut_print, "", ""), #ifdef CONFIG_UT_TIME U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""), #endif @@ -132,6 +133,7 @@ static char ut_help_text[] = #ifdef CONFIG_UT_OVERLAY "ut overlay [test-name]\n" #endif + "ut print [test-name] - test printing\n" "ut setexpr [test-name] - test setexpr command\n" #ifdef CONFIG_SANDBOX "ut str - Basic test of string functions\n" diff --git a/test/print_ut.c b/test/print_ut.c index 5b0a46de9c3..5fabdf84289 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -3,42 +3,49 @@ * Copyright (c) 2012, The Chromium Authors */ -#define DEBUG - #include #include #include #include #include #include +#include +#include +#include #define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \ "and a lot more text to come" -/* Test printing GUIDs */ -static void guid_ut_print(void) -{ +/* Declare a new print test */ +#define PRINT_TEST(_name, _flags) UNIT_TEST(_name, _flags, print_test) + #if CONFIG_IS_ENABLED(LIB_UUID) +/* Test printing GUIDs */ +static int print_guid(struct unit_test_state *uts) +{ unsigned char guid[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 }; char str[40]; sprintf(str, "%pUb", guid); - assert(!strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str)); + ut_assertok(strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str)); sprintf(str, "%pUB", guid); - assert(!strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str)); + ut_assertok(strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str)); sprintf(str, "%pUl", guid); - assert(!strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str)); + ut_assertok(strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str)); sprintf(str, "%pUL", guid); - assert(!strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str)); -#endif -} + ut_assertok(strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str)); + + return 0; +} +PRINT_TEST(print_guid, 0); +#endif -/* Test efi_loader specific printing */ -static void efi_ut_print(void) -{ #if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD) +/* Test efi_loader specific printing */ +static int print_efi_ut(struct unit_test_state *uts) +{ char str[10]; u8 buf[sizeof(struct efi_device_path_sd_mmc_path) + sizeof(struct efi_device_path)]; @@ -60,92 +67,88 @@ static void efi_ut_print(void) dp_end->length = sizeof(struct efi_device_path); snprintf(str, sizeof(str), "_%pD_", buf); - assert(!strcmp("_/SD(3)_", str)); + ut_assertok(strcmp("_/SD(3)_", str)); /* NULL device path */ snprintf(str, sizeof(str), "_%pD_", NULL); - assert(!strcmp("__", str)); -#endif -} + ut_assertok(strcmp("__", str)); -static int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) + return 0; +} +PRINT_TEST(print_efi_ut, 0); +#endif + +static int print_printf(struct unit_test_state *uts) { char big_str[400]; int big_str_len; char str[10], *s; int len; - printf("%s: Testing print\n", __func__); - snprintf(str, sizeof(str), "testing"); - assert(!strcmp("testing", str)); + ut_assertok(strcmp("testing", str)); snprintf(str, sizeof(str), "testing but too long"); - assert(!strcmp("testing b", str)); + ut_assertok(strcmp("testing b", str)); snprintf(str, 1, "testing none"); - assert(!strcmp("", str)); + ut_assertok(strcmp("", str)); *str = 'x'; snprintf(str, 0, "testing none"); - assert(*str == 'x'); + ut_asserteq('x', *str); sprintf(big_str, "_%ls_", L"foo"); - assert(!strcmp("_foo_", big_str)); + ut_assertok(strcmp("_foo_", big_str)); /* Test the banner function */ s = display_options_get_banner(true, str, sizeof(str)); - assert(s == str); - assert(!strcmp("\n\nU-Boo\n\n", s)); + ut_asserteq_ptr(str, s); + ut_assertok(strcmp("\n\nU-Boo\n\n", s)); /* Assert that we do not overwrite memory before the buffer */ str[0] = '`'; s = display_options_get_banner(true, str + 1, 1); - assert(s == str + 1); - assert(!strcmp("`", str)); + ut_asserteq_ptr(str + 1, s); + ut_assertok(strcmp("`", str)); str[0] = '~'; s = display_options_get_banner(true, str + 1, 2); - assert(s == str + 1); - assert(!strcmp("~\n", str)); + ut_asserteq_ptr(str + 1, s); + ut_assertok(strcmp("~\n", str)); /* The last two characters are set to \n\n for all buffer sizes > 2 */ s = display_options_get_banner(false, str, sizeof(str)); - assert(s == str); - assert(!strcmp("U-Boot \n\n", s)); + ut_asserteq_ptr(str, s); + ut_assertok(strcmp("U-Boot \n\n", s)); /* Give it enough space for some of the version */ big_str_len = strlen(version_string) - 5; s = display_options_get_banner_priv(false, FAKE_BUILD_TAG, big_str, big_str_len); - assert(s == big_str); - assert(!strncmp(version_string, s, big_str_len - 3)); - assert(!strcmp("\n\n", s + big_str_len - 3)); + ut_asserteq_ptr(big_str, s); + ut_assertok(strncmp(version_string, s, big_str_len - 3)); + ut_assertok(strcmp("\n\n", s + big_str_len - 3)); /* Give it enough space for the version and some of the build tag */ big_str_len = strlen(version_string) + 9 + 20; s = display_options_get_banner_priv(false, FAKE_BUILD_TAG, big_str, big_str_len); - assert(s == big_str); + ut_asserteq_ptr(big_str, s); len = strlen(version_string); - assert(!strncmp(version_string, s, len)); - assert(!strncmp(", Build: ", s + len, 9)); - assert(!strncmp(FAKE_BUILD_TAG, s + 9 + len, 12)); - assert(!strcmp("\n\n", s + big_str_len - 3)); + ut_assertok(strncmp(version_string, s, len)); + ut_assertok(strncmp(", Build: ", s + len, 9)); + ut_assertok(strncmp(FAKE_BUILD_TAG, s + 9 + len, 12)); + ut_assertok(strcmp("\n\n", s + big_str_len - 3)); - /* Test efi_loader specific printing */ - efi_ut_print(); - - /* Test printing GUIDs */ - guid_ut_print(); - - printf("%s: Everything went swimmingly\n", __func__); return 0; } +PRINT_TEST(print_printf, 0); -U_BOOT_CMD( - ut_print, 1, 1, do_ut_print, - "Very basic test of printf(), etc.", - "" -); +int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(print_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(print_test); + + return cmd_ut_category("print", "print_", tests, n_ents, argc, argv); +} From c614ddf28b064d1de18b97edb6d0f5b91ce70376 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 06:59:59 -0600 Subject: [PATCH 020/250] test: Add a test for print_buffer() Add a test for this function, to cover the various features. Expand the expect_str length to take acount of the ~300-bytes lines generated in one case. Signed-off-by: Simon Glass --- include/test/test.h | 4 +-- test/print_ut.c | 82 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 2 deletions(-) diff --git a/include/test/test.h b/include/test/test.h index bf7d785d8ed..0104e189f63 100644 --- a/include/test/test.h +++ b/include/test/test.h @@ -32,8 +32,8 @@ struct unit_test_state { struct udevice *testdev; int force_fail_alloc; int skip_post_probe; - char expect_str[256]; - char actual_str[256]; + char expect_str[512]; + char actual_str[512]; }; /* Test flags for each test */ diff --git a/test/print_ut.c b/test/print_ut.c index 5fabdf84289..b4dc902d0de 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -8,11 +8,14 @@ #include #include #include +#include #include #include #include #include +#define BUF_SIZE 0x100 + #define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \ "and a lot more text to come" @@ -145,6 +148,85 @@ static int print_printf(struct unit_test_state *uts) } PRINT_TEST(print_printf, 0); +static int print_display_buffer(struct unit_test_state *uts) +{ + u8 *buf; + int i; + + buf = map_sysmem(0, BUF_SIZE); + memset(buf, '\0', BUF_SIZE); + for (i = 0; i < 0x11; i++) + buf[i] = i * 0x11; + + /* bytes */ + console_record_reset(); + print_buffer(0, buf, 1, 0x12, 0); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline("00000010: 10 00 .."); + ut_assert_console_end(); + + /* line length */ + console_record_reset(); + print_buffer(0, buf, 1, 0x12, 8); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw"); + ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........"); + ut_assert_nextline("00000010: 10 00 .."); + ut_assert_console_end(); + + /* long line */ + console_record_reset(); + buf[0x41] = 0x41; + print_buffer(0, buf, 1, 0x42, 0x40); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................"); + ut_assert_nextline("00000040: 00 41 .A"); + ut_assert_console_end(); + + /* address */ + console_record_reset(); + print_buffer(0x12345678, buf, 1, 0x12, 0); + ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline("12345688: 10 00 .."); + ut_assert_console_end(); + + /* 16-bit */ + console_record_reset(); + print_buffer(0, buf, 2, 9, 0); + ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........"); + ut_assert_nextline("00000010: 0010 .."); + ut_assert_console_end(); + + /* 32-bit */ + console_record_reset(); + print_buffer(0, buf, 4, 5, 0); + ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........"); + ut_assert_nextline("00000010: 00000010 ...."); + ut_assert_console_end(); + + /* 64-bit */ + console_record_reset(); + print_buffer(0, buf, 8, 3, 0); + ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........"); + ut_assert_nextline("00000010: 0000000000000010 ........"); + ut_assert_console_end(); + + /* ASCII */ + console_record_reset(); + buf[1] = 31; + buf[2] = 32; + buf[3] = 33; + for (i = 0; i < 4; i++) + buf[4 + i] = 126 + i; + buf[8] = 255; + print_buffer(0, buf, 1, 10, 0); + ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~....."); + ut_assert_console_end(); + + unmap_sysmem(buf); + + return 0; +} +PRINT_TEST(print_display_buffer, UT_TESTF_CONSOLE_REC); + int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct unit_test *tests = UNIT_TEST_SUITE_START(print_test); From c7b16d830e72372a1af54af94f0e83fcc2b1a0fb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:00 -0600 Subject: [PATCH 021/250] display_options: Drop two spaces before the ASCII column At present with print_buffer() U-Boot shows four spaces between the hex and ASCII data. Two seems enough and matches print_hex_dump(). Change it. Signed-off-by: Simon Glass --- lib/display_options.c | 2 +- test/cmd/mem_search.c | 26 +++++++++++++------------- test/dm/rtc.c | 6 +++--- test/print_ut.c | 32 ++++++++++++++++---------------- test/ut.c | 2 +- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/lib/display_options.c b/lib/display_options.c index cd48998b6d4..7752baba2bd 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -189,7 +189,7 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, lb.uc[i] = '.'; } lb.uc[i] = '\0'; - printf(" %s\n", lb.uc); + printf(" %s\n", lb.uc); /* update references */ addr += thislinelen * width; diff --git a/test/cmd/mem_search.c b/test/cmd/mem_search.c index 94942793a49..f80c9c40687 100644 --- a/test/cmd/mem_search.c +++ b/test/cmd/mem_search.c @@ -30,9 +30,9 @@ static int mem_test_ms_b(struct unit_test_state *uts) buf[0x100] = 0x12; ut_assertok(console_record_reset_enable()); run_command("ms.b 1 ff 12", 0); - ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................"); + ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................"); ut_assert_nextline("--"); - ut_assert_nextline("000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ................"); + ut_assert_nextline("000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ................"); ut_assert_nextline("2 matches"); ut_assert_console_end(); @@ -57,7 +57,7 @@ static int mem_test_ms_w(struct unit_test_state *uts) buf[BUF_SIZE / 2] = 0x1234; ut_assertok(console_record_reset_enable()); run_command("ms.w 0 80 1234", 0); - ut_assert_nextline("00000030: 0000 0000 1234 0000 0000 0000 0000 0000 ....4..........."); + ut_assert_nextline("00000030: 0000 0000 1234 0000 0000 0000 0000 0000 ....4..........."); ut_assert_nextline("1 match"); ut_assert_console_end(); @@ -82,7 +82,7 @@ static int mem_test_ms_l(struct unit_test_state *uts) buf[BUF_SIZE / 4] = 0x12345678; ut_assertok(console_record_reset_enable()); run_command("ms 0 40 12345678", 0); - ut_assert_nextline("00000030: 00000000 00000000 12345678 00000000 ........xV4....."); + ut_assert_nextline("00000030: 00000000 00000000 12345678 00000000 ........xV4....."); ut_assert_nextline("1 match"); ut_assert_console_end(); @@ -212,10 +212,10 @@ static int mem_test_ms_mult(struct unit_test_state *uts) strcpy(buf + BUF_SIZE - strlen(str) + 1, str); ut_assertok(console_record_reset_enable()); run_command("ms.b 0 100 68 65 6c 6c 6f", 0); - ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he"); - ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo............."); + ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he"); + ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo............."); ut_assert_nextline("--"); - ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........"); + ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........"); ut_assert_nextline("2 matches"); ut_assert_console_end(); unmap_sysmem(buf); @@ -242,12 +242,12 @@ static int mem_test_ms_s(struct unit_test_state *uts) strcpy(buf + 0xa1, str2); ut_assertok(console_record_reset_enable()); run_command("ms.s 0 100 hello", 0); - ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he"); - ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo............."); + ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he"); + ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo............."); ut_assert_nextline("--"); - ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........"); + ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........"); ut_assert_nextline("--"); - ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere....."); + ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere....."); ut_assert_nextline("3 matches"); ut_assert_console_end(); @@ -257,7 +257,7 @@ static int mem_test_ms_s(struct unit_test_state *uts) ut_assertok(console_record_reset_enable()); run_command("ms.s 0 100 hello there", 0); - ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere....."); + ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere....."); ut_assert_nextline("1 match"); ut_assert_console_end(); @@ -284,7 +284,7 @@ static int mem_test_ms_limit(struct unit_test_state *uts) buf[0x76] = 0x12; ut_assertok(console_record_reset_enable()); run_command("ms.b -l2 1 ff 12", 0); - ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................"); + ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................"); ut_assert_nextline("--"); ut_assert_nextlinen("00000060: 00 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00"); ut_assert_nextline("2 matches (repeat command to check for more)"); diff --git a/test/dm/rtc.c b/test/dm/rtc.c index 8ab997c87d1..c7f9f8f0ce7 100644 --- a/test/dm/rtc.c +++ b/test/dm/rtc.c @@ -204,7 +204,7 @@ static int dm_test_rtc_cmd_rw(struct unit_test_state *uts) ut_assert_console_end(); run_command("rtc read 0x30 2", 0); - ut_assert_nextline("00000030: aa bb .."); + ut_assert_nextline("00000030: aa bb .."); ut_assert_console_end(); run_command("rtc dev 1", 0); @@ -215,7 +215,7 @@ static int dm_test_rtc_cmd_rw(struct unit_test_state *uts) ut_assert_console_end(); run_command("rtc read 0x30 2", 0); - ut_assert_nextline("00000030: cc dd .."); + ut_assert_nextline("00000030: cc dd .."); ut_assert_console_end(); /* @@ -227,7 +227,7 @@ static int dm_test_rtc_cmd_rw(struct unit_test_state *uts) ut_assert_console_end(); run_command("rtc read 0x30 2", 0); - ut_assert_nextline("00000030: aa bb .."); + ut_assert_nextline("00000030: aa bb .."); ut_assert_console_end(); return 0; diff --git a/test/print_ut.c b/test/print_ut.c index b4dc902d0de..9562db6ec3c 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -161,52 +161,52 @@ static int print_display_buffer(struct unit_test_state *uts) /* bytes */ console_record_reset(); print_buffer(0, buf, 1, 0x12, 0); - ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); - ut_assert_nextline("00000010: 10 00 .."); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline("00000010: 10 00 .."); ut_assert_console_end(); /* line length */ console_record_reset(); print_buffer(0, buf, 1, 0x12, 8); - ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw"); - ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........"); - ut_assert_nextline("00000010: 10 00 .."); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw"); + ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........"); + ut_assert_nextline("00000010: 10 00 .."); ut_assert_console_end(); /* long line */ console_record_reset(); buf[0x41] = 0x41; print_buffer(0, buf, 1, 0x42, 0x40); - ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................"); - ut_assert_nextline("00000040: 00 41 .A"); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................"); + ut_assert_nextline("00000040: 00 41 .A"); ut_assert_console_end(); /* address */ console_record_reset(); print_buffer(0x12345678, buf, 1, 0x12, 0); - ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); - ut_assert_nextline("12345688: 10 00 .."); + ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline("12345688: 10 00 .."); ut_assert_console_end(); /* 16-bit */ console_record_reset(); print_buffer(0, buf, 2, 9, 0); - ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........"); - ut_assert_nextline("00000010: 0010 .."); + ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........"); + ut_assert_nextline("00000010: 0010 .."); ut_assert_console_end(); /* 32-bit */ console_record_reset(); print_buffer(0, buf, 4, 5, 0); - ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........"); - ut_assert_nextline("00000010: 00000010 ...."); + ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........"); + ut_assert_nextline("00000010: 00000010 ...."); ut_assert_console_end(); /* 64-bit */ console_record_reset(); print_buffer(0, buf, 8, 3, 0); - ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........"); - ut_assert_nextline("00000010: 0000000000000010 ........"); + ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........"); + ut_assert_nextline("00000010: 0000000000000010 ........"); ut_assert_console_end(); /* ASCII */ @@ -218,7 +218,7 @@ static int print_display_buffer(struct unit_test_state *uts) buf[4 + i] = 126 + i; buf[8] = 255; print_buffer(0, buf, 1, 10, 0); - ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~....."); + ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~....."); ut_assert_console_end(); unmap_sysmem(buf); diff --git a/test/ut.c b/test/ut.c index 350509a2926..1eec2a57dff 100644 --- a/test/ut.c +++ b/test/ut.c @@ -151,7 +151,7 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes) if (str[8] != ':' || str[9] != ' ') return 1; - bytes = len - 8 - 2 - 3 * 16 - 4; + bytes = len - 8 - 2 - 3 * 16 - 2; upto += bytes; } From 2f410fe55766de190bcc2c3dd18245a00aad1d4f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:01 -0600 Subject: [PATCH 022/250] hexdump: Move API to header file Move the comments to the header file so people can find the function info without digging in the implementation. Fix up the code style and add an enum for the first arg. Signed-off-by: Simon Glass --- include/hexdump.h | 75 ++++++++++++++++++++++++++++++++++++++++++++- lib/hexdump.c | 78 ++--------------------------------------------- 2 files changed, 77 insertions(+), 76 deletions(-) diff --git a/include/hexdump.h b/include/hexdump.h index f7b76ff7121..62fce7ae7b4 100644 --- a/include/hexdump.h +++ b/include/hexdump.h @@ -10,7 +10,7 @@ #include #include -enum { +enum dump_prefix_t { DUMP_PREFIX_NONE, DUMP_PREFIX_ADDRESS, DUMP_PREFIX_OFFSET @@ -81,10 +81,83 @@ static inline char *bin2hex(char *dst, const void *src, size_t count) return dst; } +/** + * hex_dump_to_buffer - convert a blob of data to "hex ASCII" in memory + * @buf: data blob to dump + * @len: number of bytes in the @buf + * @rowsize: number of bytes to print per line; must be 16 or 32 + * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) + * @linebuf: where to put the converted data + * @linebuflen: total size of @linebuf, including space for terminating NUL + * @ascii: include ASCII after the hex output + * + * hex_dump_to_buffer() works on one "line" of output at a time, i.e., + * 16 or 32 bytes of input data converted to hex + ASCII output. + * + * Given a buffer of u8 data, hex_dump_to_buffer() converts the input data + * to a hex + ASCII dump at the supplied memory location. + * The converted output is always NUL-terminated. + * + * E.g.: + * hex_dump_to_buffer(frame->data, frame->len, 16, 1, + * linebuf, sizeof(linebuf), true); + * + * example output buffer: + * 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO + * + * Return: + * The amount of bytes placed in the buffer without terminating NUL. If the + * output was truncated, then the return value is the number of bytes + * (excluding the terminating NUL) which would have been written to the final + * string if enough space had been available. + */ int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, char *linebuf, size_t linebuflen, bool ascii); + +/** + * print_hex_dump - print a text hex dump to syslog for a binary blob of data + * @prefix_str: string to prefix each line with; + * caller supplies trailing spaces for alignment if desired + * @prefix_type: controls whether prefix of an offset, address, or none + * is printed (see enum dump_prefix_t) + * @rowsize: number of bytes to print per line; must be 16 or 32 + * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) + * @buf: data blob to dump + * @len: number of bytes in the @buf + * @ascii: include ASCII after the hex output + * + * Given a buffer of u8 data, print_hex_dump() prints a hex + ASCII dump + * to the stdio, with an optional leading prefix. + * + * print_hex_dump() works on one "line" of output at a time, i.e., + * 16 or 32 bytes of input data converted to hex + ASCII output. + * print_hex_dump() iterates over the entire input @buf, breaking it into + * "line size" chunks to format and print. + * + * E.g.: + * print_hex_dump("raw data: ", DUMP_PREFIX_ADDRESS, 16, 1, frame->data, + * frame->len, true); + * + * Example output using %DUMP_PREFIX_OFFSET and 1-byte mode: + * 0009ab42: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO + * Example output using %DUMP_PREFIX_ADDRESS and 4-byte mode: + * ffffffff88089af0: 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~. + */ void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, int groupsize, const void *buf, size_t len, bool ascii); + +/** + * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params + * @prefix_str: string to prefix each line with; + * caller supplies trailing spaces for alignment if desired + * @prefix_type: controls whether prefix of an offset, address, or none + * is printed (see enum dump_prefix_t) + * @buf: data blob to dump + * @len: number of bytes in the @buf + * + * Calls print_hex_dump(), rowsize of 16, groupsize of 1, + * and ASCII output included. + */ void print_hex_dump_bytes(const char *prefix_str, int prefix_type, const void *buf, size_t len); diff --git a/lib/hexdump.c b/lib/hexdump.c index a3f219a8741..e31784cc118 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -19,36 +19,6 @@ const char hex_asc[] = "0123456789abcdef"; const char hex_asc_upper[] = "0123456789ABCDEF"; #if CONFIG_IS_ENABLED(HEXDUMP) -/** - * hex_dump_to_buffer - convert a blob of data to "hex ASCII" in memory - * @buf: data blob to dump - * @len: number of bytes in the @buf - * @rowsize: number of bytes to print per line; must be 16 or 32 - * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) - * @linebuf: where to put the converted data - * @linebuflen: total size of @linebuf, including space for terminating NUL - * @ascii: include ASCII after the hex output - * - * hex_dump_to_buffer() works on one "line" of output at a time, i.e., - * 16 or 32 bytes of input data converted to hex + ASCII output. - * - * Given a buffer of u8 data, hex_dump_to_buffer() converts the input data - * to a hex + ASCII dump at the supplied memory location. - * The converted output is always NUL-terminated. - * - * E.g.: - * hex_dump_to_buffer(frame->data, frame->len, 16, 1, - * linebuf, sizeof(linebuf), true); - * - * example output buffer: - * 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO - * - * Return: - * The amount of bytes placed in the buffer without terminating NUL. If the - * output was truncated, then the return value is the number of bytes - * (excluding the terminating NUL) which would have been written to the final - * string if enough space had been available. - */ int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, char *linebuf, size_t linebuflen, bool ascii) { @@ -150,35 +120,6 @@ overflow1: return ascii ? ascii_column + len : (groupsize * 2 + 1) * ngroups - 1; } -/** - * print_hex_dump - print a text hex dump to syslog for a binary blob of data - * @prefix_str: string to prefix each line with; - * caller supplies trailing spaces for alignment if desired - * @prefix_type: controls whether prefix of an offset, address, or none - * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE) - * @rowsize: number of bytes to print per line; must be 16 or 32 - * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) - * @buf: data blob to dump - * @len: number of bytes in the @buf - * @ascii: include ASCII after the hex output - * - * Given a buffer of u8 data, print_hex_dump() prints a hex + ASCII dump - * to the stdio, with an optional leading prefix. - * - * print_hex_dump() works on one "line" of output at a time, i.e., - * 16 or 32 bytes of input data converted to hex + ASCII output. - * print_hex_dump() iterates over the entire input @buf, breaking it into - * "line size" chunks to format and print. - * - * E.g.: - * print_hex_dump("raw data: ", DUMP_PREFIX_ADDRESS, 16, 1, frame->data, - * frame->len, true); - * - * Example output using %DUMP_PREFIX_OFFSET and 1-byte mode: - * 0009ab42: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO - * Example output using %DUMP_PREFIX_ADDRESS and 4-byte mode: - * ffffffff88089af0: 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~. - */ void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, int groupsize, const void *buf, size_t len, bool ascii) { @@ -210,18 +151,6 @@ void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, } } -/** - * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params - * @prefix_str: string to prefix each line with; - * caller supplies trailing spaces for alignment if desired - * @prefix_type: controls whether prefix of an offset, address, or none - * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE) - * @buf: data blob to dump - * @len: number of bytes in the @buf - * - * Calls print_hex_dump(), rowsize of 16, groupsize of 1, - * and ASCII output included. - */ void print_hex_dump_bytes(const char *prefix_str, int prefix_type, const void *buf, size_t len) { @@ -232,14 +161,13 @@ void print_hex_dump_bytes(const char *prefix_str, int prefix_type, * Some code in U-Boot copy-pasted from Linux kernel uses both * functions below so to keep stuff compilable we keep these stubs here. */ -void print_hex_dump(const char *prefix_str, int prefix_type, - int rowsize, int groupsize, const void *buf, - size_t len, bool ascii) +void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii) { } void print_hex_dump_bytes(const char *prefix_str, int prefix_type, - const void *buf, size_t len) + const void *buf, size_t len) { } #endif /* CONFIG_HEXDUMP */ From 19edf139e900ed61825b32bc7a261e5f6606b8b1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:02 -0600 Subject: [PATCH 023/250] hexdump: Add support for sandbox The current implementation outputs an address as a pointer. Update the code to use an address instead, respecting the 32/64 nature of the CPU. Add some initial tests copied from print_test_display_buffer(), just the ones that can pass with the current implementation. Note that for this case print_hex_dump() and print_bufffer() produce the same result. For now the tests are duplicated sine we have separate functions. Signed-off-by: Simon Glass --- lib/hexdump.c | 5 ++++- test/print_ut.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/lib/hexdump.c b/lib/hexdump.c index e31784cc118..a76ea707b69 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -139,7 +140,9 @@ void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, switch (prefix_type) { case DUMP_PREFIX_ADDRESS: - printf("%s%p: %s\n", prefix_str, ptr + i, linebuf); + printf("%s%0*lx: %s\n", prefix_str, + IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, + (ulong)map_to_sysmem(ptr) + i, linebuf); break; case DUMP_PREFIX_OFFSET: printf("%s%.8x: %s\n", prefix_str, i, linebuf); diff --git a/test/print_ut.c b/test/print_ut.c index 9562db6ec3c..b9c4b1142c2 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -227,6 +227,64 @@ static int print_display_buffer(struct unit_test_state *uts) } PRINT_TEST(print_display_buffer, UT_TESTF_CONSOLE_REC); +static int print_do_hex_dump(struct unit_test_state *uts) +{ + u8 *buf; + int i; + + buf = map_sysmem(0, BUF_SIZE); + memset(buf, '\0', BUF_SIZE); + for (i = 0; i < 0x11; i++) + buf[i] = i * 0x11; + + /* bytes */ + console_record_reset(); + print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS, buf, 0x12); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline("00000010: 10 00 .."); + ut_assert_console_end(); + + /* 16-bit */ + console_record_reset(); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 2, buf, 0x12, true); + ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........"); + ut_assert_nextline("00000010: 0010 .."); + ut_assert_console_end(); + unmap_sysmem(buf); + + /* 32-bit */ + console_record_reset(); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 4, buf, 0x14, true); + ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........"); + ut_assert_nextline("00000010: 00000010 ...."); + ut_assert_console_end(); + unmap_sysmem(buf); + + /* 64-bit */ + console_record_reset(); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 8, buf, 0x18, true); + ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........"); + ut_assert_nextline("00000010: 0000000000000010 ........"); + ut_assert_console_end(); + unmap_sysmem(buf); + + /* ASCII */ + console_record_reset(); + buf[1] = 31; + buf[2] = 32; + buf[3] = 33; + for (i = 0; i < 4; i++) + buf[4 + i] = 126 + i; + buf[8] = 255; + print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 1, buf, 10, true); + ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~....."); + ut_assert_console_end(); + unmap_sysmem(buf); + + return 0; +} +PRINT_TEST(print_do_hex_dump, UT_TESTF_CONSOLE_REC); + int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct unit_test *tests = UNIT_TEST_SUITE_START(print_test); From 5d6d2b88389a99c9e20618593e64a9dd74862c8a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:03 -0600 Subject: [PATCH 024/250] hexdump: Support any rowsize At present print_hex_dump() only supports either 16- or 32-byte lines. With U-Boot we want to support any line length up to a maximum of 64. Update the function to support this, with 0 defaulting to 16, as with print_buffer(). Signed-off-by: Simon Glass --- include/hexdump.h | 4 ++-- lib/hexdump.c | 12 +++++++++--- test/print_ut.c | 23 ++++++++++++++++++++--- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/include/hexdump.h b/include/hexdump.h index 62fce7ae7b4..b75e26025a4 100644 --- a/include/hexdump.h +++ b/include/hexdump.h @@ -85,7 +85,7 @@ static inline char *bin2hex(char *dst, const void *src, size_t count) * hex_dump_to_buffer - convert a blob of data to "hex ASCII" in memory * @buf: data blob to dump * @len: number of bytes in the @buf - * @rowsize: number of bytes to print per line; must be 16 or 32 + * @rowsize: number of bytes to print per line; max 64 * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) * @linebuf: where to put the converted data * @linebuflen: total size of @linebuf, including space for terminating NUL @@ -120,7 +120,7 @@ int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, * caller supplies trailing spaces for alignment if desired * @prefix_type: controls whether prefix of an offset, address, or none * is printed (see enum dump_prefix_t) - * @rowsize: number of bytes to print per line; must be 16 or 32 + * @rowsize: number of bytes to print per line; max 64 * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) * @buf: data blob to dump * @len: number of bytes in the @buf diff --git a/lib/hexdump.c b/lib/hexdump.c index a76ea707b69..a56e108164d 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -16,6 +16,8 @@ #include #include +#define MAX_LINE_LENGTH_BYTES 64 + const char hex_asc[] = "0123456789abcdef"; const char hex_asc_upper[] = "0123456789ABCDEF"; @@ -30,8 +32,10 @@ int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, int ascii_column; int ret; - if (rowsize != 16 && rowsize != 32) + if (!rowsize) rowsize = 16; + else + rowsize = min(rowsize, MAX_LINE_LENGTH_BYTES); if (len > rowsize) /* limit to one line at a time */ len = rowsize; @@ -126,10 +130,12 @@ void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, { const u8 *ptr = buf; int i, linelen, remaining = len; - char linebuf[32 * 3 + 2 + 32 + 1]; + char linebuf[MAX_LINE_LENGTH_BYTES * 3 + 2 + MAX_LINE_LENGTH_BYTES + 1]; - if (rowsize != 16 && rowsize != 32) + if (!rowsize) rowsize = 16; + else + rowsize = min(rowsize, MAX_LINE_LENGTH_BYTES); for (i = 0; i < len; i += rowsize) { linelen = min(remaining, rowsize); diff --git a/test/print_ut.c b/test/print_ut.c index b9c4b1142c2..86b1a5477e8 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -244,9 +244,26 @@ static int print_do_hex_dump(struct unit_test_state *uts) ut_assert_nextline("00000010: 10 00 .."); ut_assert_console_end(); + /* line length */ + console_record_reset(); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 8, 1, buf, 0x12, true); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw"); + ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........"); + ut_assert_nextline("00000010: 10 00 .."); + ut_assert_console_end(); + unmap_sysmem(buf); + + /* long line */ + console_record_reset(); + buf[0x41] = 0x41; + print_hex_dump("", DUMP_PREFIX_ADDRESS, 0x40, 1, buf, 0x42, true); + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................"); + ut_assert_nextline("00000040: 00 41 .A"); + ut_assert_console_end(); + /* 16-bit */ console_record_reset(); - print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 2, buf, 0x12, true); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 2, buf, 0x12, true); ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........"); ut_assert_nextline("00000010: 0010 .."); ut_assert_console_end(); @@ -254,7 +271,7 @@ static int print_do_hex_dump(struct unit_test_state *uts) /* 32-bit */ console_record_reset(); - print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 4, buf, 0x14, true); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 4, buf, 0x14, true); ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........"); ut_assert_nextline("00000010: 00000010 ...."); ut_assert_console_end(); @@ -276,7 +293,7 @@ static int print_do_hex_dump(struct unit_test_state *uts) for (i = 0; i < 4; i++) buf[4 + i] = 126 + i; buf[8] = 255; - print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 1, buf, 10, true); + print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 1, buf, 10, true); ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~....."); ut_assert_console_end(); unmap_sysmem(buf); From 735dd6ef89ebd3e05c1dfaef06aca61046503c63 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:04 -0600 Subject: [PATCH 025/250] hexdump: Allow ctrl-c to interrupt output If a long hexdump is initated the user may wish to interrupt it. Add support for this. Signed-off-by: Simon Glass --- include/hexdump.h | 6 ++++-- lib/hexdump.c | 13 +++++++++---- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/include/hexdump.h b/include/hexdump.h index b75e26025a4..f2ca4793d69 100644 --- a/include/hexdump.h +++ b/include/hexdump.h @@ -125,6 +125,8 @@ int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, * @buf: data blob to dump * @len: number of bytes in the @buf * @ascii: include ASCII after the hex output + * Returns: 0 if finished normally, -EINTR if Ctrl-C was pressed, -ENOSYS if not + * supported * * Given a buffer of u8 data, print_hex_dump() prints a hex + ASCII dump * to the stdio, with an optional leading prefix. @@ -143,8 +145,8 @@ int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, * Example output using %DUMP_PREFIX_ADDRESS and 4-byte mode: * ffffffff88089af0: 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~. */ -void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, - int groupsize, const void *buf, size_t len, bool ascii); +int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii); /** * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params diff --git a/lib/hexdump.c b/lib/hexdump.c index a56e108164d..149c93ead8b 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -125,8 +125,8 @@ overflow1: return ascii ? ascii_column + len : (groupsize * 2 + 1) * ngroups - 1; } -void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, - int groupsize, const void *buf, size_t len, bool ascii) +int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii) { const u8 *ptr = buf; int i, linelen, remaining = len; @@ -157,7 +157,11 @@ void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, printf("%s%s\n", prefix_str, linebuf); break; } + if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) + return -EINTR; } + + return 0; } void print_hex_dump_bytes(const char *prefix_str, int prefix_type, @@ -170,9 +174,10 @@ void print_hex_dump_bytes(const char *prefix_str, int prefix_type, * Some code in U-Boot copy-pasted from Linux kernel uses both * functions below so to keep stuff compilable we keep these stubs here. */ -void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, - int groupsize, const void *buf, size_t len, bool ascii) +int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii) { + return -ENOSYS; } void print_hex_dump_bytes(const char *prefix_str, int prefix_type, From 0cceb99ac59b1d383488ea3ce6511ffc01da5332 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:05 -0600 Subject: [PATCH 026/250] display_options: Split print_buffer() into two functions At present print_buffer() outputs a hex dump but it is not possible to place this dump in a string. Refactor it into a top-level function which does the printing and a utility function that dumps a line into a string. This makes the code more generally useful. Signed-off-by: Simon Glass --- include/display_options.h | 25 +++++++++ lib/display_options.c | 115 +++++++++++++++++++++++--------------- test/print_ut.c | 26 +++++++++ 3 files changed, 121 insertions(+), 45 deletions(-) diff --git a/include/display_options.h b/include/display_options.h index 049688e39e8..43810cbe22f 100644 --- a/include/display_options.h +++ b/include/display_options.h @@ -47,6 +47,31 @@ void print_freq(uint64_t freq, const char *suffix); int print_buffer(ulong addr, const void *data, uint width, uint count, uint linelen); +/* + * Maximum length of an output line is when width == 1 + * 9 for address, + * a space, two hex digits and an ASCII character for each byte + * 2 spaces between the hex and ASCII + * \0 terminator + */ +#define HEXDUMP_MAX_BUF_LENGTH(bytes) (9 + (bytes) * 4 + 3) + +/** + * hexdump_line() - Print out a single line of a hex dump + * + * @addr: Starting address to display at start of line + * @data: pointer to data buffer + * @width: data value width. May be 1, 2, or 4. + * @count: number of values to display + * @linelen: Number of values to print per line; specify 0 for default length + * @out: Output buffer to hold the dump + * @size: Size of output buffer in bytes + * @return number of bytes processed, if OK, -ENOSPC if buffer too small + * + */ +int hexdump_line(ulong addr, const void *data, uint width, uint count, + uint linelen, char *out, int size); + /** * display_options() - display the version string / build tag * diff --git a/lib/display_options.c b/lib/display_options.c index 7752baba2bd..c08a87e3162 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -131,10 +131,11 @@ void print_size(uint64_t size, const char *s) printf (" %ciB%s", c, s); } -#define MAX_LINE_LENGTH_BYTES (64) -#define DEFAULT_LINE_LENGTH_BYTES (16) -int print_buffer(ulong addr, const void *data, uint width, uint count, - uint linelen) +#define MAX_LINE_LENGTH_BYTES 64 +#define DEFAULT_LINE_LENGTH_BYTES 16 + +int hexdump_line(ulong addr, const void *data, uint width, uint count, + uint linelen, char *out, int size) { /* linebuf as a union causes proper alignment */ union linebuf { @@ -143,62 +144,86 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1]; uint8_t uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1]; } lb; + uint thislinelen; int i; ulong x; + if (linelen * width > MAX_LINE_LENGTH_BYTES) + linelen = MAX_LINE_LENGTH_BYTES / width; + if (linelen < 1) + linelen = DEFAULT_LINE_LENGTH_BYTES / width; + + /* + * Check the size here so that we don't need to use snprintf(). This + * helps to reduce code size + */ + if (size < HEXDUMP_MAX_BUF_LENGTH(linelen * width)) + return -ENOSPC; + + thislinelen = linelen; + out += sprintf(out, "%08lx:", addr); + + /* check for overflow condition */ + if (count < thislinelen) + thislinelen = count; + + /* Copy from memory into linebuf and print hex values */ + for (i = 0; i < thislinelen; i++) { + if (width == 4) + x = lb.ui[i] = *(volatile uint32_t *)data; + else if (MEM_SUPPORT_64BIT_DATA && width == 8) + x = lb.uq[i] = *(volatile ulong *)data; + else if (width == 2) + x = lb.us[i] = *(volatile uint16_t *)data; + else + x = lb.uc[i] = *(volatile uint8_t *)data; + if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) + out += sprintf(out, " %x", (uint)x); + else + out += sprintf(out, " %0*lx", width * 2, x); + data += width; + } + + /* fill line with whitespace for nice ASCII print */ + for (i = 0; i < (linelen - thislinelen) * (width * 2 + 1); i++) + *out++ = ' '; + + /* Print data in ASCII characters */ + for (i = 0; i < thislinelen * width; i++) { + if (!isprint(lb.uc[i]) || lb.uc[i] >= 0x80) + lb.uc[i] = '.'; + } + lb.uc[i] = '\0'; + out += sprintf(out, " %s", lb.uc); + + return thislinelen; +} + +int print_buffer(ulong addr, const void *data, uint width, uint count, + uint linelen) +{ if (linelen*width > MAX_LINE_LENGTH_BYTES) linelen = MAX_LINE_LENGTH_BYTES / width; if (linelen < 1) linelen = DEFAULT_LINE_LENGTH_BYTES / width; while (count) { - uint thislinelen = linelen; - printf("%08lx:", addr); + uint thislinelen; + char buf[HEXDUMP_MAX_BUF_LENGTH(width * linelen)]; - /* check for overflow condition */ - if (count < thislinelen) - thislinelen = count; - - /* Copy from memory into linebuf and print hex values */ - for (i = 0; i < thislinelen; i++) { - if (width == 4) - x = lb.ui[i] = *(volatile uint32_t *)data; - else if (MEM_SUPPORT_64BIT_DATA && width == 8) - x = lb.uq[i] = *(volatile ulong *)data; - else if (width == 2) - x = lb.us[i] = *(volatile uint16_t *)data; - else - x = lb.uc[i] = *(volatile uint8_t *)data; - if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) - printf(" %x", (uint)x); - else - printf(" %0*lx", width * 2, x); - data += width; - } - - while (thislinelen < linelen) { - /* fill line with whitespace for nice ASCII print */ - for (i=0; i= 0x80) - lb.uc[i] = '.'; - } - lb.uc[i] = '\0'; - printf(" %s\n", lb.uc); + thislinelen = hexdump_line(addr, data, width, count, linelen, + buf, sizeof(buf)); + assert(thislinelen >= 0); + puts(buf); + putc('\n'); /* update references */ + data += thislinelen * width; addr += thislinelen * width; count -= thislinelen; -#ifndef CONFIG_SPL_BUILD - if (ctrlc()) - return -1; -#endif + if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) + return -EINTR; } return 0; diff --git a/test/print_ut.c b/test/print_ut.c index 86b1a5477e8..e2bcfbef007 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -227,6 +227,32 @@ static int print_display_buffer(struct unit_test_state *uts) } PRINT_TEST(print_display_buffer, UT_TESTF_CONSOLE_REC); +static int print_hexdump_line(struct unit_test_state *uts) +{ + char *linebuf; + u8 *buf; + int i; + + buf = map_sysmem(0, BUF_SIZE); + memset(buf, '\0', BUF_SIZE); + for (i = 0; i < 0x11; i++) + buf[i] = i * 0x11; + + /* Check buffer size calculations */ + linebuf = map_sysmem(0x400, BUF_SIZE); + memset(linebuf, '\xff', BUF_SIZE); + ut_asserteq(-ENOSPC, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 75)); + ut_asserteq(-1, linebuf[0]); + ut_asserteq(0x10, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 76)); + ut_asserteq(0, linebuf[75]); + ut_asserteq(-1, linebuf[76]); + + unmap_sysmem(buf); + + return 0; +} +PRINT_TEST(print_hexdump_line, UT_TESTF_CONSOLE_REC); + static int print_do_hex_dump(struct unit_test_state *uts) { u8 *buf; From 58b4b7133aba6fbb2409a975478157f9277c2e91 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 07:00:06 -0600 Subject: [PATCH 027/250] log: Add support for logging a buffer The print_buffer() function is very useful for debugging. Add a version of this in the log system also. Signed-off-by: Simon Glass --- common/log.c | 30 ++++++++++++++++++++++++++++++ include/log.h | 35 +++++++++++++++++++++++++++++++++++ test/log/log_test.c | 27 +++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) diff --git a/common/log.c b/common/log.c index ea407c6db9e..1aaa6c1527b 100644 --- a/common/log.c +++ b/common/log.c @@ -284,6 +284,36 @@ int _log(enum log_category_t cat, enum log_level_t level, const char *file, return 0; } +#define MAX_LINE_LENGTH_BYTES 64 +#define DEFAULT_LINE_LENGTH_BYTES 16 + +int _log_buffer(enum log_category_t cat, enum log_level_t level, + const char *file, int line, const char *func, ulong addr, + const void *data, uint width, uint count, uint linelen) +{ + if (linelen * width > MAX_LINE_LENGTH_BYTES) + linelen = MAX_LINE_LENGTH_BYTES / width; + if (linelen < 1) + linelen = DEFAULT_LINE_LENGTH_BYTES / width; + + while (count) { + uint thislinelen; + char buf[HEXDUMP_MAX_BUF_LENGTH(width * linelen)]; + + thislinelen = hexdump_line(addr, data, width, count, linelen, + buf, sizeof(buf)); + assert(thislinelen >= 0); + _log(cat, level, file, line, func, "%s\n", buf); + + /* update references */ + data += thislinelen * width; + addr += thislinelen * width; + count -= thislinelen; + } + + return 0; +} + int log_add_filter_flags(const char *drv_name, enum log_category_t cat_list[], enum log_level_t level, const char *file_list, int flags) diff --git a/include/log.h b/include/log.h index add3a1e4a0c..feb0204855a 100644 --- a/include/log.h +++ b/include/log.h @@ -140,6 +140,24 @@ static inline int _log_nop(enum log_category_t cat, enum log_level_t level, return 0; } +/** + * _log_buffer - Internal function to print data buffer in hex and ascii form + * + * @cat: Category of log record (indicating which subsystem generated it) + * @level: Level of log record (indicating its severity) + * @file: File name of file where log record was generated + * @line: Line number in file where log record was generated + * @func: Function where log record was generated + * @addr: Starting address to display at start of line + * @data: pointer to data buffer + * @width: data value width. May be 1, 2, or 4. + * @count: number of values to display + * @linelen: Number of values to print per line; specify 0 for default length + */ +int _log_buffer(enum log_category_t cat, enum log_level_t level, + const char *file, int line, const char *func, ulong addr, + const void *data, uint width, uint count, uint linelen); + /* Define this at the top of a file to add a prefix to debug messages */ #ifndef pr_fmt #define pr_fmt(fmt) fmt @@ -200,8 +218,25 @@ static inline int _log_nop(enum log_category_t cat, enum log_level_t level, __LINE__, __func__, \ pr_fmt(_fmt), ##_args); \ }) + +/* Emit a dump if the level is less that the maximum */ +#define log_buffer(_cat, _level, _addr, _data, _width, _count, _linelen) ({ \ + int _l = _level; \ + if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \ + _log_buffer((enum log_category_t)(_cat), \ + (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \ + __LINE__, __func__, _addr, _data, \ + _width, _count, _linelen); \ + }) #else #define log(_cat, _level, _fmt, _args...) + +#define log_buffer(_cat, _level, _addr, _data, _width, _count, _linelen) ({ \ + int _l = _level; \ + if (_LOG_DEBUG != 0 || _l <= LOGL_INFO || \ + (_DEBUG && _l == LOGL_DEBUG)) \ + print_buffer(_addr, _data, _width, _count, _linelen); \ + }) #endif #define log_nop(_cat, _level, _fmt, _args...) ({ \ diff --git a/test/log/log_test.c b/test/log/log_test.c index 4a814ff4132..f1e67509c17 100644 --- a/test/log/log_test.c +++ b/test/log/log_test.c @@ -429,3 +429,30 @@ int log_test_dropped(struct unit_test_state *uts) return 0; } LOG_TEST_FLAGS(log_test_dropped, UT_TESTF_CONSOLE_REC); + +/* Check log_buffer() */ +int log_test_buffer(struct unit_test_state *uts) +{ + u8 *buf; + int i; + + buf = malloc(0x20); + ut_assertnonnull(buf); + memset(buf, '\0', 0x20); + for (i = 0; i < 0x11; i++) + buf[i] = i * 0x11; + + ut_assertok(console_record_reset_enable()); + log_buffer(LOGC_BOOT, LOGL_INFO, 0, buf, 1, 0x12, 0); + + /* This one should product no output due to the debug level */ + log_buffer(LOGC_BOOT, LOGL_DEBUG, 0, buf, 1, 0x12, 0); + + ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline("00000010: 10 00 .."); + ut_assert_console_end(); + free(buf); + + return 0; +} +LOG_TEST_FLAGS(log_test_buffer, UT_TESTF_CONSOLE_REC); From 8d9bb98f8649222777193c6c161361e1ebd5e3fa Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 13:46:53 -0600 Subject: [PATCH 028/250] sandbox: log: Avoid build error with !CONFIG_LOG The pr_cont_test.c test requires CONFIG_LOG since it directly accesses fields in global_data that require it. Move the test into the CONFIG_LOG condition to avoid build errors. Enable CONFIG_LOG on sandbox (not sandbox_spl, etc.) so that we still run this test. This requires resyncing of the configs. Signed-off-by: Simon Glass --- configs/sandbox_defconfig | 1 + test/log/Makefile | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index bdbf714e2bd..60cdad10848 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_F=y CONFIG_STACKPROTECTOR=y diff --git a/test/log/Makefile b/test/log/Makefile index a3dedace043..09f8689d070 100644 --- a/test/log/Makefile +++ b/test/log/Makefile @@ -17,6 +17,7 @@ endif ifdef CONFIG_LOG obj-y += pr_cont_test.o obj-$(CONFIG_CONSOLE_RECORD) += cont_test.o +obj-y += pr_cont_test.o else obj-$(CONFIG_CONSOLE_RECORD) += nolog_test.o endif From e1cbd916c86cbfdb87a7b2219624057428c285d4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 8 May 2021 13:46:54 -0600 Subject: [PATCH 029/250] log: Convert log values to printf() if not enabled At present if logging not enabled, log_info() becomes a nop. But we want log output at the 'info' level to be akin to printf(). Update the macro to pass the output straight to printf() in this case. This mimics the behaviour for the log_...() macros like log_debug() and log_info(), so we can drop the special case for these. Add new tests to cover this case. Signed-off-by: Simon Glass --- doc/develop/logging.rst | 6 ++++-- include/log.h | 34 +++++++++++++++------------------- test/log/Makefile | 1 + test/log/nolog_ndebug.c | 39 +++++++++++++++++++++++++++++++++++++++ test/log/nolog_test.c | 3 +++ 5 files changed, 62 insertions(+), 21 deletions(-) create mode 100644 test/log/nolog_ndebug.c diff --git a/doc/develop/logging.rst b/doc/develop/logging.rst index f4e925048e8..51095b05ba9 100644 --- a/doc/develop/logging.rst +++ b/doc/develop/logging.rst @@ -52,6 +52,10 @@ If CONFIG_LOG is not set, then no logging will be available. The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and CONFIG_TPL_LOG_MAX_LEVEL. +If logging is disabled, the default behaviour is to output any message at +level LOGL_INFO and below. If logging is disabled and DEBUG is defined (at +the very top of a C file) then any message at LOGL_DEBUG will be written. + Temporary logging within a single file -------------------------------------- @@ -291,8 +295,6 @@ More logging destinations: Convert debug() statements in the code to log() statements -Support making printf() emit log statements at L_INFO level - Convert error() statements in the code to log() statements Figure out what to do with BUG(), BUG_ON() and warn_non_spl() diff --git a/include/log.h b/include/log.h index feb0204855a..e0e12ce1944 100644 --- a/include/log.h +++ b/include/log.h @@ -174,6 +174,10 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, */ #if CONFIG_IS_ENABLED(LOG) #define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL) +#else +#define _LOG_MAX_LEVEL LOGL_INFO +#endif + #define log_emer(_fmt...) log(LOG_CATEGORY, LOGL_EMERG, ##_fmt) #define log_alert(_fmt...) log(LOG_CATEGORY, LOGL_ALERT, ##_fmt) #define log_crit(_fmt...) log(LOG_CATEGORY, LOGL_CRIT, ##_fmt) @@ -185,34 +189,19 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, #define log_content(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_CONTENT, ##_fmt) #define log_io(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt) #define log_cont(_fmt...) log(LOGC_CONT, LOGL_CONT, ##_fmt) -#else -#define _LOG_MAX_LEVEL LOGL_INFO -#define log_emerg(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_alert(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_crit(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_err(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_warning(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_notice(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_info(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_cont(_fmt, ...) printf(_fmt, ##__VA_ARGS__) -#define log_debug(_fmt, ...) debug(_fmt, ##__VA_ARGS__) -#define log_content(_fmt...) log_nop(LOG_CATEGORY, \ - LOGL_DEBUG_CONTENT, ##_fmt) -#define log_io(_fmt...) log_nop(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt) -#endif -#if CONFIG_IS_ENABLED(LOG) #ifdef LOG_DEBUG #define _LOG_DEBUG LOGL_FORCE_DEBUG #else #define _LOG_DEBUG 0 #endif +#if CONFIG_IS_ENABLED(LOG) + /* Emit a log record if the level is less that the maximum */ #define log(_cat, _level, _fmt, _args...) ({ \ int _l = _level; \ - if (CONFIG_IS_ENABLED(LOG) && \ - (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL)) \ + if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \ _log((enum log_category_t)(_cat), \ (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \ __LINE__, __func__, \ @@ -229,7 +218,14 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, _width, _count, _linelen); \ }) #else -#define log(_cat, _level, _fmt, _args...) + +/* Note: _LOG_DEBUG != 0 avoids a warning with clang */ +#define log(_cat, _level, _fmt, _args...) ({ \ + int _l = _level; \ + if (_LOG_DEBUG != 0 || _l <= LOGL_INFO || \ + (_DEBUG && _l == LOGL_DEBUG)) \ + printf(_fmt, ##_args); \ + }) #define log_buffer(_cat, _level, _addr, _data, _width, _count, _linelen) ({ \ int _l = _level; \ diff --git a/test/log/Makefile b/test/log/Makefile index 09f8689d070..08eea70e344 100644 --- a/test/log/Makefile +++ b/test/log/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_CONSOLE_RECORD) += cont_test.o obj-y += pr_cont_test.o else obj-$(CONFIG_CONSOLE_RECORD) += nolog_test.o +obj-$(CONFIG_CONSOLE_RECORD) += nolog_ndebug.o endif endif # CONFIG_UT_LOG diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c new file mode 100644 index 00000000000..bd9a4f408e7 --- /dev/null +++ b/test/log/nolog_ndebug.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + * + * Logging function tests for CONFIG_LOG=n without #define DEBUG + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define BUFFSIZE 32 + +static int log_test_log_disabled_ndebug(struct unit_test_state *uts) +{ + char buf[BUFFSIZE]; + int i; + + memset(buf, 0, BUFFSIZE); + console_record_reset_enable(); + + /* Output a log record at every level */ + for (i = LOGL_EMERG; i < LOGL_COUNT; i++) + log(LOGC_NONE, i, "testing level %i\n", i); + gd->flags &= ~GD_FLG_RECORD; + + /* Since DEBUG is not defined, we expect to not get debug output */ + for (i = LOGL_EMERG; i < LOGL_DEBUG; i++) + ut_assertok(ut_check_console_line(uts, "testing level %d", i)); + ut_assertok(ut_check_console_end(uts)); + + return 0; +} +LOG_TEST(log_test_log_disabled_ndebug); diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c index cb4fb3db9a2..4e52e5bed82 100644 --- a/test/log/nolog_test.c +++ b/test/log/nolog_test.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -128,8 +129,10 @@ static int log_test_nolog_debug(struct unit_test_state *uts) memset(buf, 0, BUFFSIZE); console_record_reset_enable(); log_debug("testing %s\n", "log_debug"); + log(LOGC_NONE, LOGL_DEBUG, "more %s\n", "log_debug"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing log_debug")); + ut_assertok(ut_check_console_line(uts, "more log_debug")); ut_assertok(ut_check_console_end(uts)); return 0; } From 2509493cc1482b2b07ea6fd883960cd6bc068af5 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 12 May 2021 11:03:04 +0300 Subject: [PATCH 030/250] net: convert TFTP_TSIZE to proper Kconfig option TFTP transfer size can be used to re-size the TFTP progress bar on single line based on the server reported file size. The support for this has been around from 2019, but it was never converted to proper Kconfig. While adding this new Kconfig, enable it by default for OMAP2+ and K3 devices also. Signed-off-by: Tero Kristo --- configs/apalis-imx8_defconfig | 1 + configs/apalis-imx8x_defconfig | 1 + configs/apalis-tk1_defconfig | 1 + configs/apalis_t30_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/cherryhill_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/colibri-imx6ull_defconfig | 1 + configs/colibri-imx8x_defconfig | 1 + configs/colibri_t20_defconfig | 1 + configs/colibri_t30_defconfig | 1 + .../conga-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/dfi-bt700-q7x-151_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/galileo_defconfig | 1 + configs/gurnard_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/rpi_0_w_defconfig | 1 + configs/rpi_2_defconfig | 1 + configs/rpi_3_32b_defconfig | 1 + configs/rpi_3_b_plus_defconfig | 1 + configs/rpi_3_defconfig | 1 + configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + configs/rpi_arm64_defconfig | 1 + configs/rpi_defconfig | 1 + configs/slimbootloader_defconfig | 1 + configs/snapper9260_defconfig | 1 + configs/snapper9g20_defconfig | 1 + configs/som-db5800-som-6867_defconfig | 1 + .../theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/theadorable-x86-dfi-bt700_defconfig | 1 + include/configs/apalis-imx8.h | 2 -- include/configs/apalis-imx8x.h | 2 -- include/configs/apalis-tk1.h | 3 --- include/configs/apalis_t30.h | 3 --- include/configs/colibri-imx6ull.h | 3 --- include/configs/colibri-imx8x.h | 3 --- include/configs/colibri_t20.h | 3 --- include/configs/colibri_t30.h | 3 --- include/configs/octeontx2_common.h | 3 --- include/configs/octeontx_common.h | 3 --- include/configs/rpi.h | 4 ---- include/configs/snapper9260.h | 1 - include/configs/snapper9g45.h | 1 - include/configs/x86-common.h | 1 - net/Kconfig | 11 +++++++++++ 64 files changed, 60 insertions(+), 35 deletions(-) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 2a0228262a1..b03a0e2e2dc 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_TFTP_TSIZE=y CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_MXC_GPIO=y diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig index 22a83fe7565..0d225db4365 100644 --- a/configs/apalis-imx8x_defconfig +++ b/configs/apalis-imx8x_defconfig @@ -40,6 +40,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_TFTP_TSIZE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 5da83e9d1fb..7c67306a491 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -38,6 +38,7 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 85f9ce9793b..d23f0572848 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_E1000=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 429de94bd32..95a91353c78 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -47,6 +47,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 01d15eba865..24f992d7b61 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -35,6 +35,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index e43f8783c5d..d785c9ba1a5 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -73,6 +73,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent interrupts linux-name acpi,name acpi,path u-boot,acpi-dsdt-order u-boot,acpi-ssdt-order" CONFIG_ENV_OVERWRITE=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 872e33d7571..e6c6c3816b6 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 60a7640a838..6a69938677f 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -50,6 +50,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 71b5f8bdfea..c839e20dc0a 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -52,6 +52,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 49461db5660..5f11c591007 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -44,6 +44,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CROS_EC=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 6d207daa822..ebf157eeb44 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -58,6 +58,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_TFTP_TSIZE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index fca0093f8f3..eba334bbd0a 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_TFTP_TSIZE=y CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_MXC_GPIO=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 02f40a88e6a..cacd98893bb 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=1536 +CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_MTD=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index d0740585fe7..3707e36d941 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SYS_NS16550=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index fd99d36163e..cc271bde884 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -54,6 +54,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 32df445ad7c..203306d51dc 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -50,6 +50,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index e3cfdbc30b5..84ff12876f9 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -41,6 +41,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_PCI_PNP is not set diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 501a20e7908..992f662acb9 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -36,6 +36,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_PCI_PNP is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index c1d4f9c781b..b771a2a691e 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -39,6 +39,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 397c5a9c93b..0258f310891 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -42,6 +42,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 530477c6aad..268fbfee7b7 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -48,6 +48,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 43e1df75afc..1c3724b3131 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -34,6 +34,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_PCI_PNP is not set diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index a44e1e3b1c2..58a9a2eab9a 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -34,6 +34,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_PCI_PNP is not set diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 75c7b66dd18..60e3c5620b1 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -40,6 +40,7 @@ CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index b63adc65a07..896a3b15088 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -33,6 +33,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_AT91_GPIO=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 696a502c99a..e3c34737489 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -53,6 +53,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 2402a34dbe8..25791910c69 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -72,6 +72,7 @@ CONFIG_USE_ENV_SPI_MODE=y CONFIG_ENV_SPI_MODE=0x0 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 9a34b97ddb0..a1d4ecde85c 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -73,6 +73,7 @@ CONFIG_USE_ENV_SPI_MODE=y CONFIG_ENV_SPI_MODE=0x0 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DM_I2C=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index a63310c18a0..72394a7bb40 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -75,6 +75,7 @@ CONFIG_USE_ENV_SPI_MODE=y CONFIG_ENV_SPI_MODE=0x0 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DM_I2C=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 07c0d3f873a..a82c405b3af 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -72,6 +72,7 @@ CONFIG_USE_ENV_SPI_MODE=y CONFIG_ENV_SPI_MODE=0x0 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DM_I2C=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 4815d8af4e6..6e42fb7e33e 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 218026b739a..6be7ce0c6e6 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index b9ac5fbbce6..ca92645c033 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -21,6 +21,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 2b73619383f..b0aab1bfc53 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -21,6 +21,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index f4fdb455f46..7b1b08cc4d9 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_PHYLIB=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index ccdabcb9ee3..62ef2dd51a4 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_PHYLIB=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 3a8ca5f2e51..a19a42839e2 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_PHYLIB=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 47ea466454f..cfca71cdc1c 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y CONFIG_DFU_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 9cd1477107f..fc200664387 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y CONFIG_DFU_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index aeef34c4de0..84e223790cc 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 5bfb81e02e3..1880f22c5d2 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -21,6 +21,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_TSIZE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index e3c81a5c24b..5cfbaa224fa 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_FAT=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_PCI_PNP is not set diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index a4437c1668c..95fd1bae9c6 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_FAT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_AT91_GPIO=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 63fa8af249d..0e770801ead 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_AT91_GPIO=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 393882d997e..6cf91e08234 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -48,6 +48,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 897d061416e..8c2af20c303 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -52,6 +52,7 @@ CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index a8890eb4e8c..bbeea8defce 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -51,6 +51,7 @@ CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 51aeaafe874..f560d2bbdd1 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -49,6 +49,7 @@ CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 8fe3226cf9d..b04a03f76da 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -21,8 +21,6 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* Networking */ -#define CONFIG_TFTP_TSIZE - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h index fdb0da34ec8..2ad4ca34188 100644 --- a/include/configs/apalis-imx8x.h +++ b/include/configs/apalis-imx8x.h @@ -19,8 +19,6 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_TFTP_TSIZE - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 981f856efaa..57192649ecc 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -25,9 +25,6 @@ /* PCI networking support */ #define CONFIG_E1000_NO_NVM -/* General networking support */ -#define CONFIG_TFTP_TSIZE - /* * Custom Distro Boot configuration: * 1. 8bit SD port (MMC1) diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index f0c003d2fe0..9e5f5236002 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -28,9 +28,6 @@ /* PCI networking support */ #define CONFIG_E1000_NO_NVM -/* General networking support */ -#define CONFIG_TFTP_TSIZE - /* Increase console I/O buffer size */ #undef CONFIG_SYS_CBSIZE #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 22ee2ba03e4..61282441c41 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -18,9 +18,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -/* Network */ -#define CONFIG_TFTP_TSIZE - /* ENET1 */ #define IMX_FEC_BASE ENET2_BASE_ADDR diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 59593f6c00f..cb22b3c75a8 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -21,9 +21,6 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -/* Networking */ -#define CONFIG_TFTP_TSIZE - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 94e17bbb7cc..158bb09b37d 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -17,9 +17,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2 -/* General networking support */ -#define CONFIG_TFTP_TSIZE - /* LCD support */ #define CONFIG_LCD_LOGO diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 94802a66f7a..30b48c5fd6a 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -26,9 +26,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 -/* General networking support */ -#define CONFIG_TFTP_TSIZE - /* Increase console I/O buffer size */ #undef CONFIG_SYS_CBSIZE #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 7c585ad9e21..280089617f1 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -28,9 +28,6 @@ /* Allow environment variable to be overwritten */ #define CONFIG_ENV_OVERWRITE -/** Reduce hashes printed out */ -#define CONFIG_TFTP_TSIZE - /* Autoboot options */ #define CONFIG_RESET_TO_RETRY #define CONFIG_BOOT_RETRY_TIME -1 diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 434e54442fc..0e4a17684f9 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -51,9 +51,6 @@ /* Allow environment variable to be overwritten */ #define CONFIG_ENV_OVERWRITE -/** Reduce hashes printed out */ -#define CONFIG_TFTP_TSIZE - /* Autoboot options */ #define CONFIG_RESET_TO_RETRY #define CONFIG_BOOT_RETRY_TIME -1 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 834f1cd2364..bcfcfff68ba 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -68,10 +68,6 @@ #define CONFIG_LCD_DT_SIMPLEFB #define CONFIG_VIDEO_BCM2835 -#ifdef CONFIG_CMD_USB -#define CONFIG_TFTP_TSIZE -#endif - /* DFU over USB/UDC */ #ifdef CONFIG_CMD_DFU #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index f5f99ee0d24..34a0041617e 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -49,7 +49,6 @@ #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY #define CONFIG_TFTP_PORT -#define CONFIG_TFTP_TSIZE /* USB */ #define CONFIG_USB_ATMEL diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index bbd3b118778..077e9d667a1 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -49,7 +49,6 @@ #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY #define CONFIG_TFTP_PORT -#define CONFIG_TFTP_TSIZE /* MMC */ #define CONFIG_GENERIC_ATMEL_MCI diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f186dd6b823..ab39b0bbbe8 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -76,7 +76,6 @@ * USB configuration */ -#define CONFIG_TFTP_TSIZE #define CONFIG_BOOTP_BOOTFILESIZE /* Default environment */ diff --git a/net/Kconfig b/net/Kconfig index c4b4dae0641..ba0ca813ce5 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -74,6 +74,17 @@ config TFTP_WINDOWSIZE before an ack response is required. The default TFTP implementation implies a window size of 1. +config TFTP_TSIZE + bool "Track TFTP transfers based on file size option" + depends on CMD_TFTPBOOT + default y if (ARCH_OMAP2PLUS || ARCH_K3) + help + By default, TFTP progress bar is increased for each received UDP + frame, which can lead into long time being spent for sending + data over the UART. Enabling this option, TFTP queries the file + size from server, and if supported, limits the progress bar to + 50 characters total which fits on single line. + config SERVERIP_FROM_PROXYDHCP bool "Get serverip value from Proxy DHCP response" help From 8e3ea2da729df07f296611abeabba6cc67333daa Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 1 Jun 2021 16:51:47 +0530 Subject: [PATCH 031/250] usb: dfu: Migrate CONFIG_SYS_DFU_DATA_BUF_SIZE and CONFIG_SYS_DFU_MAX_FILE_SIZE to Kconfig Currently the config options CONFIG_SYS_DFU_DATA_BUF_SIZE and CONFIG_SYS_DFU_MAX_FILE_SIZE are being set in include/configs/.h files and also in _defconfig files without a Kconfig option. It is easier for users to set these configs in defconfig files than in config header files as they are a part of the source code. Add Kconfig symbols, and update the defconfigs by using tools/moveconfig.py script. Suggested-by: Pratyush Yadav Signed-off-by: Aswath Govindraju Acked-by: Oleksandr Suvorov Acked-by: Matthias Brugger Acked-by: Lukasz Majewski --- configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/am65x_hs_evm_a53_defconfig | 2 ++ configs/beaver_defconfig | 2 ++ configs/cei-tk1-som_defconfig | 2 ++ configs/colibri-imx6ull_defconfig | 1 + configs/colibri_vf_defconfig | 1 + configs/corvus_defconfig | 1 + configs/dalmore_defconfig | 2 ++ configs/dh_imx6_defconfig | 1 + configs/draco_defconfig | 1 + configs/etamin_defconfig | 1 + configs/jetson-tk1_defconfig | 2 ++ configs/nyan-big_defconfig | 2 ++ configs/odroid-xu3_defconfig | 1 + configs/odroid_defconfig | 1 + configs/origen_defconfig | 1 + configs/p2371-0000_defconfig | 2 ++ configs/p2371-2180_defconfig | 2 ++ configs/p2571_defconfig | 2 ++ configs/p3450-0000_defconfig | 2 ++ configs/pico-dwarf-imx6ul_defconfig | 1 + configs/pico-hobbit-imx6ul_defconfig | 1 + configs/pico-imx6_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/pico-pi-imx6ul_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rpi_4_32b_defconfig | 2 ++ configs/rpi_4_defconfig | 2 ++ configs/rut_defconfig | 1 + configs/s5p_goni_defconfig | 1 + configs/s5pc210_universal_defconfig | 1 + configs/smartweb_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/taurus_defconfig | 1 + configs/thuban_defconfig | 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + configs/venice2_defconfig | 2 ++ configs/warp7_bl33_defconfig | 1 + configs/warp7_defconfig | 1 + configs/warp_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/dfu/Kconfig | 20 ++++++++++++++++++++ include/configs/am65x_evm.h | 8 -------- include/configs/colibri-imx6ull.h | 1 - include/configs/colibri_vf.h | 1 - include/configs/corvus.h | 1 - include/configs/dh_imx6.h | 1 - include/configs/exynos4-common.h | 1 - include/configs/odroid_xu3.h | 1 - include/configs/pico-imx6.h | 1 - include/configs/pico-imx6ul.h | 1 - include/configs/rpi.h | 3 --- include/configs/s5p_goni.h | 1 - include/configs/siemens-am33x-common.h | 1 - include/configs/smartweb.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/taurus.h | 1 - include/configs/tegra-common-usb-gadget.h | 2 -- include/configs/warp.h | 1 - include/configs/warp7.h | 1 - include/configs/xilinx_versal.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq-common.h | 1 - include/dfu.h | 6 ------ scripts/config_whitelist.txt | 2 -- 81 files changed, 92 insertions(+), 39 deletions(-) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 01e027f607f..7f2b825378f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -90,6 +90,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 16163422251..b45a6d24295 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -65,6 +65,8 @@ CONFIG_BLK=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index ec0c7df0f7e..33526f0cf73 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -85,6 +85,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 4c892443b97..cf18feef407 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -34,6 +34,8 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 987e3ac8e95..c1ff9d7f142 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -34,6 +34,8 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index ebf157eeb44..bec5fd7b311 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -63,6 +63,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 31df3500d95..13399ca839a 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_DFU_NAND=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_VYBRID_GPIO=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_FSL_ESDHC_IMX=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 491f5630822..8206c4cdc98 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -51,6 +51,7 @@ CONFIG_BLK=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index f2c1e849787..fc152121225 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -33,6 +33,8 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index db7d683eb78..934798e094e 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -64,6 +64,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index d48f8082755..e3ccdea5f5e 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -76,6 +76,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y # CONFIG_SPL_DM_MMC is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 3256fd3493e..10534d36b11 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -77,6 +77,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y # CONFIG_SPL_DM_MMC is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 74d315d1435..0e721662164 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -34,6 +34,8 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 3a47c5a0d01..349f918727b 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -51,6 +51,8 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 755a2ca9add..bc71b45c0fb 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -41,6 +41,7 @@ CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y CONFIG_SET_DFU_ALT_INFO=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MTD=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 9f2b0b205d5..36719d91f66 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_SET_DFU_ALT_INFO=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_SYS_I2C_S3C24X0=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 4c4dc1a0db6..650276e379e 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -31,6 +31,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index da3be084be2..97232bb8094 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -28,6 +28,8 @@ CONFIG_SYS_MMC_ENV_PART=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index c7f4404bbac..af490891e2b 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -32,6 +32,8 @@ CONFIG_SYS_MMC_ENV_PART=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 97303409674..68bfb8f28cd 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_MMC_ENV_PART=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index 6e6a8133b4d..12c3f9bb28e 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -33,6 +33,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index ab571b5ddab..3f3c4efbdc5 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -43,6 +43,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index a9c867e1a94..88fdfeca1d5 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 0f27c547553..f0109814339 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 159fb6b6cd7..a54b22f5a53 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 7d9e219c28e..06fa449e38f 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index eb70b6bbf85..8c21890ed72 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -75,6 +75,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y # CONFIG_SPL_DM_MMC is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 63c62a5c074..29ade173f4a 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -76,6 +76,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y # CONFIG_SPL_DM_MMC is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index cfca71cdc1c..e3ccdf7adfb 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -25,6 +25,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index fc200664387..b41d29836df 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -25,6 +25,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index ba3d6377df7..0913388339d 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -75,6 +75,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y # CONFIG_SPL_DM_MMC is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 28d8be6b01f..72f9ce16a95 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -36,6 +36,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_NET is not set CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_DM_I2C_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index 759034a8a5c..734a99f8efa 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_SYS_I2C_S3C24X0=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 1f600d02780..dc7b27742f8 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index d4f9bade3d0..e6e6cb24e15 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index ae7fd501917..ff7aa1df2a4 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index 033c40736ed..70a891b003a 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 53efc9f5bda..35ad9a2ea72 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index d94b9584dea..92d9336f358 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index b24b417a6bc..2e7a9a21e67 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 4ea9b41a7e2..32f20314332 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 16c9b927a9b..756388ee570 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 3984b9bc784..174494c16e5 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_LED_STATUS=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index a79cdf3fa7c..dbd64286241 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -71,6 +71,7 @@ CONFIG_BLK=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index d1cc9a69bec..247538a5d9f 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -76,6 +76,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y # CONFIG_SPL_DM_MMC is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index ec66bb09584..3681919f850 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -38,6 +38,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_I2C=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index e4145948859..301a357ec70 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -38,6 +38,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_I2C=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 0041ee15366..27cd9132e86 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -37,6 +37,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_I2C=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 8439ddc2677..a3955e1ffc5 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -34,6 +34,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_MMC_DW=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 931c69ba6f1..64cd5dcdb3b 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_MMC_DW=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index ca18677dd4c..9c14cef2b99 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -32,6 +32,8 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index c5c5d99c6ca..5452a49061c 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 910419938cd..43471e754a9 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 34acc9e6c84..04f756aacf8 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MXC_UART=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f4e9a80728d..121c3ae7205 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -54,6 +54,7 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_CLK_VERSAL=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_FPGA_XILINX=y CONFIG_FPGA_VERSALPL=y CONFIG_DM_I2C=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 7e56395a521..e53ef2443ec 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -68,6 +68,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_I2C=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index e939b04ef6a..b0cc9d9ba88 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -90,6 +90,7 @@ CONFIG_DFU_NAND=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_DFU_MTD=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 121dc54f546..b50547476cb 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -92,5 +92,25 @@ config SET_DFU_ALT_INFO help This option allows to call the function set_dfu_alt_info to dynamically build dfu_alt_info in board. + +config SYS_DFU_DATA_BUF_SIZE + hex "Size of buffer to be allocated for transfer to raw storage device" + default 0x800000 + help + DFU transfer uses a buffer before writing data to the + raw storage device. This value can be used for setting the + size of this buffer. The size of the buffer is also configurable + through the "dfu_bufsiz" environment variable. If both are + given the size of the buffer is set to "dfu_bufsize". + +config SYS_DFU_MAX_FILE_SIZE + hex "Size of the buffer to be allocated for transferring files" + default SYS_DFU_DATA_BUF_SIZE + help + When updating files rather than the raw storage device, + we use a static buffer to copy the file into and then write + the buffer once we've been given the whole file. Define + this to the maximum filesize (in bytes) for the buffer. + If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE. endif endmenu diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 76d73086fb8..8c50fe9d11f 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -22,7 +22,6 @@ #ifdef CONFIG_TARGET_AM654_A53_EVM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x20000 #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as @@ -45,7 +44,6 @@ /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START 0x84000000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x5000 #endif #ifdef CONFIG_SYS_K3_SPL_ATF @@ -56,12 +54,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* - * If the maximum size is not declared then it is defined as - * CONFIG_SYS_DFU_DATA_BUF_SIZE. - */ -#define CONFIG_SYS_DFU_MAX_FILE_SIZE (1024 * 1024 * 8) /* 8 MiB */ - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #define CONFIG_SYS_BOOTM_LEN SZ_64M diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 61282441c41..2fa34851730 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -140,7 +140,6 @@ #define CONFIG_USBD_HS /* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 #if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index cae7c14bfb9..5bd440f1db3 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -143,6 +143,5 @@ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB DFU */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #endif /* __CONFIG_H */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 55f77e4400a..bd4d6e8e39f 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -81,7 +81,6 @@ #define CONFIG_AT91_WANTS_COMMON_PHY /* DFU class support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #define DFU_MANIFEST_POLL_TIMEOUT 25000 #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 4a469af5e60..d9be1c38c44 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -66,7 +66,6 @@ /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB IDs */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 005f65d4ed6..5e2aca371e7 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -19,7 +19,6 @@ /* SD/MMC configuration */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB Samsung's IDs */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 0c86196152f..fc70dc6a732 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -27,7 +27,6 @@ #define CONFIG_USB_EHCI_EXYNOS /* DFU */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 19c8aeb71b6..6199f0d72e7 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -38,7 +38,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_DFU_ENV_SETTINGS \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 747ef09f37d..04a2531f744 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -49,7 +49,6 @@ #define CONFIG_USBD_HS -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_DFU_ENV_SETTINGS \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index bcfcfff68ba..522b41c02db 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -70,9 +70,6 @@ /* DFU over USB/UDC */ #ifdef CONFIG_CMD_DFU -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M -#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_2M - #ifdef CONFIG_ARM64 #define KERNEL_FILENAME "Image" #else diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 9688bdc4c03..6af6009e612 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -41,7 +41,6 @@ #define CONFIG_PWM 1 /* USB Composite download gadget - g_dnl */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB Samsung's IDs */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index e18af7493c7..f96dd774b17 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -143,7 +143,6 @@ #define CONFIG_USBD_HS /* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 6e715dc0c1b..5e8637e4948 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -122,7 +122,6 @@ #define CONFIG_USB_GADGET_AT91 /* DFU class support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 62b327cd6e5..c5e4292f196 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -148,7 +148,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB IDs */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 39eae8e2ba0..6e869462f1e 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -92,7 +92,6 @@ #define CONFIG_USB_GADGET_AT91 /* DFU class support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h index e6b61c4e8fd..201f4bc093c 100644 --- a/include/configs/tegra-common-usb-gadget.h +++ b/include/configs/tegra-common-usb-gadget.h @@ -13,8 +13,6 @@ #define CONFIG_CI_UDC_HAS_HOSTPC #endif /* DFU protocol */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M -#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M #endif #endif /* _TEGRA_COMMON_USB_GADGET_H_ */ diff --git a/include/configs/warp.h b/include/configs/warp.h index 0f97804eb29..bda8ff9a34f 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -50,7 +50,6 @@ #define CONFIG_USBD_HS -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 /* I2C Configs */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 8eb10602744..a5d52e3977f 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -149,7 +149,6 @@ #define CONFIG_USBD_HS /* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01" diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 380f93a2f68..ebe81968d13 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_MAXARGS 64 #if defined(CONFIG_CMD_DFU) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF #endif diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 986af2be781..cadaf1a9631 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -52,7 +52,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 39035f8bebc..7859b77603f 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -58,7 +58,6 @@ #ifdef CONFIG_USB_EHCI_ZYNQ # define CONFIG_EHCI_IS_TDI -# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 # define DFU_DEFAULT_POLL_TIMEOUT 300 # define CONFIG_THOR_RESET_OFF #endif diff --git a/include/dfu.h b/include/dfu.h index d18b7017282..afada3959b7 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -100,12 +100,6 @@ struct virt_internal_data { }; #define DFU_NAME_SIZE 32 -#ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024*1024*8) /* 8 MiB */ -#endif -#ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE -#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE -#endif #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8f92b82719a..0f5ac8ff522 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1988,8 +1988,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR -CONFIG_SYS_DFU_DATA_BUF_SIZE -CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DIAG_ADDR CONFIG_SYS_DIALOG_PMIC_I2C_ADDR CONFIG_SYS_DIMM_SLOTS_PER_CTLR From dc9f1009b1057e451d66f94dcbc25bc7c64fe67b Mon Sep 17 00:00:00 2001 From: Kevin Scholz Date: Thu, 3 Jun 2021 08:14:53 -0500 Subject: [PATCH 032/250] arm: dts: k3-j7200: ddr: Update to 0.5.0 version of DDR for LPDDR 2666MTs Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 2666MTs LPDDR configuration on J7200. Signed-off-by: Kevin Scholz Signed-off-by: Praneeth Bajjuri Signed-off-by: Lokesh Vutla Tested-by: Suman Anna Link: https://lore.kernel.org/r/20210603131453.11414-1-praneeth@ti.com --- ...00.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} | 437 +++++++++--------- .../arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +- 2 files changed, 220 insertions(+), 219 deletions(-) rename arch/arm/dts/{k3-j7200-ddr-evm-lp4-1600.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} (90%) diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi similarity index 90% rename from arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi rename to arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi index 12ffd913d12..42ac8c5c89c 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi @@ -1,13 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.3.0 - * This file was generated on 06/08/2020 - * Includes hand edits + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0 + * This file was generated on 08/07/2020 + * Includes hand-edits */ #define DDRSS_PLL_FHS_CNT 10 -#define DDRSS_PLL_FREQUENCY_1 400000000 -#define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_PLL_FREQUENCY_1 666500000 +#define DDRSS_PLL_FREQUENCY_2 666500000 #define DDRSS_CTL_00_DATA 0x00000B00 #define DDRSS_CTL_01_DATA 0x00000000 @@ -20,14 +21,14 @@ #define DDRSS_CTL_08_DATA 0x000186A0 #define DDRSS_CTL_09_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x00000064 -#define DDRSS_CTL_11_DATA 0x00027100 -#define DDRSS_CTL_12_DATA 0x00186A00 +#define DDRSS_CTL_11_DATA 0x000411AB +#define DDRSS_CTL_12_DATA 0x0028B0AB #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000640 -#define DDRSS_CTL_15_DATA 0x00027100 -#define DDRSS_CTL_16_DATA 0x00186A00 +#define DDRSS_CTL_14_DATA 0x00000A6B +#define DDRSS_CTL_15_DATA 0x000411AB +#define DDRSS_CTL_16_DATA 0x0028B0AB #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000640 +#define DDRSS_CTL_18_DATA 0x00000A6B #define DDRSS_CTL_19_DATA 0x01010000 #define DDRSS_CTL_20_DATA 0x02011001 #define DDRSS_CTL_21_DATA 0x02010000 @@ -37,66 +38,66 @@ #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 #define DDRSS_CTL_27_DATA 0x02020200 -#define DDRSS_CTL_28_DATA 0x00002020 +#define DDRSS_CTL_28_DATA 0x00003636 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 #define DDRSS_CTL_34_DATA 0x040C0000 -#define DDRSS_CTL_35_DATA 0x081C081C +#define DDRSS_CTL_35_DATA 0x0C300C30 #define DDRSS_CTL_36_DATA 0x00050804 #define DDRSS_CTL_37_DATA 0x09040008 -#define DDRSS_CTL_38_DATA 0x08000204 -#define DDRSS_CTL_39_DATA 0x0B240034 -#define DDRSS_CTL_40_DATA 0x08001910 -#define DDRSS_CTL_41_DATA 0x0B240034 -#define DDRSS_CTL_42_DATA 0x20001910 +#define DDRSS_CTL_38_DATA 0x0D000204 +#define DDRSS_CTL_39_DATA 0x113C0057 +#define DDRSS_CTL_40_DATA 0x0D00291B +#define DDRSS_CTL_41_DATA 0x113C0057 +#define DDRSS_CTL_42_DATA 0x2000291B #define DDRSS_CTL_43_DATA 0x000A0A09 #define DDRSS_CTL_44_DATA 0x040006DB -#define DDRSS_CTL_45_DATA 0x0C0A0904 -#define DDRSS_CTL_46_DATA 0x06006DB0 -#define DDRSS_CTL_47_DATA 0x0C0A0906 -#define DDRSS_CTL_48_DATA 0x06006DB0 -#define DDRSS_CTL_49_DATA 0x02030406 -#define DDRSS_CTL_50_DATA 0x11040500 -#define DDRSS_CTL_51_DATA 0x08121112 +#define DDRSS_CTL_45_DATA 0x130E0B04 +#define DDRSS_CTL_46_DATA 0x0A00B6D0 +#define DDRSS_CTL_47_DATA 0x130E0B0A +#define DDRSS_CTL_48_DATA 0x0A00B6D0 +#define DDRSS_CTL_49_DATA 0x0203040A +#define DDRSS_CTL_50_DATA 0x1C040500 +#define DDRSS_CTL_51_DATA 0x081D1C1D #define DDRSS_CTL_52_DATA 0x14000D0A #define DDRSS_CTL_53_DATA 0x02010A0A #define DDRSS_CTL_54_DATA 0x01010002 -#define DDRSS_CTL_55_DATA 0x04222208 -#define DDRSS_CTL_56_DATA 0x04131304 -#define DDRSS_CTL_57_DATA 0x00001313 +#define DDRSS_CTL_55_DATA 0x04383808 +#define DDRSS_CTL_56_DATA 0x041F1F04 +#define DDRSS_CTL_57_DATA 0x00001F1F #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00000E08 #define DDRSS_CTL_61_DATA 0x000000BB -#define DDRSS_CTL_62_DATA 0x000000E0 -#define DDRSS_CTL_63_DATA 0x00000C28 -#define DDRSS_CTL_64_DATA 0x000000E0 -#define DDRSS_CTL_65_DATA 0x00000C28 +#define DDRSS_CTL_62_DATA 0x00000176 +#define DDRSS_CTL_63_DATA 0x00001448 +#define DDRSS_CTL_64_DATA 0x00000176 +#define DDRSS_CTL_65_DATA 0x00001448 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00030000 -#define DDRSS_CTL_68_DATA 0x00380010 -#define DDRSS_CTL_69_DATA 0x0038017E -#define DDRSS_CTL_70_DATA 0x0040017E +#define DDRSS_CTL_68_DATA 0x005D0010 +#define DDRSS_CTL_69_DATA 0x005D0282 +#define DDRSS_CTL_70_DATA 0x00400282 #define DDRSS_CTL_71_DATA 0x00120103 -#define DDRSS_CTL_72_DATA 0x00060005 -#define DDRSS_CTL_73_DATA 0x14080006 -#define DDRSS_CTL_74_DATA 0x05050114 -#define DDRSS_CTL_75_DATA 0x0201030A -#define DDRSS_CTL_76_DATA 0x030C0605 -#define DDRSS_CTL_77_DATA 0x06050201 -#define DDRSS_CTL_78_DATA 0x0001030C +#define DDRSS_CTL_72_DATA 0x000A0005 +#define DDRSS_CTL_73_DATA 0x1F08000A +#define DDRSS_CTL_74_DATA 0x0505011F +#define DDRSS_CTL_75_DATA 0x0301030A +#define DDRSS_CTL_76_DATA 0x03130A07 +#define DDRSS_CTL_77_DATA 0x0A070301 +#define DDRSS_CTL_78_DATA 0x00010313 #define DDRSS_CTL_79_DATA 0x000F000F -#define DDRSS_CTL_80_DATA 0x00E600E6 -#define DDRSS_CTL_81_DATA 0x00E600E6 +#define DDRSS_CTL_80_DATA 0x01800180 +#define DDRSS_CTL_81_DATA 0x01800180 #define DDRSS_CTL_82_DATA 0x03050505 #define DDRSS_CTL_83_DATA 0x03010303 -#define DDRSS_CTL_84_DATA 0x0C050605 -#define DDRSS_CTL_85_DATA 0x03020603 -#define DDRSS_CTL_86_DATA 0x0C050605 -#define DDRSS_CTL_87_DATA 0x03020603 +#define DDRSS_CTL_84_DATA 0x14070A07 +#define DDRSS_CTL_85_DATA 0x03030A03 +#define DDRSS_CTL_86_DATA 0x14070A07 +#define DDRSS_CTL_87_DATA 0x03030A03 #define DDRSS_CTL_88_DATA 0x03010000 #define DDRSS_CTL_89_DATA 0x00010000 #define DDRSS_CTL_90_DATA 0x00000000 @@ -118,20 +119,20 @@ #define DDRSS_CTL_106_DATA 0x00002EC0 #define DDRSS_CTL_107_DATA 0x00000000 #define DDRSS_CTL_108_DATA 0x0000051D -#define DDRSS_CTL_109_DATA 0x00030A00 -#define DDRSS_CTL_110_DATA 0x00030A00 -#define DDRSS_CTL_111_DATA 0x00030A00 -#define DDRSS_CTL_112_DATA 0x00030A00 -#define DDRSS_CTL_113_DATA 0x00030A00 +#define DDRSS_CTL_109_DATA 0x00051200 +#define DDRSS_CTL_110_DATA 0x00051200 +#define DDRSS_CTL_111_DATA 0x00051200 +#define DDRSS_CTL_112_DATA 0x00051200 +#define DDRSS_CTL_113_DATA 0x00051200 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x00005518 -#define DDRSS_CTL_116_DATA 0x00030A00 -#define DDRSS_CTL_117_DATA 0x00030A00 -#define DDRSS_CTL_118_DATA 0x00030A00 -#define DDRSS_CTL_119_DATA 0x00030A00 -#define DDRSS_CTL_120_DATA 0x00030A00 +#define DDRSS_CTL_115_DATA 0x00008DF8 +#define DDRSS_CTL_116_DATA 0x00051200 +#define DDRSS_CTL_117_DATA 0x00051200 +#define DDRSS_CTL_118_DATA 0x00051200 +#define DDRSS_CTL_119_DATA 0x00051200 +#define DDRSS_CTL_120_DATA 0x00051200 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x00005518 +#define DDRSS_CTL_122_DATA 0x00008DF8 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -140,8 +141,8 @@ #define DDRSS_CTL_128_DATA 0x00000000 #define DDRSS_CTL_129_DATA 0x00000000 #define DDRSS_CTL_130_DATA 0x00000000 -#define DDRSS_CTL_131_DATA 0x05030500 -#define DDRSS_CTL_132_DATA 0x00030503 +#define DDRSS_CTL_131_DATA 0x07030500 +#define DDRSS_CTL_132_DATA 0x00030703 #define DDRSS_CTL_133_DATA 0x0A090000 #define DDRSS_CTL_134_DATA 0x0A090701 #define DDRSS_CTL_135_DATA 0x0900000E @@ -176,23 +177,23 @@ #define DDRSS_CTL_164_DATA 0x000A0000 #define DDRSS_CTL_165_DATA 0x000D0005 #define DDRSS_CTL_166_DATA 0x000D0404 -#define DDRSS_CTL_167_DATA 0x005000A0 -#define DDRSS_CTL_168_DATA 0x060600C8 -#define DDRSS_CTL_169_DATA 0x00A000C8 -#define DDRSS_CTL_170_DATA 0x00C80050 -#define DDRSS_CTL_171_DATA 0x00C80606 +#define DDRSS_CTL_167_DATA 0x0086010B +#define DDRSS_CTL_168_DATA 0x0A0A014E +#define DDRSS_CTL_169_DATA 0x010B014E +#define DDRSS_CTL_170_DATA 0x014E0086 +#define DDRSS_CTL_171_DATA 0x014E0A0A #define DDRSS_CTL_172_DATA 0x00000000 #define DDRSS_CTL_173_DATA 0x00000000 #define DDRSS_CTL_174_DATA 0x00000000 -#define DDRSS_CTL_175_DATA 0x12A40084 -#define DDRSS_CTL_176_DATA 0x2B0012A4 +#define DDRSS_CTL_175_DATA 0x24C40084 +#define DDRSS_CTL_176_DATA 0x2B0024C4 #define DDRSS_CTL_177_DATA 0x00002B2B #define DDRSS_CTL_178_DATA 0x36000000 #define DDRSS_CTL_179_DATA 0x27270036 #define DDRSS_CTL_180_DATA 0x0F0F0000 #define DDRSS_CTL_181_DATA 0x00000000 #define DDRSS_CTL_182_DATA 0x00841515 -#define DDRSS_CTL_183_DATA 0x12A412A4 +#define DDRSS_CTL_183_DATA 0x24C424C4 #define DDRSS_CTL_184_DATA 0x2B2B2B00 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00363600 @@ -270,12 +271,12 @@ #define DDRSS_CTL_258_DATA 0x00320040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 -#define DDRSS_CTL_261_DATA 0x00180320 +#define DDRSS_CTL_261_DATA 0x00280536 #define DDRSS_CTL_262_DATA 0x01000200 -#define DDRSS_CTL_263_DATA 0x03200040 -#define DDRSS_CTL_264_DATA 0x00000018 -#define DDRSS_CTL_265_DATA 0x00280003 -#define DDRSS_CTL_266_DATA 0x01000028 +#define DDRSS_CTL_263_DATA 0x05360040 +#define DDRSS_CTL_264_DATA 0x00000028 +#define DDRSS_CTL_265_DATA 0x00430003 +#define DDRSS_CTL_266_DATA 0x01000043 #define DDRSS_CTL_267_DATA 0x00000000 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 @@ -327,14 +328,14 @@ #define DDRSS_CTL_315_DATA 0x01000101 #define DDRSS_CTL_316_DATA 0x01010001 #define DDRSS_CTL_317_DATA 0x00010101 -#define DDRSS_CTL_318_DATA 0x05050503 -#define DDRSS_CTL_319_DATA 0x08080C0C -#define DDRSS_CTL_320_DATA 0x00090308 -#define DDRSS_CTL_321_DATA 0x000C030F -#define DDRSS_CTL_322_DATA 0x000C0311 -#define DDRSS_CTL_323_DATA 0x0C090011 +#define DDRSS_CTL_318_DATA 0x05070703 +#define DDRSS_CTL_319_DATA 0x0A081414 +#define DDRSS_CTL_320_DATA 0x0009030A +#define DDRSS_CTL_321_DATA 0x080C030F +#define DDRSS_CTL_322_DATA 0x080C0306 +#define DDRSS_CTL_323_DATA 0x0C090006 #define DDRSS_CTL_324_DATA 0x0100000C -#define DDRSS_CTL_325_DATA 0x03020301 +#define DDRSS_CTL_325_DATA 0x05020501 #define DDRSS_CTL_326_DATA 0x00000002 #define DDRSS_CTL_327_DATA 0x00000000 #define DDRSS_CTL_328_DATA 0x00010000 @@ -396,7 +397,7 @@ #define DDRSS_CTL_384_DATA 0x00000000 #define DDRSS_CTL_385_DATA 0x00000000 #define DDRSS_CTL_386_DATA 0x00000000 -#define DDRSS_CTL_387_DATA 0x26261B00 +#define DDRSS_CTL_387_DATA 0x2E2E1B00 #define DDRSS_CTL_388_DATA 0x000A0000 #define DDRSS_CTL_389_DATA 0x00000176 #define DDRSS_CTL_390_DATA 0x00000200 @@ -406,22 +407,22 @@ #define DDRSS_CTL_394_DATA 0x00000462 #define DDRSS_CTL_395_DATA 0x00000E9C #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x00001850 +#define DDRSS_CTL_397_DATA 0x00002890 #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x000048F0 -#define DDRSS_CTL_403_DATA 0x0000F320 -#define DDRSS_CTL_404_DATA 0x00000408 -#define DDRSS_CTL_405_DATA 0x00001850 +#define DDRSS_CTL_402_DATA 0x000079B0 +#define DDRSS_CTL_403_DATA 0x000195A0 +#define DDRSS_CTL_404_DATA 0x0000080E +#define DDRSS_CTL_405_DATA 0x00002890 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x000048F0 -#define DDRSS_CTL_411_DATA 0x0000F320 -#define DDRSS_CTL_412_DATA 0x02020408 +#define DDRSS_CTL_410_DATA 0x000079B0 +#define DDRSS_CTL_411_DATA 0x000195A0 +#define DDRSS_CTL_412_DATA 0x0202080E #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 #define DDRSS_CTL_415_DATA 0x00000000 @@ -432,13 +433,13 @@ #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 #define DDRSS_CTL_422_DATA 0x0006001E -#define DDRSS_CTL_423_DATA 0x000E0026 -#define DDRSS_CTL_424_DATA 0x000E0026 +#define DDRSS_CTL_423_DATA 0x0013002B +#define DDRSS_CTL_424_DATA 0x0013002B #define DDRSS_CTL_425_DATA 0x00000000 #define DDRSS_CTL_426_DATA 0x00000000 #define DDRSS_CTL_427_DATA 0x02000000 #define DDRSS_CTL_428_DATA 0x01000404 -#define DDRSS_CTL_429_DATA 0x01080108 +#define DDRSS_CTL_429_DATA 0x05120512 #define DDRSS_CTL_430_DATA 0x00000105 #define DDRSS_CTL_431_DATA 0x00010101 #define DDRSS_CTL_432_DATA 0x00010101 @@ -447,8 +448,8 @@ #define DDRSS_CTL_435_DATA 0x02000201 #define DDRSS_CTL_436_DATA 0x02010000 #define DDRSS_CTL_437_DATA 0x00000200 -#define DDRSS_CTL_438_DATA 0x10060000 -#define DDRSS_CTL_439_DATA 0x00000110 +#define DDRSS_CTL_438_DATA 0x18060000 +#define DDRSS_CTL_439_DATA 0x00000118 #define DDRSS_CTL_440_DATA 0xFFFFFFFF #define DDRSS_CTL_441_DATA 0xFFFFFFFF #define DDRSS_CTL_442_DATA 0x00000000 @@ -504,10 +505,10 @@ #define DDRSS_PI_32_DATA 0x00000000 #define DDRSS_PI_33_DATA 0x01010102 #define DDRSS_PI_34_DATA 0x00000000 -#define DDRSS_PI_35_DATA 0x000000AA -#define DDRSS_PI_36_DATA 0x00000055 -#define DDRSS_PI_37_DATA 0x000000B5 -#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_35_DATA 0x55555A5A +#define DDRSS_PI_36_DATA 0x5555A5A5 +#define DDRSS_PI_37_DATA 0x00005A5A +#define DDRSS_PI_38_DATA 0x0000A5A5 #define DDRSS_PI_39_DATA 0x00000056 #define DDRSS_PI_40_DATA 0x000000A9 #define DDRSS_PI_41_DATA 0x000000A9 @@ -515,12 +516,12 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x000F0F00 -#define DDRSS_PI_46_DATA 0x00000015 +#define DDRSS_PI_46_DATA 0x00000017 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 #define DDRSS_PI_50_DATA 0x00000000 -#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_51_DATA 0x04080000 #define DDRSS_PI_52_DATA 0x00010101 #define DDRSS_PI_53_DATA 0x00000000 #define DDRSS_PI_54_DATA 0x00030000 @@ -632,18 +633,18 @@ #define DDRSS_PI_160_DATA 0x00000000 #define DDRSS_PI_161_DATA 0x00010000 #define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x10100100 +#define DDRSS_PI_163_DATA 0x1B1B0100 #define DDRSS_PI_164_DATA 0x00000034 -#define DDRSS_PI_165_DATA 0x00000043 -#define DDRSS_PI_166_DATA 0x00020043 +#define DDRSS_PI_165_DATA 0x00000051 +#define DDRSS_PI_166_DATA 0x00020051 #define DDRSS_PI_167_DATA 0x02000200 -#define DDRSS_PI_168_DATA 0x1C080C04 -#define DDRSS_PI_169_DATA 0x000E1C08 +#define DDRSS_PI_168_DATA 0x300C0C04 +#define DDRSS_PI_169_DATA 0x000E300C #define DDRSS_PI_170_DATA 0x000000BB -#define DDRSS_PI_171_DATA 0x000000E0 -#define DDRSS_PI_172_DATA 0x00000C28 -#define DDRSS_PI_173_DATA 0x000000E0 -#define DDRSS_PI_174_DATA 0x04000C28 +#define DDRSS_PI_171_DATA 0x00000176 +#define DDRSS_PI_172_DATA 0x00001448 +#define DDRSS_PI_173_DATA 0x00000176 +#define DDRSS_PI_174_DATA 0x04001448 #define DDRSS_PI_175_DATA 0x01010404 #define DDRSS_PI_176_DATA 0x00001501 #define DDRSS_PI_177_DATA 0x00150015 @@ -652,82 +653,82 @@ #define DDRSS_PI_180_DATA 0x00000000 #define DDRSS_PI_181_DATA 0x01010101 #define DDRSS_PI_182_DATA 0x00000101 -#define DDRSS_PI_183_DATA 0x00000000 -#define DDRSS_PI_184_DATA 0x00000000 -#define DDRSS_PI_185_DATA 0x08040000 -#define DDRSS_PI_186_DATA 0x04040208 +#define DDRSS_PI_183_DATA 0x00000100 +#define DDRSS_PI_184_DATA 0x00000100 +#define DDRSS_PI_185_DATA 0x0E040100 +#define DDRSS_PI_186_DATA 0x0808020E #define DDRSS_PI_187_DATA 0x00040402 #define DDRSS_PI_188_DATA 0x000C8034 -#define DDRSS_PI_189_DATA 0x0014003C -#define DDRSS_PI_190_DATA 0x0014003C +#define DDRSS_PI_189_DATA 0x00198041 +#define DDRSS_PI_190_DATA 0x00198041 #define DDRSS_PI_191_DATA 0x01010101 #define DDRSS_PI_192_DATA 0x0002000D -#define DDRSS_PI_193_DATA 0x000200C8 -#define DDRSS_PI_194_DATA 0x010000C8 +#define DDRSS_PI_193_DATA 0x0002014E +#define DDRSS_PI_194_DATA 0x0100014E #define DDRSS_PI_195_DATA 0x000E000E -#define DDRSS_PI_196_DATA 0x00C90100 -#define DDRSS_PI_197_DATA 0x010000C9 -#define DDRSS_PI_198_DATA 0x00C900C9 +#define DDRSS_PI_196_DATA 0x014F0100 +#define DDRSS_PI_197_DATA 0x0100014F +#define DDRSS_PI_198_DATA 0x014F014F #define DDRSS_PI_199_DATA 0x32103200 #define DDRSS_PI_200_DATA 0x01013210 #define DDRSS_PI_201_DATA 0x0A070601 -#define DDRSS_PI_202_DATA 0x0D09070D -#define DDRSS_PI_203_DATA 0x0D09070D -#define DDRSS_PI_204_DATA 0x0000C00D +#define DDRSS_PI_202_DATA 0x140D080D +#define DDRSS_PI_203_DATA 0x140D0810 +#define DDRSS_PI_204_DATA 0x0000C010 #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x0016000D -#define DDRSS_PI_209_DATA 0x001600C8 -#define DDRSS_PI_210_DATA 0x001100C8 +#define DDRSS_PI_208_DATA 0x001C000D +#define DDRSS_PI_209_DATA 0x001C014E +#define DDRSS_PI_210_DATA 0x0011014E #define DDRSS_PI_211_DATA 0x32000056 #define DDRSS_PI_212_DATA 0x00000301 -#define DDRSS_PI_213_DATA 0x00580020 +#define DDRSS_PI_213_DATA 0x005A002A #define DDRSS_PI_214_DATA 0x03013212 -#define DDRSS_PI_215_DATA 0x00002000 -#define DDRSS_PI_216_DATA 0x32120058 +#define DDRSS_PI_215_DATA 0x00002A00 +#define DDRSS_PI_216_DATA 0x3212005A #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 #define DDRSS_PI_219_DATA 0x0400062B #define DDRSS_PI_220_DATA 0x0A032001 -#define DDRSS_PI_221_DATA 0x1113090A -#define DDRSS_PI_222_DATA 0x0000120C -#define DDRSS_PI_223_DATA 0x240062B8 -#define DDRSS_PI_224_DATA 0x0C0C2003 -#define DDRSS_PI_225_DATA 0x1113090A -#define DDRSS_PI_226_DATA 0x0000120C -#define DDRSS_PI_227_DATA 0x240062B8 -#define DDRSS_PI_228_DATA 0x0C0C2003 -#define DDRSS_PI_229_DATA 0x0001760A +#define DDRSS_PI_221_DATA 0x1C1F0B0A +#define DDRSS_PI_222_DATA 0x00001D12 +#define DDRSS_PI_223_DATA 0x3C00A488 +#define DDRSS_PI_224_DATA 0x13142005 +#define DDRSS_PI_225_DATA 0x1C1F0B0E +#define DDRSS_PI_226_DATA 0x00001D12 +#define DDRSS_PI_227_DATA 0x3C00A488 +#define DDRSS_PI_228_DATA 0x13142005 +#define DDRSS_PI_229_DATA 0x0001760E #define DDRSS_PI_230_DATA 0x00000E9C -#define DDRSS_PI_231_DATA 0x00001850 -#define DDRSS_PI_232_DATA 0x0000F320 -#define DDRSS_PI_233_DATA 0x00001850 -#define DDRSS_PI_234_DATA 0x0000F320 -#define DDRSS_PI_235_DATA 0x00E6000F -#define DDRSS_PI_236_DATA 0x030300E6 +#define DDRSS_PI_231_DATA 0x00002890 +#define DDRSS_PI_232_DATA 0x000195A0 +#define DDRSS_PI_233_DATA 0x00002890 +#define DDRSS_PI_234_DATA 0x000195A0 +#define DDRSS_PI_235_DATA 0x0180000F +#define DDRSS_PI_236_DATA 0x03030180 #define DDRSS_PI_237_DATA 0x00271003 #define DDRSS_PI_238_DATA 0x000186A0 #define DDRSS_PI_239_DATA 0x00000005 #define DDRSS_PI_240_DATA 0x00000064 #define DDRSS_PI_241_DATA 0x0000000F -#define DDRSS_PI_242_DATA 0x00027100 +#define DDRSS_PI_242_DATA 0x000411AB #define DDRSS_PI_243_DATA 0x000186A0 #define DDRSS_PI_244_DATA 0x00000005 -#define DDRSS_PI_245_DATA 0x00000640 -#define DDRSS_PI_246_DATA 0x000000E6 -#define DDRSS_PI_247_DATA 0x00027100 +#define DDRSS_PI_245_DATA 0x00000A6B +#define DDRSS_PI_246_DATA 0x00000180 +#define DDRSS_PI_247_DATA 0x000411AB #define DDRSS_PI_248_DATA 0x000186A0 #define DDRSS_PI_249_DATA 0x00000005 -#define DDRSS_PI_250_DATA 0x00000640 -#define DDRSS_PI_251_DATA 0x010000E6 +#define DDRSS_PI_250_DATA 0x00000A6B +#define DDRSS_PI_251_DATA 0x01000180 #define DDRSS_PI_252_DATA 0x00320040 #define DDRSS_PI_253_DATA 0x00010008 -#define DDRSS_PI_254_DATA 0x03200040 -#define DDRSS_PI_255_DATA 0x00010018 -#define DDRSS_PI_256_DATA 0x03200040 -#define DDRSS_PI_257_DATA 0x00000318 -#define DDRSS_PI_258_DATA 0x00280028 +#define DDRSS_PI_254_DATA 0x05360040 +#define DDRSS_PI_255_DATA 0x00010028 +#define DDRSS_PI_256_DATA 0x05360040 +#define DDRSS_PI_257_DATA 0x00000328 +#define DDRSS_PI_258_DATA 0x00430043 #define DDRSS_PI_259_DATA 0x00040404 #define DDRSS_PI_260_DATA 0x00000055 #define DDRSS_PI_261_DATA 0x55003C5A @@ -746,27 +747,27 @@ #define DDRSS_PI_274_DATA 0x00000000 #define DDRSS_PI_275_DATA 0x002B0084 #define DDRSS_PI_276_DATA 0x00150000 -#define DDRSS_PI_277_DATA 0x362B12A4 +#define DDRSS_PI_277_DATA 0x362B24C4 #define DDRSS_PI_278_DATA 0x00150F27 -#define DDRSS_PI_279_DATA 0x362B12A4 +#define DDRSS_PI_279_DATA 0x362B24C4 #define DDRSS_PI_280_DATA 0x00150F27 #define DDRSS_PI_281_DATA 0x002B0084 #define DDRSS_PI_282_DATA 0x00150000 -#define DDRSS_PI_283_DATA 0x362B12A4 +#define DDRSS_PI_283_DATA 0x362B24C4 #define DDRSS_PI_284_DATA 0x00150F27 -#define DDRSS_PI_285_DATA 0x362B12A4 +#define DDRSS_PI_285_DATA 0x362B24C4 #define DDRSS_PI_286_DATA 0x00150F27 #define DDRSS_PI_287_DATA 0x002B0084 #define DDRSS_PI_288_DATA 0x00150000 -#define DDRSS_PI_289_DATA 0x362B12A4 +#define DDRSS_PI_289_DATA 0x362B24C4 #define DDRSS_PI_290_DATA 0x00150F27 -#define DDRSS_PI_291_DATA 0x362B12A4 +#define DDRSS_PI_291_DATA 0x362B24C4 #define DDRSS_PI_292_DATA 0x00150F27 #define DDRSS_PI_293_DATA 0x002B0084 #define DDRSS_PI_294_DATA 0x00150000 -#define DDRSS_PI_295_DATA 0x362B12A4 +#define DDRSS_PI_295_DATA 0x362B24C4 #define DDRSS_PI_296_DATA 0x00150F27 -#define DDRSS_PI_297_DATA 0x362B12A4 +#define DDRSS_PI_297_DATA 0x362B24C4 #define DDRSS_PI_298_DATA 0x00150F27 #define DDRSS_PI_299_DATA 0x00000000 @@ -788,10 +789,10 @@ #define DDRSS_PHY_15_DATA 0x00030066 #define DDRSS_PHY_16_DATA 0x00000000 #define DDRSS_PHY_17_DATA 0x00000301 -#define DDRSS_PHY_18_DATA 0x0000AAAA -#define DDRSS_PHY_19_DATA 0x00005555 -#define DDRSS_PHY_20_DATA 0x0000B5B5 -#define DDRSS_PHY_21_DATA 0x00004A4A +#define DDRSS_PHY_18_DATA 0x55555A5A +#define DDRSS_PHY_19_DATA 0x5555A5A5 +#define DDRSS_PHY_20_DATA 0x00005A5A +#define DDRSS_PHY_21_DATA 0x0000A5A5 #define DDRSS_PHY_22_DATA 0x00005656 #define DDRSS_PHY_23_DATA 0x0000A9A9 #define DDRSS_PHY_24_DATA 0x0000A9A9 @@ -862,7 +863,7 @@ #define DDRSS_PHY_89_DATA 0x10100303 #define DDRSS_PHY_90_DATA 0x10101010 #define DDRSS_PHY_91_DATA 0x10101010 -#define DDRSS_PHY_92_DATA 0x00011010 +#define DDRSS_PHY_92_DATA 0x00021010 #define DDRSS_PHY_93_DATA 0x00100010 #define DDRSS_PHY_94_DATA 0x00100010 #define DDRSS_PHY_95_DATA 0x00100010 @@ -872,18 +873,18 @@ #define DDRSS_PHY_99_DATA 0x31C06000 #define DDRSS_PHY_100_DATA 0x07AB0340 #define DDRSS_PHY_101_DATA 0x00C0C001 -#define DDRSS_PHY_102_DATA 0x05040001 +#define DDRSS_PHY_102_DATA 0x09080001 #define DDRSS_PHY_103_DATA 0x10001000 -#define DDRSS_PHY_104_DATA 0x0C053E42 -#define DDRSS_PHY_105_DATA 0x0F0C1D01 +#define DDRSS_PHY_104_DATA 0x0C063E42 +#define DDRSS_PHY_105_DATA 0x0F0C2701 #define DDRSS_PHY_106_DATA 0x01000140 -#define DDRSS_PHY_107_DATA 0x0C000420 -#define DDRSS_PHY_108_DATA 0x000001CC +#define DDRSS_PHY_107_DATA 0x04000420 +#define DDRSS_PHY_108_DATA 0x00000255 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 #define DDRSS_PHY_112_DATA 0x80800000 -#define DDRSS_PHY_113_DATA 0x00052010 +#define DDRSS_PHY_113_DATA 0x00092010 #define DDRSS_PHY_114_DATA 0x76543210 #define DDRSS_PHY_115_DATA 0x00000008 #define DDRSS_PHY_116_DATA 0x02800280 @@ -900,8 +901,8 @@ #define DDRSS_PHY_127_DATA 0x00A000A0 #define DDRSS_PHY_128_DATA 0x00A000A0 #define DDRSS_PHY_129_DATA 0x00A000A0 -#define DDRSS_PHY_130_DATA 0x011900A0 -#define DDRSS_PHY_131_DATA 0x01A00002 +#define DDRSS_PHY_130_DATA 0x01C400A0 +#define DDRSS_PHY_131_DATA 0x01A00003 #define DDRSS_PHY_132_DATA 0x00000000 #define DDRSS_PHY_133_DATA 0x00000000 #define DDRSS_PHY_134_DATA 0x00080200 @@ -1044,10 +1045,10 @@ #define DDRSS_PHY_271_DATA 0x00030066 #define DDRSS_PHY_272_DATA 0x00000000 #define DDRSS_PHY_273_DATA 0x00000301 -#define DDRSS_PHY_274_DATA 0x0000AAAA -#define DDRSS_PHY_275_DATA 0x00005555 -#define DDRSS_PHY_276_DATA 0x0000B5B5 -#define DDRSS_PHY_277_DATA 0x00004A4A +#define DDRSS_PHY_274_DATA 0x55555A5A +#define DDRSS_PHY_275_DATA 0x5555A5A5 +#define DDRSS_PHY_276_DATA 0x00005A5A +#define DDRSS_PHY_277_DATA 0x0000A5A5 #define DDRSS_PHY_278_DATA 0x00005656 #define DDRSS_PHY_279_DATA 0x0000A9A9 #define DDRSS_PHY_280_DATA 0x0000A9A9 @@ -1118,7 +1119,7 @@ #define DDRSS_PHY_345_DATA 0x10100303 #define DDRSS_PHY_346_DATA 0x10101010 #define DDRSS_PHY_347_DATA 0x10101010 -#define DDRSS_PHY_348_DATA 0x00011010 +#define DDRSS_PHY_348_DATA 0x00021010 #define DDRSS_PHY_349_DATA 0x00100010 #define DDRSS_PHY_350_DATA 0x00100010 #define DDRSS_PHY_351_DATA 0x00100010 @@ -1128,18 +1129,18 @@ #define DDRSS_PHY_355_DATA 0x31C06000 #define DDRSS_PHY_356_DATA 0x07AB0340 #define DDRSS_PHY_357_DATA 0x00C0C001 -#define DDRSS_PHY_358_DATA 0x05040001 +#define DDRSS_PHY_358_DATA 0x09080001 #define DDRSS_PHY_359_DATA 0x10001000 -#define DDRSS_PHY_360_DATA 0x0C053E42 -#define DDRSS_PHY_361_DATA 0x0F0C1D01 +#define DDRSS_PHY_360_DATA 0x0C063E42 +#define DDRSS_PHY_361_DATA 0x0F0C2701 #define DDRSS_PHY_362_DATA 0x01000140 -#define DDRSS_PHY_363_DATA 0x0C000420 -#define DDRSS_PHY_364_DATA 0x000001CC +#define DDRSS_PHY_363_DATA 0x04000420 +#define DDRSS_PHY_364_DATA 0x00000255 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 #define DDRSS_PHY_368_DATA 0x80800000 -#define DDRSS_PHY_369_DATA 0x00052010 +#define DDRSS_PHY_369_DATA 0x00092010 #define DDRSS_PHY_370_DATA 0x76543210 #define DDRSS_PHY_371_DATA 0x00000008 #define DDRSS_PHY_372_DATA 0x02800280 @@ -1156,8 +1157,8 @@ #define DDRSS_PHY_383_DATA 0x00A000A0 #define DDRSS_PHY_384_DATA 0x00A000A0 #define DDRSS_PHY_385_DATA 0x00A000A0 -#define DDRSS_PHY_386_DATA 0x011900A0 -#define DDRSS_PHY_387_DATA 0x01A00002 +#define DDRSS_PHY_386_DATA 0x01C400A0 +#define DDRSS_PHY_387_DATA 0x01A00003 #define DDRSS_PHY_388_DATA 0x00000000 #define DDRSS_PHY_389_DATA 0x00000000 #define DDRSS_PHY_390_DATA 0x00080200 @@ -1300,10 +1301,10 @@ #define DDRSS_PHY_527_DATA 0x00030066 #define DDRSS_PHY_528_DATA 0x00000000 #define DDRSS_PHY_529_DATA 0x00000301 -#define DDRSS_PHY_530_DATA 0x0000AAAA -#define DDRSS_PHY_531_DATA 0x00005555 -#define DDRSS_PHY_532_DATA 0x0000B5B5 -#define DDRSS_PHY_533_DATA 0x00004A4A +#define DDRSS_PHY_530_DATA 0x55555A5A +#define DDRSS_PHY_531_DATA 0x5555A5A5 +#define DDRSS_PHY_532_DATA 0x00005A5A +#define DDRSS_PHY_533_DATA 0x0000A5A5 #define DDRSS_PHY_534_DATA 0x00005656 #define DDRSS_PHY_535_DATA 0x0000A9A9 #define DDRSS_PHY_536_DATA 0x0000A9A9 @@ -1374,7 +1375,7 @@ #define DDRSS_PHY_601_DATA 0x10100303 #define DDRSS_PHY_602_DATA 0x10101010 #define DDRSS_PHY_603_DATA 0x10101010 -#define DDRSS_PHY_604_DATA 0x00011010 +#define DDRSS_PHY_604_DATA 0x00021010 #define DDRSS_PHY_605_DATA 0x00100010 #define DDRSS_PHY_606_DATA 0x00100010 #define DDRSS_PHY_607_DATA 0x00100010 @@ -1384,18 +1385,18 @@ #define DDRSS_PHY_611_DATA 0x31C06000 #define DDRSS_PHY_612_DATA 0x07AB0340 #define DDRSS_PHY_613_DATA 0x00C0C001 -#define DDRSS_PHY_614_DATA 0x05040001 +#define DDRSS_PHY_614_DATA 0x09080001 #define DDRSS_PHY_615_DATA 0x10001000 -#define DDRSS_PHY_616_DATA 0x0C053E42 -#define DDRSS_PHY_617_DATA 0x0F0C1D01 +#define DDRSS_PHY_616_DATA 0x0C063E42 +#define DDRSS_PHY_617_DATA 0x0F0C2701 #define DDRSS_PHY_618_DATA 0x01000140 -#define DDRSS_PHY_619_DATA 0x0C000420 -#define DDRSS_PHY_620_DATA 0x000001CC +#define DDRSS_PHY_619_DATA 0x04000420 +#define DDRSS_PHY_620_DATA 0x00000255 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 #define DDRSS_PHY_624_DATA 0x80800000 -#define DDRSS_PHY_625_DATA 0x00052010 +#define DDRSS_PHY_625_DATA 0x00092010 #define DDRSS_PHY_626_DATA 0x76543210 #define DDRSS_PHY_627_DATA 0x00000008 #define DDRSS_PHY_628_DATA 0x02800280 @@ -1412,8 +1413,8 @@ #define DDRSS_PHY_639_DATA 0x00A000A0 #define DDRSS_PHY_640_DATA 0x00A000A0 #define DDRSS_PHY_641_DATA 0x00A000A0 -#define DDRSS_PHY_642_DATA 0x011900A0 -#define DDRSS_PHY_643_DATA 0x01A00002 +#define DDRSS_PHY_642_DATA 0x01C400A0 +#define DDRSS_PHY_643_DATA 0x01A00003 #define DDRSS_PHY_644_DATA 0x00000000 #define DDRSS_PHY_645_DATA 0x00000000 #define DDRSS_PHY_646_DATA 0x00080200 @@ -1556,10 +1557,10 @@ #define DDRSS_PHY_783_DATA 0x00030066 #define DDRSS_PHY_784_DATA 0x00000000 #define DDRSS_PHY_785_DATA 0x00000301 -#define DDRSS_PHY_786_DATA 0x0000AAAA -#define DDRSS_PHY_787_DATA 0x00005555 -#define DDRSS_PHY_788_DATA 0x0000B5B5 -#define DDRSS_PHY_789_DATA 0x00004A4A +#define DDRSS_PHY_786_DATA 0x55555A5A +#define DDRSS_PHY_787_DATA 0x5555A5A5 +#define DDRSS_PHY_788_DATA 0x00005A5A +#define DDRSS_PHY_789_DATA 0x0000A5A5 #define DDRSS_PHY_790_DATA 0x00005656 #define DDRSS_PHY_791_DATA 0x0000A9A9 #define DDRSS_PHY_792_DATA 0x0000A9A9 @@ -1630,7 +1631,7 @@ #define DDRSS_PHY_857_DATA 0x10100303 #define DDRSS_PHY_858_DATA 0x10101010 #define DDRSS_PHY_859_DATA 0x10101010 -#define DDRSS_PHY_860_DATA 0x00011010 +#define DDRSS_PHY_860_DATA 0x00021010 #define DDRSS_PHY_861_DATA 0x00100010 #define DDRSS_PHY_862_DATA 0x00100010 #define DDRSS_PHY_863_DATA 0x00100010 @@ -1640,18 +1641,18 @@ #define DDRSS_PHY_867_DATA 0x31C06000 #define DDRSS_PHY_868_DATA 0x07AB0340 #define DDRSS_PHY_869_DATA 0x00C0C001 -#define DDRSS_PHY_870_DATA 0x05040001 +#define DDRSS_PHY_870_DATA 0x09080001 #define DDRSS_PHY_871_DATA 0x10001000 -#define DDRSS_PHY_872_DATA 0x0C053E42 -#define DDRSS_PHY_873_DATA 0x0F0C1D01 +#define DDRSS_PHY_872_DATA 0x0C063E42 +#define DDRSS_PHY_873_DATA 0x0F0C2701 #define DDRSS_PHY_874_DATA 0x01000140 -#define DDRSS_PHY_875_DATA 0x0C000420 -#define DDRSS_PHY_876_DATA 0x000001CC +#define DDRSS_PHY_875_DATA 0x04000420 +#define DDRSS_PHY_876_DATA 0x00000255 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 #define DDRSS_PHY_880_DATA 0x80800000 -#define DDRSS_PHY_881_DATA 0x00052010 +#define DDRSS_PHY_881_DATA 0x00092010 #define DDRSS_PHY_882_DATA 0x76543210 #define DDRSS_PHY_883_DATA 0x00000008 #define DDRSS_PHY_884_DATA 0x02800280 @@ -1668,13 +1669,13 @@ #define DDRSS_PHY_895_DATA 0x00A000A0 #define DDRSS_PHY_896_DATA 0x00A000A0 #define DDRSS_PHY_897_DATA 0x00A000A0 -#define DDRSS_PHY_898_DATA 0x011900A0 -#define DDRSS_PHY_899_DATA 0x01A00002 +#define DDRSS_PHY_898_DATA 0x01C400A0 +#define DDRSS_PHY_899_DATA 0x01A00003 #define DDRSS_PHY_900_DATA 0x00000000 #define DDRSS_PHY_901_DATA 0x00000000 #define DDRSS_PHY_902_DATA 0x00080200 #define DDRSS_PHY_903_DATA 0x00000000 -#define DDRSS_PHY_904_DATA 0x20202010 +#define DDRSS_PHY_904_DATA 0x20202000 #define DDRSS_PHY_905_DATA 0x20202020 #define DDRSS_PHY_906_DATA 0xF0F02020 #define DDRSS_PHY_907_DATA 0x00000000 diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 04914320609..69d8600c19f 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" -#include "k3-j7200-ddr-evm-lp4-1600.dtsi" +#include "k3-j7200-ddr-evm-lp4-2666.dtsi" #include "k3-j721e-ddr.dtsi" / { From 0c51509224302fa83889ef0bf7039e24ddc59ec5 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:31 +0530 Subject: [PATCH 033/250] tools: k3_fit_atf: Add support for providing ATF load address using a Kconfig symbol Add support for providing ATF load address with a Kconfig symbol. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Reviewed-by: Suman Anna Link: https://lore.kernel.org/r/20210604163043.12811-2-a-govindraju@ti.com --- arch/arm/mach-k3/Kconfig | 7 +++++++ arch/arm/mach-k3/config.mk | 1 + tools/k3_fit_atf.sh | 9 ++++++--- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index bfbce44bfa5..21b2fc2230d 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -147,6 +147,13 @@ config SYS_K3_SPL_ATF Enabling this will try to start Cortex-A (typically with ATF) after SPL from R5. +config K3_ATF_LOAD_ADDR + hex "Load address of ATF image" + default 0x70000000 + help + The load address for the ATF image. This value defaults to 0x70000000 + if not provided in the board defconfig file. + source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/j721e/Kconfig" diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index 41fee2b5a17..67448906820 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -67,6 +67,7 @@ endif quiet_cmd_k3_mkits = MKITS $@ cmd_k3_mkits = \ $(srctree)/tools/k3_fit_atf.sh \ + $(CONFIG_K3_ATF_LOAD_ADDR) \ $(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@ $(SPL_ITS): FORCE diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh index 4e9f69c0878..2c0287a6339 100755 --- a/tools/k3_fit_atf.sh +++ b/tools/k3_fit_atf.sh @@ -5,7 +5,7 @@ # ATF, OPTEE, SPL and multiple device trees (given on the command line). # Inspired from board/sunxi/mksunxi_fit_atf.sh # -# usage: $0 [ [ [ [; - entry = <0x70000000>; + load = <$1>; + entry = <$1>; }; tee { description = "OPTEE"; @@ -65,6 +65,9 @@ cat << __HEADER_EOF }; __HEADER_EOF +# shift through ATF load address in the command line arguments +shift + for dtname in $* do cat << __FDT_IMAGE_EOF From 3ae127c4e20649da19fbe7653b0f8fd726ccfcda Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:32 +0530 Subject: [PATCH 034/250] arm: mach-k3: am642_init: Add support for USB boot mode Add support for identifying USB host and device boot modes Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-3-a-govindraju@ti.com --- arch/arm/mach-k3/am642_init.c | 13 +++++++++++-- arch/arm/mach-k3/include/mach/am64_hardware.h | 5 +++++ arch/arm/mach-k3/include/mach/am64_spl.h | 6 ++++-- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index a433702b4e3..1a2bc4bb904 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -192,8 +192,11 @@ static u32 __get_backup_bootmedia(u32 main_devstat) case BACKUP_BOOT_DEVICE_UART: return BOOT_DEVICE_UART; - case BACKUP_BOOT_DEVICE_USB: - return BOOT_DEVICE_USB; + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + case BACKUP_BOOT_DEVICE_ETHERNET: return BOOT_DEVICE_ETHERNET; @@ -245,6 +248,12 @@ static u32 __get_primary_bootmedia(u32 main_devstat) return BOOT_DEVICE_MMC2; return BOOT_DEVICE_MMC1; + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + case BOOT_DEVICE_NOBOOT: return BOOT_DEVICE_RAM; } diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index c368aa7e6bf..4ee41ad762b 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -30,6 +30,11 @@ #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + /* * The CTRL_MMR and PADCFG_MMR memory space is divided into several * equally-spaced partitions, so defining the partition size allows us to diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h index 36826cfc4ed..607b09c2e5d 100644 --- a/arch/arm/mach-k3/include/mach/am64_spl.h +++ b/arch/arm/mach-k3/include/mach/am64_spl.h @@ -19,7 +19,8 @@ #define BOOT_DEVICE_MMC 0x08 #define BOOT_DEVICE_EMMC 0x09 -#define BOOT_DEVICE_USB 0x0A +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A #define BOOT_DEVICE_GPMC_NOR 0x0C #define BOOT_DEVICE_PCIE 0x0D #define BOOT_DEVICE_XSPI 0x0E @@ -32,12 +33,13 @@ #define BOOT_DEVICE_MMC2_2 0x1F /* Backup BootMode devices */ -#define BACKUP_BOOT_DEVICE_USB 0x01 +#define BACKUP_BOOT_DEVICE_DFU 0x01 #define BACKUP_BOOT_DEVICE_UART 0x03 #define BACKUP_BOOT_DEVICE_ETHERNET 0x04 #define BACKUP_BOOT_DEVICE_MMC 0x05 #define BACKUP_BOOT_DEVICE_SPI 0x06 #define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 #define K3_PRIMARY_BOOTMODE 0x0 From 669a03e0ff8bc4c69c848769806125c7ebb5782e Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:33 +0530 Subject: [PATCH 035/250] arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modes U-Boot either supports USB host or device mode for a node at a time in the device tree nodes. To support both host and dfu bootmodes, dr_mode is set to "peripheral" by default and then fixed based on the mode selected by the boot mode config dip switches on the board. This needs to happen before the cdns3 generic layer binds the usb device to a host or a device driver. Therefore, use fdtdec_setup_board() implementation to fixup the device tree property. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-4-a-govindraju@ti.com --- arch/arm/mach-k3/am642_init.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 1a2bc4bb904..579dbacb7e4 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -106,6 +107,38 @@ void do_dt_magic(void) } #endif +#if CONFIG_IS_ENABLED(USB_STORAGE) +static int fixup_usb_boot(const void *fdt_blob) +{ + int ret = 0; + + switch (spl_boot_device()) { + case BOOT_DEVICE_USB: + /* + * If the boot mode is host, fixup the dr_mode to host + * before cdns3 bind takes place + */ + ret = fdt_find_and_setprop((void *)fdt_blob, + "/bus@f4000/cdns-usb@f900000/usb@f400000", + "dr_mode", "host", 5, 0); + if (ret) + printf("%s: fdt_find_and_setprop() failed:%d\n", + __func__, ret); + fallthrough; + default: + break; + } + + return ret; +} + +int fdtdec_board_setup(const void *fdt_blob) +{ + /* Can use the pointer from the function parameters */ + return fixup_usb_boot(fdt_blob); +} +#endif + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) From 397d7b0faea0ddd36f45c63ee728e6e18b3f8673 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:34 +0530 Subject: [PATCH 036/250] board: ti: am64x: Set the core voltage of USB PHY to 0.85V Set the core voltage of USB PHY in AM64x to 0.85V in spl_board_init(). Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-5-a-govindraju@ti.com --- board/ti/am64x/evm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 35cd9e027c0..cdbb9a87bc4 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -152,3 +152,17 @@ int board_late_init(void) return 0; } #endif + +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 +#define CORE_VOLTAGE 0x80000000 + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + u32 val; + /* Set USB PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB0_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB0_PHY_CTRL); +} +#endif From cdb738411facbf7a1b265c9bbaf67c329025aa10 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:35 +0530 Subject: [PATCH 037/250] arm: dts: k3-am64-main: Add USB DT nodes Add DT node for the single USB subsystem in main dtsi file. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-6-a-govindraju@ti.com --- arch/arm/dts/k3-am64-main.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index a65011b396c..5a58337c1ca 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -499,6 +499,36 @@ clock-names = "gpio"; }; + usbss0: cdns-usb@f900000{ + compatible = "ti,am64-usb", "ti,j721e-usb"; + reg = <0x00 0xf900000 0x00 0x100>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + usb0: usb@f400000{ + compatible = "cdns,usb3"; + reg = <0x00 0xf400000 0x00 0x10000>, + <0x00 0xf410000 0x00 0x10000>, + <0x00 0xf420000 0x00 0x10000>; + reg-names = "otg", + "xhci", + "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + main_gpio1: gpio@601000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x00601000 0x00 0x100>; From 7803a5bda96f93466120aa41796fc6bbfe1cc112 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:36 +0530 Subject: [PATCH 038/250] arm: dts: k3-am642-*-evm: Add USB support AM64 EVM board has a micro USB 2.0 AB connector and the USB0_VBUS is connected with a resistor divider in between. USB0_DRVVBUS pin is muxed between USB0_DRVVBUS and GPIO1_79 signals. Add the corresponding properties and set the pinmux mode for USB subsystem in the evm dts file. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-7-a-govindraju@ti.com --- arch/arm/dts/k3-am642-evm.dts | 18 ++++++++++++++++++ arch/arm/dts/k3-am642-r5-evm.dts | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index dc3482bea43..3a505d22c63 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -201,6 +201,12 @@ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ >; }; + + main_usb0_pins_default: main-usb0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; }; &main_uart0 { @@ -337,3 +343,15 @@ ti,driver-strength-ohm = <50>; disable-wp; }; + +&usbss0 { + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; +}; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 1fbf6d2c23a..cc48fd4cb60 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -141,6 +141,12 @@ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; }; + + main_usb0_pins_default: main-usb0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; }; &dmsc { @@ -201,4 +207,16 @@ /delete-property/ power-domains; }; +&usbss0 { + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; +}; + #include "k3-am642-evm-u-boot.dtsi" From 1c8b404b88a5389f9e25b644a42ccaaff433c919 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:37 +0530 Subject: [PATCH 039/250] arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to peripheral for USB subsystem Add U-Boot tags and fix the dr_mode as peripheral in U-Boot to support DFU by default. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-8-a-govindraju@ti.com --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index 10dea7a1cc4..ed38b7269ee 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -50,6 +50,19 @@ u-boot,dm-spl; }; +&usb0 { + dr_mode="peripheral"; + u-boot,dm-spl; +}; + +&usbss0 { + u-boot,dm-spl; +}; + +&main_usb0_pins_default { + u-boot,dm-spl; +}; + &dmss { u-boot,dm-spl; }; From 26f32c32b2506172130255ee2a136d66bc28905c Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:38 +0530 Subject: [PATCH 040/250] configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For USB DFU boot mode there is a limitation on the load address of boot images that they have to be less than 0x70001000. Therefore, move the SPL_TEXT_BASE address to 0x70000000. Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at 0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move the location of ATF to a latter location in SRAM, past the SPL image. Also rearrange the EEPROM and BSS data on top of ATF. Given below is the placement of various data sections in SRAM ┌──────────────────────────────────────┐0x70000000 │ │ │ │ │ │ │ SPL IMAGE (Max size 1.5 MB) │ │ │ │ │ │ │ ├──────────────────────────────────────┤0x7017FFFF │ │ │ SPL STACK │ │ │ ├──────────────────────────────────────┤0x70192727 │ GLOBAL DATA(216 B) │ ├──────────────────────────────────────┤0x701927FF │ │ │ INITIAL HEAP (32 KB) │ │ │ ├──────────────────────────────────────┤0x7019A7FF │ │ │ BSS (20 KB) │ ├──────────────────────────────────────┤0x7019F7FF │ EEPROM DATA (2 KB) │ ├──────────────────────────────────────┤0x7019FFFF │ │ │ │ │ ATF (123 KB) │ │ │ │ │ ├──────────────────────────────────────┤0x701BEBFB │ BOOT PARAMETER INDEX TABLE (5124 B)│ ├──────────────────────────────────────┤0x701BFFFF │ │ │SYSFW FIREWALLED DUE TO A BUG (128 KB)│ │ │ ├──────────────────────────────────────┤0x701DFFFF │ │ │ DMSC CODE AREA (128 KB) │ │ │ └──────────────────────────────────────┘0x701FFFFF Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-9-a-govindraju@ti.com --- arch/arm/mach-k3/include/mach/am64_hardware.h | 6 ++---- configs/am64x_evm_a53_defconfig | 1 + configs/am64x_evm_r5_defconfig | 2 +- include/configs/am64x_evm.h | 3 ++- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 4ee41ad762b..96383437d5b 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -7,8 +7,6 @@ #ifndef __ASM_ARCH_AM64_HARDWARE_H #define __ASM_ARCH_AM64_HARDWARE_H -#include - #define CTRL_MMR0_BASE 0x43000000 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) @@ -54,7 +52,7 @@ #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00 -/* Use Last 1K as Scratch pad */ -#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00 +/* Use Last 2K as Scratch pad */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 249b0dbabf6..8894ac1702d 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM642=y +CONFIG_K3_ATF_LOAD_ADDR=0x701a0000 CONFIG_TARGET_AM642_A53_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 2810fa1fc57..de0c814222c 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_SPL_TEXT_BASE=0x70020000 +CONFIG_SPL_TEXT_BASE=0x70000000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 7c30e50c5f1..7c9bdc2d7d3 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -12,6 +12,7 @@ #include #include #include +#include /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 @@ -43,7 +44,7 @@ * location filled in by the boot ROM that we want to read out without any * interference from the C context. */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ +#define CONFIG_SPL_BSS_START_ADDR (TI_SRAM_SCRATCH_BOARD_EEPROM_START -\ CONFIG_SPL_BSS_MAX_SIZE) /* Set the stack right below the SPL BSS section */ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR From defd62ca137b2c5da6848d27156e03026fb34a80 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:39 +0530 Subject: [PATCH 041/250] arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its max size Due to a limitation for USB DFU boot mode, SPL load address has to be less than or equal to 0x70001000. So, load address of SPL and ATF have been moved to 0x70000000 and 0x701a0000 respectively. Also, the maximum size of ATF has been increased to 0x1c000 [1]. Therefore, update ATF's location and maximum size accordingly in the device tree file. [1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9 Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-10-a-govindraju@ti.com --- arch/arm/dts/k3-am64-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 5a58337c1ca..6b5ebec6b1f 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -14,7 +14,7 @@ ranges = <0x0 0x00 0x70000000 0x200000>; atf-sram@0 { - reg = <0x0 0x1a000>; + reg = <0x1a0000 0x1c000>; }; }; From ce7ad5739054a9b3a766e49e574905590753c329 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 4 Jun 2021 22:00:40 +0530 Subject: [PATCH 042/250] configs: am64: Enable configs to support USB host and device modes Enable config options required to add support for USB Mass storage boot, USB DFU boot, host and device modes in U-Boot. Signed-off-by: Aswath Govindraju Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210604163043.12811-11-a-govindraju@ti.com --- configs/am64x_evm_a53_defconfig | 39 +++++++++++++++++++++++++++++++++ configs/am64x_evm_r5_defconfig | 36 ++++++++++++++++++++++++++++-- include/configs/am64x_evm.h | 12 +++++++++- 3 files changed, 84 insertions(+), 3 deletions(-) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 8894ac1702d..fbce9e96748 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -23,6 +23,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm" CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -30,12 +31,17 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y @@ -102,3 +108,36 @@ CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_USB=y +CONFIG_DFU=y +CONFIG_DFU_OVER_USB=y +# CONFIG_DFU_TFTP is not set +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +# CONFIG_DFU_VIRT is not set +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_TI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index de0c814222c..3e9b5650c60 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm" CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y @@ -31,19 +32,30 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -52,8 +64,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_IS_IN_FAT=y -CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y @@ -64,6 +74,10 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y @@ -101,4 +115,22 @@ CONFIG_CADENCE_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_TI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 7c9bdc2d7d3..c2c2bf06777 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -13,6 +13,7 @@ #include #include #include +#include /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 @@ -95,16 +96,25 @@ "${bootdir}/${name_fit}\0" \ "partitions=" PARTS_DEFAULT +#define EXTRA_ENV_DFUARGS \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_OSPI + /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM642_BOARD_SETTINGS \ - EXTRA_ENV_AM642_BOARD_SETTINGS_MMC + EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \ + EXTRA_ENV_DFUARGS /* Now for the remaining common defines */ #include +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 + /* MMC ENV related defines */ #ifdef CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 From e61a4ff13f36a9952b4ecdfaa209963d411d2884 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 9 Mar 2021 21:19:15 +0100 Subject: [PATCH 043/250] Nokia RX-51: Enable CONFIG_WDT to remove deprecation warning Also convert CONFIG_HW_WATCHDOG to CONFIG_WATCHDOG. Signed-off-by: Pali Roh?r Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210309201915.16586-1-pali@kernel.org --- board/nokia/rx51/rx51.c | 37 ++++++++++++++++++++++++++++++++---- configs/nokia_rx51_defconfig | 2 ++ include/configs/nokia_rx51.h | 3 --- 3 files changed, 35 insertions(+), 7 deletions(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 7bd5fbd7152..fd3cec8358a 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -487,20 +488,20 @@ static unsigned long int twl_wd_time; /* last time of watchdog reset */ static unsigned long int twl_i2c_lock; /* - * Routine: hw_watchdog_reset + * Routine: rx51_watchdog_reset * Description: Reset timeout of twl4030 watchdog. */ -void hw_watchdog_reset(void) +static int rx51_watchdog_reset(struct udevice *dev) { u8 timeout = 0; /* do not reset watchdog too often - max every 4s */ if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ) - return; + return 0; /* localy lock twl4030 i2c bus */ if (test_and_set_bit(0, &twl_i2c_lock)) - return; + return 0; /* read actual watchdog timeout */ twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, @@ -517,8 +518,32 @@ void hw_watchdog_reset(void) /* localy unlock twl4030 i2c bus */ test_and_clear_bit(0, &twl_i2c_lock); + + return 0; } +static int rx51_watchdog_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + return 0; +} + +static int rx51_watchdog_probe(struct udevice *dev) +{ + return 0; +} + +static const struct wdt_ops rx51_watchdog_ops = { + .start = rx51_watchdog_start, + .reset = rx51_watchdog_reset, +}; + +U_BOOT_DRIVER(rx51_watchdog) = { + .name = "rx51_watchdog", + .id = UCLASS_WDT, + .ops = &rx51_watchdog_ops, + .probe = rx51_watchdog_probe, +}; + /* * TWL4030 keypad handler for cfb_console */ @@ -722,3 +747,7 @@ U_BOOT_DRVINFOS(rx51_i2c) = { { "i2c_omap", &rx51_i2c[1] }, { "i2c_omap", &rx51_i2c[2] }, }; + +U_BOOT_DRVINFOS(rx51_watchdog) = { + { "rx51_watchdog" }, +}; diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 3548aab0e16..061f5c357c4 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -67,4 +67,6 @@ CONFIG_CFB_CONSOLE=y CONFIG_CFB_CONSOLE_ANSI=y # CONFIG_VGA_AS_SINGLE_DEVICE is not set CONFIG_SPLASH_SCREEN=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=31000 +CONFIG_WDT=y # CONFIG_GZIP is not set diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 23368de624e..fe991ea0399 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -85,9 +85,6 @@ #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -/* Watchdog support */ -#define CONFIG_HW_WATCHDOG - /* * Framebuffer */ From 73c3d8ebb5d270766b15456e0e18e8b2287a1d01 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:37:58 +0200 Subject: [PATCH 044/250] rtc: davinci: enable compilation for omap architectures The Davinci's onchip RTC is also present on TI OMAP1, AM33XX, AM43XX and DRA7XX SOCs. So, let's enable compilation for these architectures too. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-2-dariobin@libero.it --- drivers/rtc/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index c84a9d2b27b..cbdfddb80f6 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -188,4 +188,11 @@ config RTC_ABX80X families of ultra-low-power battery- and capacitor-backed real-time clock chips. +config RTC_DAVINCI + bool "Enable TI OMAP RTC driver" + depends on ARCH_DAVINCI || ARCH_OMAP2PLUS + help + Say "yes" here to support the on chip real time clock + present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx. + endmenu From 6acee20e57c751b20321c95ed78aa452febf1f7e Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:37:59 +0200 Subject: [PATCH 045/250] rtc: davinci: fix compiler errors Fix errors raised by module compilation. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-3-dariobin@libero.it --- drivers/rtc/davinci.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index c446e7a735f..8f5f76c9d6d 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -9,11 +9,16 @@ #include #include #include +#include #include +#if !defined(RTC_BASE) && defined(DAVINCI_RTC_BASE) +#define RTC_BASE DAVINCI_RTC_BASE +#endif + int rtc_get(struct rtc_time *tmp) { - struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; unsigned long sec, min, hour, mday, wday, mon_cent, year; unsigned long status; @@ -57,7 +62,7 @@ int rtc_get(struct rtc_time *tmp) int rtc_set(struct rtc_time *tmp) { - struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, @@ -75,7 +80,7 @@ int rtc_set(struct rtc_time *tmp) void rtc_reset(void) { - struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; /* run RTC counter */ writel(0x01, &rtc->ctrl); From 82a456a085facede0913a742660df9a1607d1543 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:38:00 +0200 Subject: [PATCH 046/250] rtc: davinci: replace 32bit access with 8bit access Use 32-bit access only where it is needed. Most of the RTC registers contain useful information in the 8 least significant bits, the others are reserved. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-4-dariobin@libero.it --- drivers/rtc/davinci.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 8f5f76c9d6d..99ae31e2a5f 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -22,7 +22,7 @@ int rtc_get(struct rtc_time *tmp) unsigned long sec, min, hour, mday, wday, mon_cent, year; unsigned long status; - status = readl(&rtc->status); + status = readb(&rtc->status); if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) { printf("RTC doesn't run\n"); return -1; @@ -30,13 +30,13 @@ int rtc_get(struct rtc_time *tmp) if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY) udelay(20); - sec = readl(&rtc->second); - min = readl(&rtc->minutes); - hour = readl(&rtc->hours); - mday = readl(&rtc->day); - wday = readl(&rtc->dotw); - mon_cent = readl(&rtc->month); - year = readl(&rtc->year); + sec = readb(&rtc->second); + min = readb(&rtc->minutes); + hour = readb(&rtc->hours); + mday = readb(&rtc->day); + wday = readb(&rtc->dotw); + mon_cent = readb(&rtc->month); + year = readb(&rtc->year); debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx " "hr: %02lx min: %02lx sec: %02lx\n", @@ -67,14 +67,14 @@ int rtc_set(struct rtc_time *tmp) debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - writel(bin2bcd(tmp->tm_year % 100), &rtc->year); - writel(bin2bcd(tmp->tm_mon), &rtc->month); + writeb(bin2bcd(tmp->tm_year % 100), &rtc->year); + writeb(bin2bcd(tmp->tm_mon), &rtc->month); - writel(bin2bcd(tmp->tm_wday), &rtc->dotw); - writel(bin2bcd(tmp->tm_mday), &rtc->day); - writel(bin2bcd(tmp->tm_hour), &rtc->hours); - writel(bin2bcd(tmp->tm_min), &rtc->minutes); - writel(bin2bcd(tmp->tm_sec), &rtc->second); + writeb(bin2bcd(tmp->tm_wday), &rtc->dotw); + writeb(bin2bcd(tmp->tm_mday), &rtc->day); + writeb(bin2bcd(tmp->tm_hour), &rtc->hours); + writeb(bin2bcd(tmp->tm_min), &rtc->minutes); + writeb(bin2bcd(tmp->tm_sec), &rtc->second); return 0; } @@ -83,5 +83,5 @@ void rtc_reset(void) struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; /* run RTC counter */ - writel(0x01, &rtc->ctrl); + writeb(0x01, &rtc->ctrl); } From 79250ef3e263ef23c16c3c06a50834f0dcca4426 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:38:01 +0200 Subject: [PATCH 047/250] rtc: davinci: check BUSY bit before set TC registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To write correct data to the TC registers, the STATUS register must be read until the BUSY bit is equal to zero. Once the BUSY flag is zero, there is a 15 μs access period in which the TC registers can be programmed. The rtc_wait_not_busy() has been inspired by the Kernel. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-5-dariobin@libero.it --- drivers/rtc/davinci.c | 45 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 99ae31e2a5f..7b8c729f3ba 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -16,19 +16,39 @@ #define RTC_BASE DAVINCI_RTC_BASE #endif -int rtc_get(struct rtc_time *tmp) +static int davinci_rtc_wait_not_busy(struct davinci_rtc *rtc) { - struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; - unsigned long sec, min, hour, mday, wday, mon_cent, year; - unsigned long status; + int count; + u8 status; status = readb(&rtc->status); if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) { printf("RTC doesn't run\n"); return -1; } - if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY) - udelay(20); + + /* BUSY may stay active for 1/32768 second (~30 usec) */ + for (count = 0; count < 50; count++) { + if (!(status & RTC_STATE_BUSY)) + break; + + udelay(1); + status = readb(&rtc->status); + } + + /* now we have ~15 usec to read/write various registers */ + return 0; +} + +int rtc_get(struct rtc_time *tmp) +{ + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; + unsigned long sec, min, hour, mday, wday, mon_cent, year; + int ret; + + ret = davinci_rtc_wait_not_busy(rtc); + if (ret) + return ret; sec = readb(&rtc->second); min = readb(&rtc->minutes); @@ -63,10 +83,12 @@ int rtc_get(struct rtc_time *tmp) int rtc_set(struct rtc_time *tmp) { struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; + int ret; + + ret = davinci_rtc_wait_not_busy(rtc); + if (ret) + return ret; - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); writeb(bin2bcd(tmp->tm_year % 100), &rtc->year); writeb(bin2bcd(tmp->tm_mon), &rtc->month); @@ -75,6 +97,11 @@ int rtc_set(struct rtc_time *tmp) writeb(bin2bcd(tmp->tm_hour), &rtc->hours); writeb(bin2bcd(tmp->tm_min), &rtc->minutes); writeb(bin2bcd(tmp->tm_sec), &rtc->second); + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + return 0; } From c7c7c8db00ace48f538f4b51d606cd6e4f537df1 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:38:02 +0200 Subject: [PATCH 048/250] rtc: davinci: use unlock/lock mechanism The RTC module contains a kicker mechanism to prevent any spurious writes from changing the register values. To set the time, you must first unlock the TC registers, update them and then lock. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-6-dariobin@libero.it --- drivers/rtc/davinci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 7b8c729f3ba..82e5eb3b430 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -16,6 +16,18 @@ #define RTC_BASE DAVINCI_RTC_BASE #endif +static void davinci_rtc_lock(struct davinci_rtc *rtc) +{ + writel(0, &rtc->kick0r); + writel(0, &rtc->kick1r); +} + +static void davinci_rtc_unlock(struct davinci_rtc *rtc) +{ + writel(RTC_KICK0R_WE, &rtc->kick0r); + writel(RTC_KICK1R_WE, &rtc->kick1r); +} + static int davinci_rtc_wait_not_busy(struct davinci_rtc *rtc) { int count; @@ -89,6 +101,7 @@ int rtc_set(struct rtc_time *tmp) if (ret) return ret; + davinci_rtc_unlock(rtc); writeb(bin2bcd(tmp->tm_year % 100), &rtc->year); writeb(bin2bcd(tmp->tm_mon), &rtc->month); @@ -97,6 +110,7 @@ int rtc_set(struct rtc_time *tmp) writeb(bin2bcd(tmp->tm_hour), &rtc->hours); writeb(bin2bcd(tmp->tm_min), &rtc->minutes); writeb(bin2bcd(tmp->tm_sec), &rtc->second); + davinci_rtc_lock(rtc); debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, From 62af440e218f96ada507f2067f9f33eca7fa1c87 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:38:03 +0200 Subject: [PATCH 049/250] arm: dts: sync rtc node of am335x boards with Linux 5.9-rc7 There have been some changes to the am335x- DTs related to the rtc node, so let's re-syncs them with Linux. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-7-dariobin@libero.it --- arch/arm/dts/am335x-bone-common.dtsi | 5 +++++ arch/arm/dts/am335x-evm.dts | 5 +++++ arch/arm/dts/am335x-evmsk.dts | 5 +++++ arch/arm/dts/am335x-osd335x-common.dtsi | 6 ++++++ 4 files changed, 21 insertions(+) diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 5b8230e2815..8dcfac3a5b8 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -398,3 +398,8 @@ &sham { status = "okay"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts index 07288fb188b..2a2972f441f 100644 --- a/arch/arm/dts/am335x-evm.dts +++ b/arch/arm/dts/am335x-evm.dts @@ -762,3 +762,8 @@ pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins_default>; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts index c94c33b5957..b14bf2ff1b3 100644 --- a/arch/arm/dts/am335x-evmsk.dts +++ b/arch/arm/dts/am335x-evmsk.dts @@ -724,3 +724,8 @@ &lcdc { status = "okay"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi index f8ff473f94f..2b55b7d0f9c 100644 --- a/arch/arm/dts/am335x-osd335x-common.dtsi +++ b/arch/arm/dts/am335x-osd335x-common.dtsi @@ -122,3 +122,9 @@ &sham { status = "okay"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; + system-power-controller; +}; From 9ec8b8b4ca124278d812b530d11e9e48408ce301 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:38:04 +0200 Subject: [PATCH 050/250] rtc: davinci: add driver model support Update the driver to support the device tree and the driver model. The read / write helpers in rtc_ops allow access to scratch registers only. The offset parameter is added to the address of the scratch0 register. Support for non-DM has been removed as there were no users. Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-8-dariobin@libero.it --- drivers/rtc/davinci.c | 432 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 369 insertions(+), 63 deletions(-) diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 82e5eb3b430..21e52344774 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -2,127 +2,433 @@ /* * (C) Copyright 2011 DENX Software Engineering GmbH * Heiko Schocher + * Copyright (C) 2021 Dario Binacchi */ #include #include +#include +#include #include #include #include -#include -#include +#include #include -#if !defined(RTC_BASE) && defined(DAVINCI_RTC_BASE) -#define RTC_BASE DAVINCI_RTC_BASE -#endif +/* RTC registers */ +#define OMAP_RTC_SECONDS_REG 0x00 +#define OMAP_RTC_MINUTES_REG 0x04 +#define OMAP_RTC_HOURS_REG 0x08 +#define OMAP_RTC_DAYS_REG 0x0C +#define OMAP_RTC_MONTHS_REG 0x10 +#define OMAP_RTC_YEARS_REG 0x14 +#define OMAP_RTC_WEEKS_REG 0x18 -static void davinci_rtc_lock(struct davinci_rtc *rtc) +#define OMAP_RTC_CTRL_REG 0x40 +#define OMAP_RTC_STATUS_REG 0x44 +#define OMAP_RTC_INTERRUPTS_REG 0x48 + +#define OMAP_RTC_OSC_REG 0x54 + +#define OMAP_RTC_SCRATCH0_REG 0x60 +#define OMAP_RTC_SCRATCH1_REG 0x64 +#define OMAP_RTC_SCRATCH2_REG 0x68 + +#define OMAP_RTC_KICK0_REG 0x6c +#define OMAP_RTC_KICK1_REG 0x70 + +#define OMAP_RTC_PMIC_REG 0x98 + +/* OMAP_RTC_CTRL_REG bit fields: */ +#define OMAP_RTC_CTRL_SPLIT BIT(7) +#define OMAP_RTC_CTRL_DISABLE BIT(6) +#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) +#define OMAP_RTC_CTRL_TEST BIT(4) +#define OMAP_RTC_CTRL_MODE_12_24 BIT(3) +#define OMAP_RTC_CTRL_AUTO_COMP BIT(2) +#define OMAP_RTC_CTRL_ROUND_30S BIT(1) +#define OMAP_RTC_CTRL_STOP BIT(0) + +/* OMAP_RTC_STATUS_REG bit fields */ +#define OMAP_RTC_STATUS_POWER_UP BIT(7) +#define OMAP_RTC_STATUS_ALARM2 BIT(7) +#define OMAP_RTC_STATUS_ALARM BIT(6) +#define OMAP_RTC_STATUS_1D_EVENT BIT(5) +#define OMAP_RTC_STATUS_1H_EVENT BIT(4) +#define OMAP_RTC_STATUS_1M_EVENT BIT(3) +#define OMAP_RTC_STATUS_1S_EVENT BIT(2) +#define OMAP_RTC_STATUS_RUN BIT(1) +#define OMAP_RTC_STATUS_BUSY BIT(0) + +/* OMAP_RTC_OSC_REG bit fields */ +#define OMAP_RTC_OSC_32KCLK_EN BIT(6) +#define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) +#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) + +/* OMAP_RTC_KICKER values */ +#define OMAP_RTC_KICK0_VALUE 0x83e70b13 +#define OMAP_RTC_KICK1_VALUE 0x95a4f1e0 + +struct omap_rtc_device_type { + bool has_32kclk_en; + bool has_irqwakeen; + bool has_pmic_mode; + bool has_power_up_reset; +}; + +struct omap_rtc_priv { + fdt_addr_t base; + u8 max_reg; + struct udevice *dev; + struct clk clk; + bool has_ext_clk; + const struct omap_rtc_device_type *type; +}; + +static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg) { - writel(0, &rtc->kick0r); - writel(0, &rtc->kick1r); + return readb(priv->base + reg); } -static void davinci_rtc_unlock(struct davinci_rtc *rtc) +static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg) { - writel(RTC_KICK0R_WE, &rtc->kick0r); - writel(RTC_KICK1R_WE, &rtc->kick1r); + return readl(priv->base + reg); } -static int davinci_rtc_wait_not_busy(struct davinci_rtc *rtc) +static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg, + u8 val) +{ + writeb(val, priv->base + reg); +} + +static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg, + u32 val) +{ + writel(val, priv->base + reg); +} + +static inline void omap_rtc_unlock(struct omap_rtc_priv *priv) +{ + omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE); + omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE); +} + +static inline void omap_rtc_lock(struct omap_rtc_priv *priv) +{ + omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0); + omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0); +} + +static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv) { int count; u8 status; - status = readb(&rtc->status); - if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) { + status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG); + if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) { printf("RTC doesn't run\n"); return -1; } /* BUSY may stay active for 1/32768 second (~30 usec) */ for (count = 0; count < 50; count++) { - if (!(status & RTC_STATE_BUSY)) + if (!(status & OMAP_RTC_STATUS_BUSY)) break; udelay(1); - status = readb(&rtc->status); + status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG); } /* now we have ~15 usec to read/write various registers */ return 0; } -int rtc_get(struct rtc_time *tmp) +static int omap_rtc_reset(struct udevice *dev) { - struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; - unsigned long sec, min, hour, mday, wday, mon_cent, year; + struct omap_rtc_priv *priv = dev_get_priv(dev); + + /* run RTC counter */ + omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01); + return 0; +} + +static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + struct omap_rtc_priv *priv = dev_get_priv(dev); int ret; - ret = davinci_rtc_wait_not_busy(rtc); + ret = omap_rtc_wait_not_busy(priv); if (ret) return ret; - sec = readb(&rtc->second); - min = readb(&rtc->minutes); - hour = readb(&rtc->hours); - mday = readb(&rtc->day); - wday = readb(&rtc->dotw); - mon_cent = readb(&rtc->month); - year = readb(&rtc->year); + omap_rtc_unlock(priv); + omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100)); + omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon)); + omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday)); + omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday)); + omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour)); + omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min)); + omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec)); + omap_rtc_lock(priv); - debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx " + dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, + tm->tm_min, tm->tm_sec); + + return 0; +} + +static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + struct omap_rtc_priv *priv = dev_get_priv(dev); + unsigned long sec, min, hour, mday, wday, mon_cent, year; + int ret; + + ret = omap_rtc_wait_not_busy(priv); + if (ret) + return ret; + + sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG); + min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG); + hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG); + mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG); + wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG); + mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG); + year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG); + + dev_dbg(dev, + "Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx " "hr: %02lx min: %02lx sec: %02lx\n", year, mon_cent, mday, wday, hour, min, sec); - tmp->tm_sec = bcd2bin(sec & 0x7F); - tmp->tm_min = bcd2bin(min & 0x7F); - tmp->tm_hour = bcd2bin(hour & 0x3F); - tmp->tm_mday = bcd2bin(mday & 0x3F); - tmp->tm_mon = bcd2bin(mon_cent & 0x1F); - tmp->tm_year = bcd2bin(year) + 2000; - tmp->tm_wday = bcd2bin(wday & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst = 0; + tm->tm_sec = bcd2bin(sec & 0x7F); + tm->tm_min = bcd2bin(min & 0x7F); + tm->tm_hour = bcd2bin(hour & 0x3F); + tm->tm_mday = bcd2bin(mday & 0x3F); + tm->tm_mon = bcd2bin(mon_cent & 0x1F); + tm->tm_year = bcd2bin(year) + 2000; + tm->tm_wday = bcd2bin(wday & 0x07); + tm->tm_yday = 0; + tm->tm_isdst = 0; - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, + tm->tm_min, tm->tm_sec); return 0; } -int rtc_set(struct rtc_time *tmp) +static int omap_rtc_scratch_read(struct udevice *dev, uint offset, + u8 *buffer, uint len) { - struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; - int ret; + struct omap_rtc_priv *priv = dev_get_priv(dev); + u32 *val = (u32 *)buffer; + unsigned int reg; + int i; - ret = davinci_rtc_wait_not_busy(rtc); - if (ret) - return ret; + if (len & 3) + return -EFAULT; - davinci_rtc_unlock(rtc); - writeb(bin2bcd(tmp->tm_year % 100), &rtc->year); - writeb(bin2bcd(tmp->tm_mon), &rtc->month); + for (i = 0; i < len / 4; i++) { + reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4); + if (reg >= OMAP_RTC_KICK0_REG) + return -EFAULT; - writeb(bin2bcd(tmp->tm_wday), &rtc->dotw); - writeb(bin2bcd(tmp->tm_mday), &rtc->day); - writeb(bin2bcd(tmp->tm_hour), &rtc->hours); - writeb(bin2bcd(tmp->tm_min), &rtc->minutes); - writeb(bin2bcd(tmp->tm_sec), &rtc->second); - davinci_rtc_lock(rtc); - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + val[i] = omap_rtc_readl(priv, reg); + } return 0; } -void rtc_reset(void) +static int omap_rtc_scratch_write(struct udevice *dev, uint offset, + const u8 *buffer, uint len) { - struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; + struct omap_rtc_priv *priv = dev_get_priv(dev); + u32 *val = (u32 *)buffer; + unsigned int reg; + int i; - /* run RTC counter */ - writeb(0x01, &rtc->ctrl); + if (len & 3) + return -EFAULT; + + omap_rtc_unlock(priv); + for (i = 0; i < len / 4; i++) { + reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4); + if (reg >= OMAP_RTC_KICK0_REG) + return -EFAULT; + + omap_rtc_writel(priv, reg, val[i]); + } + omap_rtc_lock(priv); + + return 0; } + +static int omap_rtc_remove(struct udevice *dev) +{ + struct omap_rtc_priv *priv = dev_get_priv(dev); + u8 reg; + + if (priv->clk.dev) + clk_disable(&priv->clk); + + omap_rtc_unlock(priv); + + /* leave rtc running, but disable irqs */ + omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0); + + if (priv->has_ext_clk) { + reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG); + reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC; + omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg); + } + + omap_rtc_lock(priv); + return 0; +} + +static int omap_rtc_probe(struct udevice *dev) +{ + struct omap_rtc_priv *priv = dev_get_priv(dev); + u8 reg, mask, new_ctrl; + + priv->dev = dev; + priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev); + priv->max_reg = OMAP_RTC_PMIC_REG; + + if (!clk_get_by_name(dev, "ext-clk", &priv->clk)) + priv->has_ext_clk = true; + else + clk_get_by_name(dev, "int-clk", &priv->clk); + + if (priv->clk.dev) + clk_enable(&priv->clk); + else + dev_warn(dev, "missing clock\n"); + + omap_rtc_unlock(priv); + + /* + * disable interrupts + * + * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used + */ + omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0); + + if (priv->type->has_32kclk_en) { + reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG); + omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, + reg | OMAP_RTC_OSC_32KCLK_EN); + } + + /* clear old status */ + reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG); + + mask = OMAP_RTC_STATUS_ALARM; + + if (priv->type->has_pmic_mode) + mask |= OMAP_RTC_STATUS_ALARM2; + + if (priv->type->has_power_up_reset) { + mask |= OMAP_RTC_STATUS_POWER_UP; + if (reg & OMAP_RTC_STATUS_POWER_UP) + dev_info(dev, "RTC power up reset detected\n"); + } + + if (reg & mask) + omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask); + + /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ + reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG); + if (reg & OMAP_RTC_CTRL_STOP) + dev_info(dev, "already running\n"); + + /* force to 24 hour mode */ + new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); + new_ctrl |= OMAP_RTC_CTRL_STOP; + + /* + * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: + * + * - Device wake-up capability setting should come through chip + * init logic. OMAP1 boards should initialize the "wakeup capable" + * flag in the platform device if the board is wired right for + * being woken up by RTC alarm. For OMAP-L138, this capability + * is built into the SoC by the "Deep Sleep" capability. + * + * - Boards wired so RTC_ON_nOFF is used as the reset signal, + * rather than nPWRON_RESET, should forcibly enable split + * power mode. (Some chip errata report that RTC_CTRL_SPLIT + * is write-only, and always reads as zero...) + */ + + if (new_ctrl & OMAP_RTC_CTRL_SPLIT) + dev_info(dev, "split power mode\n"); + + if (reg != new_ctrl) + omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl); + + /* + * If we have the external clock then switch to it so we can keep + * ticking across suspend. + */ + if (priv->has_ext_clk) { + reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG); + reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; + reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; + omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg); + } + + omap_rtc_lock(priv); + return 0; +} + +static int omap_rtc_of_to_plat(struct udevice *dev) +{ + struct omap_rtc_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) { + dev_err(dev, "invalid address\n"); + return -EINVAL; + } + + dev_dbg(dev, "base=%pa\n", &priv->base); + return 0; +} + +static const struct rtc_ops omap_rtc_ops = { + .get = omap_rtc_get, + .set = omap_rtc_set, + .reset = omap_rtc_reset, + .read = omap_rtc_scratch_read, + .write = omap_rtc_scratch_write, +}; + +static const struct omap_rtc_device_type omap_rtc_am3352_type = { + .has_32kclk_en = true, + .has_irqwakeen = true, + .has_pmic_mode = true, +}; + +static const struct omap_rtc_device_type omap_rtc_da830_type = { + .has_32kclk_en = false, + .has_irqwakeen = false, + .has_pmic_mode = false, +}; + +static const struct udevice_id omap_rtc_ids[] = { + {.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type}, + {.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type } +}; + +U_BOOT_DRIVER(omap_rtc) = { + .name = "omap_rtc", + .id = UCLASS_RTC, + .of_match = omap_rtc_ids, + .ops = &omap_rtc_ops, + .of_to_plat = omap_rtc_of_to_plat, + .probe = omap_rtc_probe, + .remove = omap_rtc_remove, + .priv_auto = sizeof(struct omap_rtc_priv), +}; From 08ea87a6de1b9357b6edcfafb90be5bcecfd31c0 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 22:38:05 +0200 Subject: [PATCH 051/250] rtc: davinci: fix date loaded on reset On reset, the RTC loads the 2000-01-01 date with a wrong day of the week (Sunday instead of Saturday). Signed-off-by: Dario Binacchi Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210602203805.11494-9-dariobin@libero.it --- drivers/rtc/davinci.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 21e52344774..c7ce41bbf5c 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -290,6 +290,7 @@ static int omap_rtc_remove(struct udevice *dev) static int omap_rtc_probe(struct udevice *dev) { struct omap_rtc_priv *priv = dev_get_priv(dev); + struct rtc_time tm; u8 reg, mask, new_ctrl; priv->dev = dev; @@ -380,6 +381,15 @@ static int omap_rtc_probe(struct udevice *dev) } omap_rtc_lock(priv); + + if (omap_rtc_get(dev, &tm)) { + dev_err(dev, "failed to get datetime\n"); + } else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 && + tm.tm_wday == 0) { + tm.tm_wday = 6; + omap_rtc_set(dev, &tm); + } + return 0; } From 7d0f3fbb93cfebd7b5dc5635166e48ab998c4f82 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:02 +0300 Subject: [PATCH 052/250] lib: rational: copy the rational fraction lib routines from Linux Copy the best rational approximation calculation routines from Linux. Typical usecase for these routines is to calculate the M/N divider values for PLLs to reach a specific clock rate. This is based on linux kernel commit: "lib/math/rational.c: fix possible incorrect result from rational fractions helper" (sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881) Signed-off-by: Tero Kristo Reviewed-by: Tom Rini Signed-off-by: Tero Kristo --- include/linux/rational.h | 20 ++++++++ lib/Kconfig | 7 +++ lib/Makefile | 2 + lib/rational.c | 99 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 128 insertions(+) create mode 100644 include/linux/rational.h create mode 100644 lib/rational.c diff --git a/include/linux/rational.h b/include/linux/rational.h new file mode 100644 index 00000000000..33f5f5fc3e3 --- /dev/null +++ b/include/linux/rational.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer + * + * helper functions when coping with rational numbers, + * e.g. when calculating optimum numerator/denominator pairs for + * pll configuration taking into account restricted register size + */ + +#ifndef _LINUX_RATIONAL_H +#define _LINUX_RATIONAL_H + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator); + +#endif /* _LINUX_RATIONAL_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 15019d2c658..ad0cd52edd8 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -674,6 +674,13 @@ config GENERATE_SMBIOS_TABLE See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in the devicetree. +config LIB_RATIONAL + bool "enable continued fraction calculation routines" + +config SPL_LIB_RATIONAL + bool "enable continued fraction calculation routines for SPL" + depends on SPL + endmenu config ASN1_COMPILER diff --git a/lib/Makefile b/lib/Makefile index b4795a62a0d..881034f4ae3 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/ obj-$(CONFIG_$(SPL_)LZMA) += lzma/ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o +obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o + obj-$(CONFIG_LIBAVB) += libavb/ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ diff --git a/lib/rational.c b/lib/rational.c new file mode 100644 index 00000000000..316db3b5901 --- /dev/null +++ b/lib/rational.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer + * Copyright (C) 2019 Trent Piepho + * + * helper functions when coping with rational numbers + */ + +#include +#include +#include + +/* + * calculate best rational approximation for a given fraction + * taking into account restricted register size, e.g. to find + * appropriate values for a pll with 5 bit denominator and + * 8 bit numerator register fields, trying to set up with a + * frequency ratio of 3.1415, one would say: + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator) +{ + /* n/d is the starting rational, which is continually + * decreased each iteration using the Euclidean algorithm. + * + * dp is the value of d from the prior iteration. + * + * n2/d2, n1/d1, and n0/d0 are our successively more accurate + * approximations of the rational. They are, respectively, + * the current, previous, and two prior iterations of it. + * + * a is current term of the continued fraction. + */ + unsigned long n, d, n0, d0, n1, d1, n2, d2; + n = given_numerator; + d = given_denominator; + n0 = d1 = 0; + n1 = d0 = 1; + + for (;;) { + unsigned long dp, a; + + if (d == 0) + break; + /* Find next term in continued fraction, 'a', via + * Euclidean algorithm. + */ + dp = d; + a = n / d; + d = n % d; + n = dp; + + /* Calculate the current rational approximation (aka + * convergent), n2/d2, using the term just found and + * the two prior approximations. + */ + n2 = n0 + a * n1; + d2 = d0 + a * d1; + + /* If the current convergent exceeds the maxes, then + * return either the previous convergent or the + * largest semi-convergent, the final term of which is + * found below as 't'. + */ + if ((n2 > max_numerator) || (d2 > max_denominator)) { + unsigned long t = min((max_numerator - n0) / n1, + (max_denominator - d0) / d1); + + /* This tests if the semi-convergent is closer + * than the previous convergent. + */ + if (2u * t > a || (2u * t == a && d0 * dp > d1 * d)) { + n1 = n0 + t * n1; + d1 = d0 + t * d1; + } + break; + } + n0 = n1; + n1 = n2; + d0 = d1; + d1 = d2; + } + *best_numerator = n1; + *best_denominator = d1; +} From 99214c1f4825a3d2b88ebde1ad48b315c04f16fa Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:03 +0300 Subject: [PATCH 053/250] arm: mach-k3: introduce new config option for sysfw split On J7 family of SoCs (J721E and J7200), sysfw is being split to be run under two cores, TIFS portion on DMSC core, and DM firmware under MCU R5. As MCU R5 is also used to run one phase of the bootloader, we must prevent access from here towards sysfw services. To support this, add new config option which can be used to detect presence of RM/PM sysfw services. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 21b2fc2230d..fa8d134b42f 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -154,6 +154,17 @@ config K3_ATF_LOAD_ADDR The load address for the ATF image. This value defaults to 0x70000000 if not provided in the board defconfig file. +config K3_DM_FW + bool "Separate DM firmware image" + depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + default y + help + Enabling this will indicate that the system has separate DM + and TIFS firmware images in place, instead of a single SYSFW + firmware. Due to DM being executed on the same core as R5 SPL + bootloader, it makes RM and PM services not being available + during R5 SPL execution time. + source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/j721e/Kconfig" From 25805b6f0cf29cbb8db15ae2f0d4801c2f349985 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:04 +0300 Subject: [PATCH 054/250] remoteproc: k3-r5: remove sysfw PM calls if not supported With the sysfw rearch, sysfw PM calls are no longer available from SPL level. To properly support this, remove the is_on checks and the reset assertion from the R5 remoteproc driver as these are not supported. Attempting to access unavailable services will cause the device to hang. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/remoteproc/ti_k3_r5f_rproc.c | 30 ++++++++++++++++++---------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 3c569a3b7b6..6f3e12d915e 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -804,20 +804,28 @@ static int k3_r5f_probe(struct udevice *dev) return ret; } - ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id, - &r_state, &core->in_use); - if (ret) - return ret; + /* + * The PM functionality is not supported by the firmware during + * SPL execution with the separated DM firmware image. The following + * piece of code is not compiled in that case. + */ + if (!IS_ENABLED(CONFIG_K3_DM_FW)) { + ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, + core->tsp.dev_id, + &r_state, &core->in_use); + if (ret) + return ret; - if (core->in_use) { - dev_info(dev, "Core %d is already in use. No rproc commands work\n", - core->tsp.proc_id); - return 0; + if (core->in_use) { + dev_info(dev, "Core %d is already in use. No rproc commands work\n", + core->tsp.proc_id); + return 0; + } + + /* Make sure Local reset is asserted. Redundant? */ + reset_assert(&core->reset); } - /* Make sure Local reset is asserted. Redundant? */ - reset_assert(&core->reset); - ret = k3_r5f_rproc_configure(core); if (ret) { dev_err(dev, "rproc configure failed %d\n", ret); From 481d394e77915201e4ecc2d98e9cc2fbc3224991 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 11 Jun 2021 11:45:05 +0300 Subject: [PATCH 055/250] common: fit: Update board_fit_image_post_process() to pass fit and node_offset board_fit_image_post_process() passes only start and size of the image, but type of the image is not passed. So pass fit and node_offset, to derive information about image to be processed. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Signed-off-by: Tero Kristo --- arch/arm/mach-k3/security.c | 3 ++- arch/arm/mach-keystone/mon.c | 3 ++- arch/arm/mach-socfpga/board.c | 3 ++- board/ti/am335x/board.c | 3 ++- board/ti/am43xx/board.c | 3 ++- board/ti/am57xx/board.c | 3 ++- board/ti/dra7xx/evm.c | 3 ++- common/image-fit.c | 2 +- common/spl/spl_fit.c | 2 +- include/image.h | 5 ++++- 10 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 66f90a5a34d..5b5ff9ba7b3 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -18,7 +18,8 @@ #include #include -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { struct ti_sci_handle *ti_sci = get_ti_sci_handle(); struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index 58995d73ac8..b863bab1969 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1) return result; } -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { int result = 0; void *image = *p_image; diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 650122fcd4f..36eecdc0577 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -103,7 +103,8 @@ __weak int board_fit_config_name_match(const char *name) #endif #if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS) -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) { if (socfpga_vendor_authentication(p_image, p_size)) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 5959ff73dc4..5c156a5d1d8 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -960,7 +960,8 @@ int board_fit_config_name_match(const char *name) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index e9febb95921..a71b588efcb 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -896,7 +896,8 @@ int embedded_dtb_select(void) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 05c26c74d9d..399a2e5d913 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -1199,7 +1199,8 @@ static int board_bootmode_has_emmc(void) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 05f251f7782..23e80059915 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) #endif #ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(void **p_image, size_t *p_size) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) { secure_boot_verify_image(p_image, p_size); } diff --git a/common/image-fit.c b/common/image-fit.c index e614643fe39..0c5a05948d1 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, /* perform any post-processing on the image data */ if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)) - board_fit_image_post_process(&buf, &size); + board_fit_image_post_process(fit, noffset, &buf, &size); len = (ulong)size; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index caddf511967..57d621d5b3c 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -320,7 +320,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, } if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)) - board_fit_image_post_process(&src, &length); + board_fit_image_post_process(fit, node, &src, &length); load_ptr = map_sysmem(load_addr, length); if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) { diff --git a/include/image.h b/include/image.h index 459685d4d43..0c24bf6f35f 100644 --- a/include/image.h +++ b/include/image.h @@ -1581,11 +1581,14 @@ int board_fit_config_name_match(const char *name); * into the FIT creation (i.e. the binary blobs would have been pre-processed * before being added to the FIT image). * + * @fit: pointer to fit image + * @node: offset of image node * @image: pointer to the image start pointer * @size: pointer to the image size * @return no return value (failure should be handled internally) */ -void board_fit_image_post_process(void **p_image, size_t *p_size); +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size); #define FDT_ERROR ((ulong)(-1)) From fc960cb6fb94c77d1245e7f39b49d7278f480d62 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:06 +0300 Subject: [PATCH 056/250] clk: fixed_rate: add API for directly registering fixed rate clocks Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by: Peng Fan Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk_fixed_rate.c | 45 ++++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 48 insertions(+) diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 09f9ef26a42..325a9b2dcfb 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -9,6 +9,9 @@ #include #include +#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock" +#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock" + static ulong clk_fixed_rate_get_rate(struct clk *clk) { return to_clk_fixed_rate(clk->dev)->fixed_rate; @@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, clk->enable_count = 0; } +static ulong clk_fixed_rate_raw_get_rate(struct clk *clk) +{ + return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate; +} + +const struct clk_ops clk_fixed_rate_raw_ops = { + .get_rate = clk_fixed_rate_raw_get_rate, +}; + static int clk_fixed_rate_of_to_plat(struct udevice *dev) { clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev)); @@ -47,6 +59,32 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev) return 0; } +#if CONFIG_IS_ENABLED(CLK_CCF) +struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + ulong rate) +{ + struct clk *clk; + struct clk_fixed_rate *fixed; + int ret; + + fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return ERR_PTR(-ENOMEM); + + fixed->fixed_rate = rate; + + clk = &fixed->clk; + + ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL); + if (ret) { + kfree(fixed); + return ERR_PTR(ret); + } + + return clk; +} +#endif + static const struct udevice_id clk_fixed_rate_match[] = { { .compatible = "fixed-clock", @@ -63,3 +101,10 @@ U_BOOT_DRIVER(fixed_clock) = { .ops = &clk_fixed_rate_ops, .flags = DM_FLAG_PRE_RELOC, }; + +U_BOOT_DRIVER(clk_fixed_rate_raw) = { + .name = UBOOT_DM_CLK_FIXED_RATE_RAW, + .id = UCLASS_CLK, + .ops = &clk_fixed_rate_raw_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 6fda14f5fe6..9d296f240a4 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags); +struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + ulong rate); + const char *clk_hw_get_name(const struct clk *hw); ulong clk_generic_get_rate(struct clk *clk); From 1a725e229096385b4fb8d59247584435779d0161 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:07 +0300 Subject: [PATCH 057/250] clk: fix clock tree dump to properly dump out every registered clock Some clocks are not associated to a DM node, so just parsing the DM is not enough. This is especially true for root clocks, which typically don't have any parents. Instead, fetch every registered UCLASS_CLK instance, and dump these out. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- cmd/clk.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/cmd/clk.c b/cmd/clk.c index e3c3d2f9bb2..0245b971360 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) { int i, is_last; struct udevice *child; - struct clk *clkp; + struct clk *clkp, *parent; u32 rate; clkp = dev_get_clk_ptr(dev); if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) { + parent = clk_get_parent(clkp); + if (!IS_ERR(parent) && depth == -1) + return; depth++; rate = clk_get_rate(clkp); @@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) } list_for_each_entry(child, &dev->child_head, sibling_node) { + if (child == dev) + continue; + is_last = list_is_last(&child->sibling_node, &dev->child_head); show_clks(child, depth, (last_flag << 1) | is_last); } @@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) int __weak soc_clk_dump(void) { - struct udevice *root; + struct udevice *dev; + struct uclass *uc; + int ret; - root = dm_root(); - if (root) { - printf(" Rate Usecnt Name\n"); - printf("------------------------------------------\n"); - show_clks(root, -1, 0); - } + ret = uclass_get(UCLASS_CLK, &uc); + if (ret) + return ret; + + printf(" Rate Usecnt Name\n"); + printf("------------------------------------------\n"); + + uclass_foreach_dev(dev, uc) + show_clks(dev, -1, 0); return 0; } From 920ea5a7f8cd05810ede2fc5c0a51d75ae00d175 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:08 +0300 Subject: [PATCH 058/250] clk: do not attempt to fetch clock pointer with null device Bail out early if device returned for the parent clock is null. This avoids warning prints like this when doing clk dump: dev_get_uclass_priv: null device Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk-uclass.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 53e7be764d3..451d7da001a 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -502,6 +502,8 @@ struct clk *clk_get_parent(struct clk *clk) return NULL; pdev = dev_get_parent(clk->dev); + if (!pdev) + return ERR_PTR(-ENODEV); pclk = dev_get_clk_ptr(pdev); if (!pclk) return ERR_PTR(-ENODEV); From 7ab418fbe61275efb5c89cff48bbdd299eb1a22e Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:09 +0300 Subject: [PATCH 059/250] clk: add support for setting clk rate from cmdline Add new clk subcommand "clk setfreq", for setting up a clock rate directly from u-boot cmdline. This is handy for any debugging purposes towards clocks. Acked-by: Lukasz Majewski Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- cmd/clk.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/cmd/clk.c b/cmd/clk.c index 0245b971360..7ece2454e09 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -98,8 +98,56 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc, return ret; } +#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK) +struct udevice *clk_lookup(const char *name) +{ + int i = 0; + struct udevice *dev; + + do { + uclass_get_device(UCLASS_CLK, i++, &dev); + if (!strcmp(name, dev->name)) + return dev; + } while (dev); + + return NULL; +} + +static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct clk *clk = NULL; + s32 freq; + struct udevice *dev; + + freq = simple_strtoul(argv[2], NULL, 10); + + dev = clk_lookup(argv[1]); + + if (dev) + clk = dev_get_clk_ptr(dev); + + if (!clk) { + printf("clock '%s' not found.\n", argv[1]); + return -EINVAL; + } + + freq = clk_set_rate(clk, freq); + if (freq < 0) { + printf("set_rate failed: %d\n", freq); + return CMD_RET_FAILURE; + } + + printf("set_rate returns %u\n", freq); + return 0; +} +#endif + static struct cmd_tbl cmd_clk_sub[] = { U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK) + U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""), +#endif }; static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc, @@ -124,7 +172,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_SYS_LONGHELP static char clk_help_text[] = - "dump - Print clock frequencies"; + "dump - Print clock frequencies\n" + "setfreq [clk] [freq] - Set clock frequency"; #endif -U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); +U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text); From c319572abd95826b958c753ebcd3b83884eb60af Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:10 +0300 Subject: [PATCH 060/250] clk: sci-clk: fix return value of set_rate Set rate should return the new clock rate on success, and negative error value on failure. Fix this, as currently set_rate returns 0 on success. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-sci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c index 6f0fdaa111c..acb9eadf03c 100644 --- a/drivers/clk/ti/clk-sci.c +++ b/drivers/clk/ti/clk-sci.c @@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate) #endif ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX); - if (ret) + if (ret) { dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret); + return ret; + } - return ret; + return rate; } static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent) From 1e1fab0be59217aff9378e24f94f2340fbe2c3f7 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:11 +0300 Subject: [PATCH 061/250] clk: fix assigned-clocks to pass with deferring provider If a clock provider is not ready for assigning default rates/parents during its probe, it may return -EPROBE_DEFER directly from xlate. Handle this special case properly by skipping the entry and adjusting the return value to pass. The defaults will be handled properly in post probe phase then. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk-uclass.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 451d7da001a..815f7bfe987 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -241,6 +241,15 @@ static int clk_set_default_parents(struct udevice *dev, int stage) ret = clk_get_by_indexed_prop(dev, "assigned-clocks", index, &clk); + /* + * If the clock provider is not ready yet, let it handle + * the re-programming later. + */ + if (ret == -EPROBE_DEFER) { + ret = 0; + continue; + } + if (ret) { debug("%s: could not get assigned clock %d for %s\n", __func__, index, dev_read_name(dev)); @@ -309,6 +318,15 @@ static int clk_set_default_rates(struct udevice *dev, int stage) ret = clk_get_by_indexed_prop(dev, "assigned-clocks", index, &clk); + /* + * If the clock provider is not ready yet, let it handle + * the re-programming later. + */ + if (ret == -EPROBE_DEFER) { + ret = 0; + continue; + } + if (ret) { dev_dbg(dev, "could not get assigned clock %d (err = %d)\n", From 6b7fd3128f71e8c1fa847c18be4b9a322f341ba7 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:12 +0300 Subject: [PATCH 062/250] clk: fix set_rate to clean up cached rates for the hierarchy Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk-uclass.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 815f7bfe987..3d2344f009e 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -568,6 +568,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_clean_rate_cache(struct clk *clk) +{ + struct udevice *child_dev; + struct clk *clkp; + + if (!clk) + return; + + clk->rate = 0; + + list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) { + clkp = dev_get_clk_ptr(child_dev); + clk_clean_rate_cache(clkp); + } +} + ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; @@ -580,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* Clean up cached rates for us and all child clocks */ + clk_clean_rate_cache(clk); + return ops->set_rate(clk, rate); } From 0aa2930ca192a8738d1da8222fc6ac21d7c19182 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:13 +0300 Subject: [PATCH 063/250] clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/ti/Kconfig | 12 ++ drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-k3-pll.c | 283 ++++++++++++++++++++++++++++++++++++ include/k3-clk.h | 15 ++ 4 files changed, 311 insertions(+) create mode 100644 drivers/clk/ti/clk-k3-pll.c create mode 100644 include/k3-clk.h diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig index 2dc86d44a98..a8ec4f541a4 100644 --- a/drivers/clk/ti/Kconfig +++ b/drivers/clk/ti/Kconfig @@ -41,3 +41,15 @@ config CLK_TI_SCI This enables the clock driver support over TI System Control Interface available on some new TI's SoCs. If you wish to use clock resources managed by the TI System Controller, say Y here. Otherwise, say N. + +config CLK_K3_PLL + bool "PLL clock support for K3 SoC family of devices" + depends on CLK && LIB_RATIONAL + help + Enables PLL clock support for K3 SoC family of devices. + +config SPL_CLK_K3_PLL + bool "PLL clock support for K3 SoC family of devices" + depends on CLK && LIB_RATIONAL && SPL + help + Enables PLL clock support for K3 SoC family of devices. diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 9f56b477360..47839213e58 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o +obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c new file mode 100644 index 00000000000..bf2407a020a --- /dev/null +++ b/drivers/clk/ti/clk-k3-pll.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 SoC PLL clock driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include "k3-clk.h" +#include + +/* 16FFT register offsets */ +#define PLL_16FFT_CFG 0x08 +#define PLL_KICK0 0x10 +#define PLL_KICK1 0x14 +#define PLL_16FFT_CTRL 0x20 +#define PLL_16FFT_STAT 0x24 +#define PLL_16FFT_FREQ_CTRL0 0x30 +#define PLL_16FFT_FREQ_CTRL1 0x34 +#define PLL_16FFT_DIV_CTRL 0x38 + +/* CTRL register bits */ +#define PLL_16FFT_CTRL_BYPASS_EN BIT(31) +#define PLL_16FFT_CTRL_PLL_EN BIT(15) +#define PLL_16FFT_CTRL_DSM_EN BIT(1) + +/* STAT register bits */ +#define PLL_16FFT_STAT_LOCK BIT(0) + +/* FREQ_CTRL0 bits */ +#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff + +/* DIV CTRL register bits */ +#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f + +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 +#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15) + +/* KICK register magic values */ +#define PLL_KICK0_VALUE 0x68ef3490 +#define PLL_KICK1_VALUE 0xd172bc5a + +/** + * struct ti_pll_clk - TI PLL clock data info structure + * @clk: core clock structure + * @reg: memory address of the PLL controller + */ +struct ti_pll_clk { + struct clk clk; + void __iomem *reg; +}; + +#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk) + +static int ti_pll_wait_for_lock(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 stat; + int i; + + for (i = 0; i < 100000; i++) { + stat = readl(pll->reg + PLL_16FFT_STAT); + if (stat & PLL_16FFT_STAT_LOCK) + return 0; + } + + printf("%s: pll (%s) failed to lock\n", __func__, + clk->dev->name); + + return -EBUSY; +} + +static ulong ti_pll_clk_get_rate(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u64 current_freq; + u64 parent_freq = clk_get_parent_rate(clk); + u32 pllm; + u32 plld; + u32 pllfm; + u32 ctrl; + + /* Check if we are in bypass */ + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + if (ctrl & PLL_16FFT_CTRL_BYPASS_EN) + return parent_freq; + + pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0); + pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1); + + plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) & + PLL_16FFT_DIV_CTRL_REF_DIV_MASK; + + current_freq = parent_freq * pllm / plld; + + if (pllfm) { + u64 tmp; + + tmp = parent_freq * pllfm; + do_div(tmp, plld); + tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS; + current_freq += tmp; + } + + return current_freq; +} + +static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u64 current_freq; + u64 parent_freq = clk_get_parent_rate(clk); + int ret; + u32 ctrl; + unsigned long pllm; + u32 pllfm = 0; + unsigned long plld; + u32 rem; + int shift; + + debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate); + + if (ti_pll_clk_get_rate(clk) == rate) + return rate; + + if (rate != parent_freq) + /* + * Attempt with higher max multiplier value first to give + * some space for fractional divider to kick in. + */ + for (shift = 8; shift >= 0; shift -= 8) { + rational_best_approximation(rate, parent_freq, + ((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1, + PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld); + if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK) + break; + } + + /* Put PLL to bypass mode */ + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl |= PLL_16FFT_CTRL_BYPASS_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + if (rate == parent_freq) { + debug("%s: put %s to bypass\n", __func__, clk->dev->name); + return rate; + } + + debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n", + __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm); + + /* Check if we need fractional config */ + if (plld > 1) { + pllfm = pllm % plld; + pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS; + rem = pllfm % plld; + pllfm /= plld; + if (rem) + pllfm++; + pllm /= plld; + plld = 1; + } + + if (pllfm) + ctrl |= PLL_16FFT_CTRL_DSM_EN; + else + ctrl &= ~PLL_16FFT_CTRL_DSM_EN; + + writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0); + writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1); + writel(plld, pll->reg + PLL_16FFT_DIV_CTRL); + + ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; + ctrl |= PLL_16FFT_CTRL_PLL_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + ret = ti_pll_wait_for_lock(clk); + if (ret) + return ret; + + debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n", + __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq); + + current_freq = parent_freq * pllm / plld; + + if (pllfm) { + u64 tmp; + + tmp = parent_freq * pllfm; + do_div(tmp, plld); + tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS; + current_freq += tmp; + } + + return current_freq; +} + +static int ti_pll_clk_enable(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 ctrl; + + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; + ctrl |= PLL_16FFT_CTRL_PLL_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + return ti_pll_wait_for_lock(clk); +} + +static int ti_pll_clk_disable(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 ctrl; + + ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl |= PLL_16FFT_CTRL_BYPASS_EN; + writel(ctrl, pll->reg + PLL_16FFT_CTRL); + + return 0; +} + +static const struct clk_ops ti_pll_clk_ops = { + .get_rate = ti_pll_clk_get_rate, + .set_rate = ti_pll_clk_set_rate, + .enable = ti_pll_clk_enable, + .disable = ti_pll_clk_disable, +}; + +struct clk *clk_register_ti_pll(const char *name, const char *parent_name, + void __iomem *reg) +{ + struct ti_pll_clk *pll; + int ret; + int i; + u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->reg = reg; + + ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name); + if (ret) { + printf("%s: failed to register: %d\n", __func__, ret); + kfree(pll); + return ERR_PTR(ret); + } + + /* Unlock the PLL registers */ + writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0); + writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1); + + /* Enable all HSDIV outputs */ + cfg = readl(pll->reg + PLL_16FFT_CFG); + for (i = 0; i < 16; i++) { + hsdiv_presence_bit = BIT(16 + i); + hsdiv_ctrl_offs = 0x80 + (i * 4); + /* Enable HSDIV output if present */ + if ((hsdiv_presence_bit & cfg) != 0UL) { + ctrl = readl(pll->reg + hsdiv_ctrl_offs); + ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN; + writel(ctrl, pll->reg + hsdiv_ctrl_offs); + } + } + + return &pll->clk; +} + +U_BOOT_DRIVER(ti_pll_clk) = { + .name = "ti-pll-clk", + .id = UCLASS_CLK, + .ops = &ti_pll_clk_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/k3-clk.h b/include/k3-clk.h new file mode 100644 index 00000000000..fc84378d03f --- /dev/null +++ b/include/k3-clk.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com + * Tero Kristo + */ + +#ifndef __K3_CLK_H__ +#define __K3_CLK_H__ + +#include + +struct clk *clk_register_ti_pll(const char *name, const char *parent_name, + void __iomem *reg); + +#endif /* __K3_CLK_H__ */ From b4a72a9f5b805b438312fd239fc8bfffd8f7b771 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:14 +0300 Subject: [PATCH 064/250] clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/ti/Kconfig | 12 ++ drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-k3.c | 374 ++++++++++++++++++++++++++++++++++++++++ include/k3-clk.h | 161 +++++++++++++++++ 4 files changed, 548 insertions(+) create mode 100644 drivers/clk/ti/clk-k3.c diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig index a8ec4f541a4..fbcdefd889a 100644 --- a/drivers/clk/ti/Kconfig +++ b/drivers/clk/ti/Kconfig @@ -53,3 +53,15 @@ config SPL_CLK_K3_PLL depends on CLK && LIB_RATIONAL && SPL help Enables PLL clock support for K3 SoC family of devices. + +config CLK_K3 + bool "Clock support for K3 SoC family of devices" + depends on CLK + help + Enables the clock translation layer from DT to device clocks. + +config SPL_CLK_K3 + bool "Clock support for K3 SoC family of devices" + depends on CLK && SPL + help + Enables the clock translation layer from DT to device clocks. diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 47839213e58..07aa9a53e08 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o +obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c new file mode 100644 index 00000000000..e921894e7a2 --- /dev/null +++ b/drivers/clk/ti/clk-k3.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 clock driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include "k3-clk.h" + +#define PLL_MIN_FREQ 800000000 +#define PLL_MAX_FREQ 3200000000UL +#define PLL_MAX_DIV 127 + +/** + * struct clk_map - mapping from dev/clk id tuples towards physical clocks + * @dev_id: device ID for the clock + * @clk_id: clock ID for the clock + * @clk: pointer to the registered clock entry for the mapping + */ +struct clk_map { + u16 dev_id; + u32 clk_id; + struct clk *clk; +}; + +/** + * struct ti_clk_data - clock controller information structure + * @map: mapping from dev/clk id tuples to physical clock entries + * @size: number of entries in the map + */ +struct ti_clk_data { + struct clk_map *map; + int size; +}; + +static ulong osc_freq; + +static void clk_add_map(struct ti_clk_data *data, struct clk *clk, + u32 dev_id, u32 clk_id) +{ + struct clk_map *map; + + debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__, + clk, data, dev_id, clk_id); + if (!clk) + return; + + map = data->map + data->size++; + + map->dev_id = dev_id; + map->clk_id = clk_id; + map->clk = clk; +} + +static const struct soc_attr ti_k3_soc_clk_data[] = { +#if IS_ENABLED(CONFIG_SOC_K3_J721E) + { + .family = "J721E", + .data = &j721e_clk_platdata, + }, + { + .family = "J7200", + .data = &j7200_clk_platdata, + }, +#endif + { /* sentinel */ } +}; + +static int ti_clk_probe(struct udevice *dev) +{ + struct ti_clk_data *data = dev_get_priv(dev); + struct clk *clk; + const char *name; + const struct clk_data *ti_clk_data; + int i, j; + const struct soc_attr *soc_match_data; + const struct ti_k3_clk_platdata *pdata; + + debug("%s(dev=%p)\n", __func__, dev); + + soc_match_data = soc_device_match(ti_k3_soc_clk_data); + if (!soc_match_data) + return -ENODEV; + + pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data; + + data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map), + GFP_KERNEL); + data->size = 0; + + for (i = 0; i < pdata->clk_list_cnt; i++) { + ti_clk_data = &pdata->clk_list[i]; + + switch (ti_clk_data->type) { + case CLK_TYPE_FIXED_RATE: + name = ti_clk_data->clk.fixed_rate.name; + clk = clk_register_fixed_rate(NULL, + name, + ti_clk_data->clk.fixed_rate.rate); + break; + case CLK_TYPE_DIV: + name = ti_clk_data->clk.div.name; + clk = clk_register_divider(NULL, name, + ti_clk_data->clk.div.parent, + ti_clk_data->clk.div.flags, + map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE), + ti_clk_data->clk.div.shift, + ti_clk_data->clk.div.width, + 0); + break; + case CLK_TYPE_MUX: + name = ti_clk_data->clk.mux.name; + clk = clk_register_mux(NULL, name, + ti_clk_data->clk.mux.parents, + ti_clk_data->clk.mux.num_parents, + ti_clk_data->clk.mux.flags, + map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE), + ti_clk_data->clk.mux.shift, + ti_clk_data->clk.mux.width, + 0); + break; + case CLK_TYPE_PLL: + name = ti_clk_data->clk.pll.name; + clk = clk_register_ti_pll(name, + ti_clk_data->clk.pll.parent, + map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE)); + + if (!osc_freq) + osc_freq = clk_get_rate(clk_get_parent(clk)); + break; + default: + name = NULL; + clk = NULL; + printf("WARNING: %s has encountered unknown clk type %d\n", + __func__, ti_clk_data->type); + } + + if (clk && ti_clk_data->default_freq) + clk_set_rate(clk, ti_clk_data->default_freq); + + if (clk && name) { + for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) { + if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) { + clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id, + pdata->soc_dev_clk_data[j].clk_id); + } + } + } + } + + return 0; +} + +static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map) +{ + if (map->dev_id == dev_id && map->clk_id == clk_id) + return 0; + if (map->dev_id > dev_id || + (map->dev_id == dev_id && map->clk_id > clk_id)) + return -1; + return 1; +} + +static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num) +{ + int result; + int idx; + + for (idx = 0; idx < num; idx++) { + result = _clk_cmp(dev_id, clk_id, &map[idx]); + + if (result == 0) + return idx; + } + + return -ENOENT; +} + +static int ti_clk_of_xlate(struct clk *clk, + struct ofnode_phandle_args *args) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + int idx; + + debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk, + args->args_count, args->args[0], args->args[1]); + + if (args->args_count != 2) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (!data->size) + return -EPROBE_DEFER; + + idx = bsearch(args->args[0], args->args[1], data->map, data->size); + if (idx < 0) + return idx; + + clk->id = idx; + + return 0; +} + +static ulong ti_clk_get_rate(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_get_rate(clkp); +} + +static ulong ti_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + int div = 1; + ulong child_rate; + const struct clk_ops *ops; + ulong new_rate, rem; + ulong diff, new_diff; + + /* + * We must propagate rate change to parent if current clock type + * does not allow setting it. + */ + while (clkp) { + ops = clkp->dev->driver->ops; + if (ops->set_rate) + break; + + /* + * Store child rate so we can calculate the clock rate + * that must be passed to parent + */ + child_rate = clk_get_rate(clkp); + clkp = clk_get_parent(clkp); + if (clkp) { + debug("%s: propagating rate change to parent %s, rate=%u.\n", + __func__, clkp->dev->name, (u32)rate / div); + div *= clk_get_rate(clkp) / child_rate; + } + } + + if (!clkp) + return -ENOSYS; + + child_rate = clk_get_rate(clkp); + + new_rate = clk_set_rate(clkp, rate / div); + + diff = abs(new_rate - rate / div); + + debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__, + clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff); + + /* + * If the new rate differs by 50% of the target, + * modify parent. This handles typical cases where we have a hsdiv + * following directly a PLL + */ + + if (diff > rate / div / 2) { + ulong pll_tgt; + int pll_div = 0; + + clk = clkp; + + debug("%s: propagating rate change to parent, rate=%u.\n", + __func__, (u32)rate / div); + + clkp = clk_get_parent(clkp); + + if (rate > osc_freq) { + if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) { + pll_tgt = rate; + pll_div = 1; + } else { + for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) { + pll_tgt = rate / div * pll_div; + if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ) + break; + } + } + } else { + pll_tgt = osc_freq; + pll_div = rate / div / osc_freq; + } + + debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__, + (u32)pll_tgt, (u32)rate, pll_div); + + clk_set_rate(clkp, pll_tgt); + + return clk_set_rate(clk, rate / div) * div; + } + + /* + * If the new rate differs by at least 5% of the target, + * we must check for rounding error in a divider, so try + * set rate with rate + (parent_freq % rate). + */ + + if (diff > rate / div / 20) { + u64 parent_freq = clk_get_parent_rate(clkp); + + rem = parent_freq % rate; + new_rate = clk_set_rate(clkp, (rate / div) + rem); + new_diff = abs(new_rate - rate / div); + + if (new_diff > diff) { + new_rate = clk_set_rate(clkp, rate / div); + } else { + debug("%s: Using better rate %lu that gives diff %lu\n", + __func__, new_rate, new_diff); + } + } + + return new_rate; +} + +static int ti_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + struct clk *parentp = data->map[parent->id].clk; + + return clk_set_parent(clkp, parentp); +} + +static int ti_clk_enable(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_enable(clkp); +} + +static int ti_clk_disable(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_disable(clkp); +} + +static const struct udevice_id ti_clk_of_match[] = { + { .compatible = "ti,k2g-sci-clk" }, + { /* sentinel */ }, +}; + +static const struct clk_ops ti_clk_ops = { + .of_xlate = ti_clk_of_xlate, + .set_rate = ti_clk_set_rate, + .get_rate = ti_clk_get_rate, + .enable = ti_clk_enable, + .disable = ti_clk_disable, + .set_parent = ti_clk_set_parent, +}; + +U_BOOT_DRIVER(ti_clk) = { + .name = "ti-clk", + .id = UCLASS_CLK, + .of_match = ti_clk_of_match, + .probe = ti_clk_probe, + .priv_auto = sizeof(struct ti_clk_data), + .ops = &ti_clk_ops, +}; diff --git a/include/k3-clk.h b/include/k3-clk.h index fc84378d03f..07352285798 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -7,7 +7,168 @@ #ifndef __K3_CLK_H__ #define __K3_CLK_H__ +#include +#include #include +#include +#include + +struct dev_clk { + int dev_id; + int clk_id; + const char *clk_name; +}; + +#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \ + .clk_id = _clk_id, .clk_name = _clk_name, } + +#define CLK_TYPE_MUX 0x01 +#define CLK_TYPE_DIV 0x02 +#define CLK_TYPE_PLL 0x03 +#define CLK_TYPE_HFOSC 0x04 +#define CLK_TYPE_POSTDIV 0x05 +#define CLK_TYPE_MUX_PLLCTRL 0x06 +#define CLK_TYPE_FIXED_RATE 0x07 + +struct pll_data { + u32 reg; + const char *name; + const char *parent; + u32 flags; +}; + +struct mux_data { + u32 reg; + const char *name; + const char * const *parents; + int num_parents; + u32 flags; + int shift; + int width; +}; + +struct div_data { + u32 reg; + const char *name; + const char *parent; + u32 flags; + int shift; + int width; +}; + +struct hfosc_data { + const char *name; + u32 flags; +}; + +struct fixed_rate_data { + const char *name; + u64 rate; + u32 flags; +}; + +struct postdiv_data { + const char *name; + const char *parent; + int width; + u32 flags; +}; + +struct mux_pllctrl_data { + u32 reg; + const char *name; + const char * const *parents; + int num_parents; + u32 flags; +}; + +struct clk_data { + int type; + u32 default_freq; + union { + struct pll_data pll; + struct mux_data mux; + struct div_data div; + struct hfosc_data hfosc; + struct postdiv_data postdiv; + struct mux_pllctrl_data mux_pllctrl; + struct fixed_rate_data fixed_rate; + } clk; +}; + +#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \ + { \ + .type = CLK_TYPE_MUX, \ + .clk.mux = { .name = _name, .parents = _parents, \ + .reg = _reg, \ + .num_parents = _num_parents, .shift = _shift, \ + .width = _width, .flags = _flags } \ + } + +#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \ + { \ + .type = CLK_TYPE_DIV, \ + .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \ + } + +#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \ + { \ + .type = CLK_TYPE_DIV, \ + .default_freq = _freq, \ + .clk.div = { \ + .name = _name, .parent = _parent, \ + .reg = _reg, .shift = _shift, \ + .width = _width, .flags = _flags } \ + } + +#define CLK_PLL(_name, _parent, _reg, _flags) \ + { \ + .type = CLK_TYPE_PLL, \ + .clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \ + } + +#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \ + { \ + .type = CLK_TYPE_PLL, \ + .default_freq = _freq, \ + .clk.pll = { .name = _name, .parent = _parent, \ + .reg = _reg, .flags = _flags } \ + } + +#define CLK_HFOSC(_name, _flags) \ + { \ + .type = CLK_TYPE_HFOSC, \ + .clk.hfosc = { .name = _name, .flags = _flags } \ + } + +#define CLK_FIXED_RATE(_name, _rate, _flags) \ + { \ + .type = CLK_TYPE_FIXED_RATE, \ + .clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \ + } + +#define CLK_POSTDIV(_name, _parent, _width, _flags) \ + { \ + .type = CLK_TYPE_POSTDIV, \ + .clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \ + } + +#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \ + { \ + .type = CLK_TYPE_MUX, \ + .clk.mux_pllctrl = { .name = _name, .parents = _parents,\ + .num_parents = _num_parents, .flags = _flags } \ + } + +struct ti_k3_clk_platdata { + const struct clk_data *clk_list; + int clk_list_cnt; + const struct dev_clk *soc_dev_clk_data; + int soc_dev_clk_data_cnt; +}; + +extern const struct ti_k3_clk_platdata j721e_clk_platdata; +extern const struct ti_k3_clk_platdata j7200_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); From 144464bd2c67a1f11e8dd4fb4a18b45b666dc1c4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:15 +0300 Subject: [PATCH 065/250] power: domain: Introduce driver for raw TI K3 PDs Normally, power domains are handled via TI-SCI in K3 SoCs. However, SPL is not going to have access to sysfw resources, so it must control them directly. Add driver for supporting this. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo Reviewed-by: Jaehoon Chung --- drivers/power/domain/Kconfig | 7 + drivers/power/domain/Makefile | 1 + drivers/power/domain/ti-power-domain.c | 368 +++++++++++++++++++++++++ include/k3-dev.h | 76 +++++ 4 files changed, 452 insertions(+) create mode 100644 drivers/power/domain/ti-power-domain.c create mode 100644 include/k3-dev.h diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index a0fd9807529..99b3f9ae71b 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN help Generic power domain implementation for TI devices implementing the TI SCI protocol. + +config TI_POWER_DOMAIN + bool "Enable the TI K3 Power domain driver" + depends on POWER_DOMAIN && ARCH_K3 + help + Generic power domain implementation for TI K3 devices. + endmenu diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 45bf9f63834..3d1e5f073cb 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o +obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c new file mode 100644 index 00000000000..56bc6fc31c5 --- /dev/null +++ b/drivers/power/domain/ti-power-domain.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments power domain driver + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PSC_PTCMD 0x120 +#define PSC_PTSTAT 0x128 +#define PSC_PDSTAT 0x200 +#define PSC_PDCTL 0x300 +#define PSC_MDSTAT 0x800 +#define PSC_MDCTL 0xa00 + +#define PDCTL_STATE_MASK 0x1 +#define PDCTL_STATE_OFF 0x0 +#define PDCTL_STATE_ON 0x1 + +#define MDSTAT_STATE_MASK 0x3f +#define MDSTAT_BUSY_MASK 0x30 +#define MDSTAT_STATE_SWRSTDISABLE 0x0 +#define MDSTAT_STATE_ENABLE 0x3 + +#define LPSC_TIMEOUT 1000 +#define PD_TIMEOUT 1000 + +static u32 psc_read(struct ti_psc *psc, u32 reg) +{ + u32 val; + + val = readl(psc->base + reg); + debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg); + return val; +} + +static void psc_write(u32 val, struct ti_psc *psc, u32 reg) +{ + debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg); + writel(val, psc->base + reg); +} + +static u32 pd_read(struct ti_pd *pd, u32 reg) +{ + return psc_read(pd->psc, reg + 4 * pd->id); +} + +static void pd_write(u32 val, struct ti_pd *pd, u32 reg) +{ + psc_write(val, pd->psc, reg + 4 * pd->id); +} + +static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg) +{ + return psc_read(lpsc->psc, reg + 4 * lpsc->id); +} + +static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg) +{ + psc_write(val, lpsc->psc, reg + 4 * lpsc->id); +} + +static const struct soc_attr ti_k3_soc_pd_data[] = { +#if IS_ENABLED(CONFIG_SOC_K3_J721E) + { + .family = "J721E", + .data = &j721e_pd_platdata, + }, + { + .family = "J7200", + .data = &j7200_pd_platdata, + }, +#endif + { /* sentinel */ } +}; + +static int ti_power_domain_probe(struct udevice *dev) +{ + struct ti_k3_pd_platdata *data = dev_get_priv(dev); + const struct soc_attr *soc_match_data; + const struct ti_k3_pd_platdata *pdata; + + printf("%s(dev=%p)\n", __func__, dev); + + if (!data) + return -ENOMEM; + + soc_match_data = soc_device_match(ti_k3_soc_pd_data); + if (!soc_match_data) + return -ENODEV; + + pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data; + + data->psc = pdata->psc; + data->pd = pdata->pd; + data->lpsc = pdata->lpsc; + data->devs = pdata->devs; + data->num_psc = pdata->num_psc; + data->num_pd = pdata->num_pd; + data->num_lpsc = pdata->num_lpsc; + data->num_devs = pdata->num_devs; + + return 0; +} + +static int ti_pd_wait(struct ti_pd *pd) +{ + u32 ptstat; + int ret; + + ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat, + !(ptstat & BIT(pd->id)), PD_TIMEOUT); + + if (ret) + printf("%s: psc%d, pd%d failed to transition.\n", __func__, + pd->psc->id, pd->id); + + return ret; +} + +static void ti_pd_transition(struct ti_pd *pd) +{ + psc_write(BIT(pd->id), pd->psc, PSC_PTCMD); +} + +static u8 ti_pd_state(struct ti_pd *pd) +{ + return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK; +} + +static int ti_pd_get(struct ti_pd *pd) +{ + u32 pdctl; + int ret; + + pd->usecount++; + + if (pd->usecount > 1) + return 0; + + if (pd->depend) { + ret = ti_pd_get(pd->depend); + if (ret) + return ret; + ti_pd_transition(pd->depend); + ret = ti_pd_wait(pd->depend); + if (ret) + return ret; + } + + pdctl = pd_read(pd, PSC_PDCTL); + + if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON) + return 0; + + debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id); + + pdctl &= ~PDCTL_STATE_MASK; + pdctl |= PDCTL_STATE_ON; + + pd_write(pdctl, pd, PSC_PDCTL); + + return 0; +} + +static int ti_pd_put(struct ti_pd *pd) +{ + u32 pdctl; + int ret; + + pd->usecount--; + + if (pd->usecount > 0) + return 0; + + pdctl = pd_read(pd, PSC_PDCTL); + if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF) + return 0; + + pdctl &= ~PDCTL_STATE_MASK; + pdctl |= PDCTL_STATE_OFF; + + debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id); + + pd_write(pdctl, pd, PSC_PDCTL); + + if (pd->depend) { + ti_pd_transition(pd); + ret = ti_pd_wait(pd); + if (ret) + return ret; + + ret = ti_pd_put(pd->depend); + if (ret) + return ret; + ti_pd_transition(pd->depend); + ret = ti_pd_wait(pd->depend); + if (ret) + return ret; + } + + return 0; +} + +static int ti_lpsc_wait(struct ti_lpsc *lpsc) +{ + u32 mdstat; + int ret; + + ret = readl_poll_timeout(lpsc->psc->base + PSC_MDSTAT + lpsc->id * 4, + mdstat, + !(mdstat & MDSTAT_BUSY_MASK), LPSC_TIMEOUT); + + if (ret) + printf("%s: module %d failed to transition.\n", __func__, + lpsc->id); + + return ret; +} + +static u8 lpsc_get_state(struct ti_lpsc *lpsc) +{ + return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK; +} + +static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) +{ + struct ti_pd *psc_pd; + int ret; + u32 mdctl; + + psc_pd = lpsc->pd; + + if (state == MDSTAT_STATE_ENABLE) { + lpsc->usecount++; + if (lpsc->usecount > 1) + return 0; + } else { + lpsc->usecount--; + if (lpsc->usecount >= 1) + return 0; + } + + debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__, + lpsc->psc->id, lpsc->id, state); + + if (lpsc->depend) + ti_lpsc_transition(lpsc->depend, state); + + mdctl = lpsc_read(lpsc, PSC_MDCTL); + if ((mdctl & MDSTAT_STATE_MASK) == state) + return 0; + + if (state == MDSTAT_STATE_ENABLE) + ti_pd_get(psc_pd); + else + ti_pd_put(psc_pd); + + mdctl &= ~MDSTAT_STATE_MASK; + mdctl |= state; + + lpsc_write(mdctl, lpsc, PSC_MDCTL); + + ti_pd_transition(psc_pd); + ret = ti_pd_wait(psc_pd); + if (ret) + return ret; + + return ti_lpsc_wait(lpsc); +} + +static int ti_power_domain_transition(struct power_domain *pd, u8 state) +{ + struct ti_lpsc *lpsc = pd->priv; + + return ti_lpsc_transition(lpsc, state); +} + +static int ti_power_domain_on(struct power_domain *pd) +{ + debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id); + + return ti_power_domain_transition(pd, MDSTAT_STATE_ENABLE); +} + +static int ti_power_domain_off(struct power_domain *pd) +{ + debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id); + + return ti_power_domain_transition(pd, MDSTAT_STATE_SWRSTDISABLE); +} + +static struct ti_lpsc *lpsc_lookup(struct ti_k3_pd_platdata *data, int id) +{ + int idx; + + for (idx = 0; idx < data->num_devs; idx++) + if (data->devs[idx].id == id) + return data->devs[idx].lpsc; + + return NULL; +} + +static int ti_power_domain_of_xlate(struct power_domain *pd, + struct ofnode_phandle_args *args) +{ + struct ti_k3_pd_platdata *data = dev_get_priv(pd->dev); + struct ti_lpsc *lpsc; + + debug("%s(power_domain=%p, id=%d)\n", __func__, pd, args->args[0]); + + if (args->args_count < 1) { + printf("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + lpsc = lpsc_lookup(data, args->args[0]); + if (!lpsc) { + printf("%s: invalid dev-id: %d\n", __func__, args->args[0]); + return -ENOENT; + } + + pd->id = lpsc->id; + pd->priv = lpsc; + + return 0; +} + +static int ti_power_domain_request(struct power_domain *pd) +{ + return 0; +} + +static int ti_power_domain_free(struct power_domain *pd) +{ + return 0; +} + +static const struct udevice_id ti_power_domain_of_match[] = { + { .compatible = "ti,sci-pm-domain" }, + { /* sentinel */ } +}; + +static struct power_domain_ops ti_power_domain_ops = { + .on = ti_power_domain_on, + .off = ti_power_domain_off, + .of_xlate = ti_power_domain_of_xlate, + .request = ti_power_domain_request, + .rfree = ti_power_domain_free, +}; + +U_BOOT_DRIVER(ti_pm_domains) = { + .name = "ti-pm-domains", + .id = UCLASS_POWER_DOMAIN, + .of_match = ti_power_domain_of_match, + .probe = ti_power_domain_probe, + .priv_auto = sizeof(struct ti_k3_pd_platdata), + .ops = &ti_power_domain_ops, +}; diff --git a/include/k3-dev.h b/include/k3-dev.h new file mode 100644 index 00000000000..de3a8bdf9eb --- /dev/null +++ b/include/k3-dev.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments K3 Device Platform Data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef __K3_DEV_H__ +#define __K3_DEV_H__ + +#include +#include +#include + +#define LPSC_MODULE_EXISTS BIT(0) +#define LPSC_NO_CLOCK_GATING BIT(1) +#define LPSC_DEPENDS BIT(2) +#define LPSC_HAS_RESET_ISO BIT(3) +#define LPSC_HAS_LOCAL_RESET BIT(4) +#define LPSC_NO_MODULE_RESET BIT(5) + +#define PSC_PD_EXISTS BIT(0) +#define PSC_PD_ALWAYSON BIT(1) +#define PSC_PD_DEPENDS BIT(2) + +struct ti_psc { + int id; + void __iomem *base; +}; + +struct ti_pd; + +struct ti_pd { + int id; + int usecount; + struct ti_psc *psc; + struct ti_pd *depend; +}; + +struct ti_lpsc; + +struct ti_lpsc { + int id; + int usecount; + struct ti_psc *psc; + struct ti_pd *pd; + struct ti_lpsc *depend; +}; + +struct ti_dev { + struct ti_lpsc *lpsc; + int id; +}; + +/** + * struct ti_k3_pd_platdata - pm domain controller information structure + */ +struct ti_k3_pd_platdata { + struct ti_psc *psc; + struct ti_pd *pd; + struct ti_lpsc *lpsc; + struct ti_dev *devs; + int num_psc; + int num_pd; + int num_lpsc; + int num_devs; +}; + +#define PSC(_id, _base) { .id = _id, .base = (void *)_base, } +#define PSC_PD(_id, _psc, _depend) { .id = _id, .psc = _psc, .depend = _depend } +#define PSC_LPSC(_id, _psc, _pd, _depend) { .id = _id, .psc = _psc, .pd = _pd, .depend = _depend } +#define PSC_DEV(_id, _lpsc) { .id = _id, .lpsc = _lpsc } + +extern const struct ti_k3_pd_platdata j721e_pd_platdata; +extern const struct ti_k3_pd_platdata j7200_pd_platdata; + +#endif From f79753c3defb15c037e4e8be6235b2a37a8b56d4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:16 +0300 Subject: [PATCH 066/250] cmd: ti: pd: Add debug command for K3 power domains Add support command for debugging K3 power domains. This is useful with the HSM rearch setup, where power domains are directly controlled by SPL instead of going through the TI SCI layer. The debugging support is only available in the u-boot codebase though, so the raw register access power domain layer must be enabled on u-boot side for this to work. By default, u-boot side uses the TI SCI layer, and R5 SPL only uses the direct access methods. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo Reviewed-by: Jaehoon Chung --- cmd/ti/Kconfig | 8 ++ cmd/ti/Makefile | 1 + cmd/ti/pd.c | 185 +++++++++++++++++++++++++ drivers/power/domain/ti-power-domain.c | 6 +- include/k3-dev.h | 9 ++ 5 files changed, 206 insertions(+), 3 deletions(-) create mode 100644 cmd/ti/pd.c diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig index efeff0d4823..db557445a89 100644 --- a/cmd/ti/Kconfig +++ b/cmd/ti/Kconfig @@ -7,4 +7,12 @@ config CMD_DDR3 supports memory verification, memory comapre and ecc verification if supported. +config CMD_PD + bool "command for verifying power domains" + depends on TI_POWER_DOMAIN + help + Debug command for K3 power domains. For this to work, the + K3 power domain driver must be enabled for the u-boot; by + default it is only enabled for SPL. + endmenu diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile index 16fbade9edd..045593396b7 100644 --- a/cmd/ti/Makefile +++ b/cmd/ti/Makefile @@ -5,4 +5,5 @@ obj- += dummy.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_DDR3) += ddr3.o +obj-$(CONFIG_CMD_PD) += pd.o endif diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c new file mode 100644 index 00000000000..9e820b84ca3 --- /dev/null +++ b/cmd/ti/pd.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Power Domain test commands + * + * Copyright (C) 2020 Texas Instruments Incorporated, + */ + +#include +#include +#include +#include + +static const struct udevice_id ti_pd_of_match[] = { + { .compatible = "ti,sci-pm-domain" }, + { /* sentinel */ } +}; + +static struct ti_k3_pd_platdata *ti_pd_find_data(void) +{ + struct udevice *dev; + int i = 0; + + while (1) { + uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev); + if (!dev) + return NULL; + + if (device_is_compatible(dev, + ti_pd_of_match[0].compatible)) + return dev_get_priv(dev); + } + + return NULL; +} + +static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd) +{ + int i; + struct ti_lpsc *lpsc; + u8 state; + static const char * const lpsc_states[] = { + "swrstdis", "syncrst", "disable", "enable", "autosleep", + "autowake", "unknown", + }; + + for (i = 0; i < data->num_lpsc; i++) { + lpsc = &data->lpsc[i]; + if (lpsc->pd != pd) + continue; + state = lpsc_get_state(lpsc); + if (state > ARRAY_SIZE(lpsc_states)) + state = ARRAY_SIZE(lpsc_states) - 1; + printf(" LPSC%d: state=%s, usecount=%d\n", + lpsc->id, lpsc_states[state], lpsc->usecount); + } +} + +static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc) +{ + int i; + struct ti_pd *pd; + u8 state; + static const char * const pd_states[] = { + "off", "on", "unknown" + }; + + for (i = 0; i < data->num_pd; i++) { + pd = &data->pd[i]; + if (pd->psc != psc) + continue; + state = ti_pd_state(pd); + if (state > ARRAY_SIZE(pd_states)) + state = ARRAY_SIZE(pd_states) - 1; + printf(" PD%d: state=%s, usecount=%d:\n", + pd->id, pd_states[state], pd->usecount); + dump_lpsc(data, pd); + } +} + +static void dump_psc(struct ti_k3_pd_platdata *data) +{ + int i; + struct ti_psc *psc; + + for (i = 0; i < data->num_psc; i++) { + psc = &data->psc[i]; + printf("PSC%d [%p]:\n", psc->id, psc->base); + dump_pd(data, psc); + } +} + +static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct ti_k3_pd_platdata *data; + + data = ti_pd_find_data(); + if (!data) + return CMD_RET_FAILURE; + + dump_psc(data); + + return 0; +} + +static int do_pd_endis(int argc, char *const argv[], u8 state) +{ + u32 psc_id; + u32 lpsc_id; + int i; + struct ti_k3_pd_platdata *data; + struct ti_lpsc *lpsc; + int ret; + + if (argc < 3) + return CMD_RET_FAILURE; + + data = ti_pd_find_data(); + if (!data) + return CMD_RET_FAILURE; + + psc_id = simple_strtoul(argv[1], NULL, 10); + lpsc_id = simple_strtoul(argv[2], NULL, 10); + + for (i = 0; i < data->num_lpsc; i++) { + lpsc = &data->lpsc[i]; + if (lpsc->pd->psc->id != psc_id) + continue; + if (lpsc->id != lpsc_id) + continue; + printf("%s pd [PSC:%d,LPSC:%d]...\n", + state == MDSTAT_STATE_ENABLE ? "Enabling" : "Disabling", + psc_id, lpsc_id); + ret = ti_lpsc_transition(lpsc, state); + if (ret) + return CMD_RET_FAILURE; + else + return 0; + } + + printf("No matching psc/lpsc found.\n"); + + return CMD_RET_FAILURE; +} + +static int do_pd_enable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_pd_endis(argc, argv, MDSTAT_STATE_ENABLE); +} + +static int do_pd_disable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_pd_endis(argc, argv, MDSTAT_STATE_SWRSTDISABLE); +} + +static struct cmd_tbl cmd_pd[] = { + U_BOOT_CMD_MKENT(dump, 1, 0, do_pd_dump, "", ""), + U_BOOT_CMD_MKENT(enable, 3, 0, do_pd_enable, "", ""), + U_BOOT_CMD_MKENT(disable, 3, 0, do_pd_disable, "", ""), +}; + +static int ti_do_pd(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_pd, ARRAY_SIZE(cmd_pd)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD(pd, 4, 1, ti_do_pd, + "TI power domain control", +#if CONFIG_IS_ENABLED(SYS_LONGHELP) + "dump - show power domain status\n" + "enable [psc] [lpsc] - enable power domain\n" + "disable [psc] [lpsc] - disable power domain\n" +#endif +); diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 56bc6fc31c5..b45e9b82453 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -132,7 +132,7 @@ static void ti_pd_transition(struct ti_pd *pd) psc_write(BIT(pd->id), pd->psc, PSC_PTCMD); } -static u8 ti_pd_state(struct ti_pd *pd) +u8 ti_pd_state(struct ti_pd *pd) { return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK; } @@ -227,12 +227,12 @@ static int ti_lpsc_wait(struct ti_lpsc *lpsc) return ret; } -static u8 lpsc_get_state(struct ti_lpsc *lpsc) +u8 lpsc_get_state(struct ti_lpsc *lpsc) { return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK; } -static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) +int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) { struct ti_pd *psc_pd; int ret; diff --git a/include/k3-dev.h b/include/k3-dev.h index de3a8bdf9eb..55c5057db35 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -22,6 +22,11 @@ #define PSC_PD_ALWAYSON BIT(1) #define PSC_PD_DEPENDS BIT(2) +#define MDSTAT_STATE_MASK 0x3f +#define MDSTAT_BUSY_MASK 0x30 +#define MDSTAT_STATE_SWRSTDISABLE 0x0 +#define MDSTAT_STATE_ENABLE 0x3 + struct ti_psc { int id; void __iomem *base; @@ -73,4 +78,8 @@ struct ti_k3_pd_platdata { extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata; +u8 ti_pd_state(struct ti_pd *pd); +u8 lpsc_get_state(struct ti_lpsc *lpsc); +int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state); + #endif From df5363a67f357106e559a64c09f6535ddac12ec1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:17 +0300 Subject: [PATCH 067/250] tools: k3_fit_atf: add DM binary to the FIT image Add DM (device manager) firmware image to the fit image that is loaded by R5 SPL. This is needed with the HSM rearch where the firmware allocation has been changed slightly. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/config.mk | 4 ++++ tools/k3_fit_atf.sh | 19 ++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index 67448906820..da458bcfb29 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -49,6 +49,10 @@ endif ifdef CONFIG_ARM64 +ifeq ($(CONFIG_SOC_K3_J721E),) +export DM := /dev/null +endif + ifeq ($(CONFIG_TI_SECURE_DEVICE),y) SPL_ITS := u-boot-spl-k3_HS.its $(SPL_ITS): export IS_HS=1 diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh index 2c0287a6339..3a476ced98b 100755 --- a/tools/k3_fit_atf.sh +++ b/tools/k3_fit_atf.sh @@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then TEE=/dev/null fi +[ -z "$DM" ] && DM="dm.bin" + +if [ ! -e $DM ]; then + echo "WARNING DM file $DM NOT found, resulting might be non-functional" >&2 + DM=/dev/null +fi + if [ ! -z "$IS_HS" ]; then HS_APPEND=_HS fi @@ -53,6 +60,16 @@ cat << __HEADER_EOF load = <0x9e800000>; entry = <0x9e800000>; }; + dm { + description = "DM binary"; + data = /incbin/("$DM"); + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0xa0000000>; + entry = <0xa0000000>; + }; spl { description = "SPL (64-bit)"; data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND"); @@ -94,7 +111,7 @@ do $(basename $dtname) { description = "$(basename $dtname .dtb)"; firmware = "atf"; - loadables = "tee", "spl"; + loadables = "tee", "dm", "spl"; fdt = "$(basename $dtname)"; }; __CONF_SECTION_EOF From 277729eaf373dd83287ff3e145735261b0fc9c93 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 11 Jun 2021 11:45:18 +0300 Subject: [PATCH 068/250] arm: mach-k3: Add platform data for j721e and j7200 Add platform clock and powerdomain data for J721e and J7200. This data is used by the corresponding drivers to register all the required device clocks and powerdomains. Signed-off-by: Dave Gerlach Signed-off-by: Tero Kristo --- arch/arm/mach-k3/Makefile | 2 +- arch/arm/mach-k3/j7200/Makefile | 5 + arch/arm/mach-k3/j7200/clk-data.c | 547 +++++++++++++++++++++ arch/arm/mach-k3/j7200/dev-data.c | 77 +++ arch/arm/mach-k3/j721e/Makefile | 5 + arch/arm/mach-k3/j721e/clk-data.c | 781 ++++++++++++++++++++++++++++++ arch/arm/mach-k3/j721e/dev-data.c | 75 +++ 7 files changed, 1491 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-k3/j7200/Makefile create mode 100644 arch/arm/mach-k3/j7200/clk-data.c create mode 100644 arch/arm/mach-k3/j7200/dev-data.c create mode 100644 arch/arm/mach-k3/j721e/Makefile create mode 100644 arch/arm/mach-k3/j721e/clk-data.c create mode 100644 arch/arm/mach-k3/j721e/dev-data.c diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 890d1498d0c..47cf7b6d17a 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -4,7 +4,7 @@ # Lokesh Vutla obj-$(CONFIG_SOC_K3_AM6) += am6_init.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o +obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile new file mode 100644 index 00000000000..ff9abd78ea6 --- /dev/null +++ b/arch/arm/mach-k3/j7200/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c new file mode 100644 index 00000000000..93c067079ab --- /dev/null +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific clock platform data + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi0_dqs_out", + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv2_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out14_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out4_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const wkup_obsclk_mux_out0_parents[] = { + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + NULL, + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv4_16fft_mcu_1_hsdivout1_clk", + "hsdiv4_16fft_mcu_1_hsdivout2_clk", + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "hsdiv4_16fft_mcu_2_hsdivout2_clk", + "hsdiv4_16fft_mcu_2_hsdivout3_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", + "gluelogic_hfosc0_clkout", + "board_0_wkup_lf_clkin_out", +}; + +static const char * const main_pll4_xref_sel_out0_parents[] = { + "main_pll_hfosc_sel_out4", + "board_0_ext_refclk1_out", +}; + +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const mcu_obsclk_outmux_out0_parents[] = { + "mcu_obsclk_div_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const clkout_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv2_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const obsclk1_mux_out0_parents[] = { + NULL, + "hsdiv0_16fft_main_8_hsdivout0_clk", + NULL, + NULL, +}; + +static const char * const gpmc_fclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout3_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const audio_refclko_mux_out0_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv2_16fft_main_4_hsdivout2_clk", + NULL, + NULL, + NULL, +}; + +static const char * const audio_refclko_mux_out1_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv2_16fft_main_4_hsdivout2_clk", + NULL, + NULL, + NULL, +}; + +static const char * const obsclk0_mux_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout0_clk", + "hsdiv4_16fft_main_1_hsdivout0_clk", + "hsdiv4_16fft_main_2_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv2_16fft_main_4_hsdivout0_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv0_16fft_main_12_hsdivout0_clk", + "obsclk1_mux_out0", + "hsdiv1_16fft_main_14_hsdivout0_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + "board_0_wkup_lf_clkin_out", + "hsdiv4_16fft_main_0_hsdivout0_clk", + "board_0_hfosc1_clk_out", + "gluelogic_hfosc0_clkout", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), + CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), + CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0), + CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), + CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), + CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0), + CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), + CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), + CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), + CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0), + CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0), + CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0), + CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0), + CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), + CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 1, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 10, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), + DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 7, "board_0_ext_refclk1_out"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"), + DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"), + DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 2, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 5, "osbclk0_div_out0"), + DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"), + DEV_CLK(157, 15, "mcu_obsclk_div_out0"), + DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 35, "clkout_mux_out0"), + DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 38, "osbclk0_div_out0"), + DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), + DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 69, "mcu_clkout_mux_out0"), + DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 77, "audio_refclko_mux_out1"), + DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"), + DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"), + DEV_CLK(157, 131, "audio_refclko_mux_out0"), + DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"), + DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 184, "gpmc_fclk_sel_out0"), + DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 192, "osbclk0_div_out0"), + DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"), + DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"), + DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(157, 206, "obsclk1_mux_out0"), + DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"), + DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"), + DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 223, "board_0_hfosc1_clk_out"), + DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"), + DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), + DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 12, "usb0_refclk_sel_out0"), + DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"), + DEV_CLK(288, 14, "board_0_hfosc1_clk_out"), + DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j7200_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 108, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 127, +}; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c new file mode 100644 index 00000000000..c68bcc58e9a --- /dev/null +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific device platform data + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]), + [2] = PSC_PD(14, &soc_psc_list[0], NULL), + [3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]), + [4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]), + [5] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[14]), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [7] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL), + [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL), + [9] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), + [10] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [11] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[8]), + [12] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL), + [13] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL), + [14] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL), + [15] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL), + [16] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[5], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(8, &soc_lpsc_list[3]), + PSC_DEV(288, &soc_lpsc_list[4]), + PSC_DEV(92, &soc_lpsc_list[5]), + PSC_DEV(91, &soc_lpsc_list[6]), + PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(4, &soc_lpsc_list[8]), + PSC_DEV(4, &soc_lpsc_list[9]), + PSC_DEV(202, &soc_lpsc_list[10]), + PSC_DEV(203, &soc_lpsc_list[11]), + PSC_DEV(102, &soc_lpsc_list[12]), + PSC_DEV(103, &soc_lpsc_list[12]), + PSC_DEV(104, &soc_lpsc_list[12]), + PSC_DEV(154, &soc_lpsc_list[12]), + PSC_DEV(149, &soc_lpsc_list[12]), + PSC_DEV(113, &soc_lpsc_list[13]), + PSC_DEV(197, &soc_lpsc_list[13]), + PSC_DEV(103, &soc_lpsc_list[14]), + PSC_DEV(104, &soc_lpsc_list[15]), + PSC_DEV(102, &soc_lpsc_list[16]), +}; + +const struct ti_k3_pd_platdata j7200_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 6, + .num_lpsc = 17, + .num_devs = 22, +}; diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile new file mode 100644 index 00000000000..ff9abd78ea6 --- /dev/null +++ b/arch/arm/mach-k3/j721e/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c new file mode 100644 index 00000000000..953ac457130 --- /dev/null +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific clock platform data + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi0_dqs_out", + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi1_dqs_out", + "fss_mcu_0_ospi_1_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll25_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out13_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out14_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out15_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out16_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out17_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out18_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out19_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out23_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out4_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out5_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out6_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const wkup_obsclk_mux_out0_parents[] = { + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + NULL, + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv4_16fft_mcu_1_hsdivout1_clk", + "hsdiv4_16fft_mcu_1_hsdivout2_clk", + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "hsdiv4_16fft_mcu_2_hsdivout2_clk", + "hsdiv4_16fft_mcu_2_hsdivout3_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", + "gluelogic_hfosc0_clkout", + "gluelogic_lpxosc_clkout", +}; + +static const char * const main_pll15_xref_sel_out0_parents[] = { + "main_pll_hfosc_sel_out15", + "board_0_ext_refclk1_out", +}; + +static const char * const main_pll24_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_mlb0_mlbcp_out", +}; + +static const char * const main_pll4_xref_sel_out0_parents[] = { + "main_pll_hfosc_sel_out4", + "board_0_ext_refclk1_out", +}; + +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const mcu_obsclk_outmux_out0_parents[] = { + "mcu_obsclk_div_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const obsclk1_mux_out0_parents[] = { + "hsdiv0_16fft_main_7_hsdivout0_clk", + "hsdiv0_16fft_main_8_hsdivout0_clk", + "hsdiv3_16fft_main_13_hsdivout0_clk", + NULL, +}; + +static const char * const clkout_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const gpmc_fclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout3_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const mcasp_ahclko_mux_out0_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk0_out", +}; + +static const char * const mcasp_ahclko_mux_out1_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk1_out", +}; + +static const char * const mcasp_ahclko_mux_out2_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk2_out", +}; + +static const char * const mcasp_ahclko_mux_out3_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk3_out", +}; + +static const char * const obsclk0_mux_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout0_clk", + "hsdiv4_16fft_main_1_hsdivout0_clk", + "hsdiv4_16fft_main_2_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv3_16fft_main_4_hsdivout0_clk", + "hsdiv3_16fft_main_5_hsdivout0_clk", + "hsdiv0_16fft_main_6_hsdivout0_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv0_16fft_main_12_hsdivout0_clk", + "obsclk1_mux_out0", + "hsdiv1_16fft_main_14_hsdivout0_clk", + "hsdiv3_16fft_main_15_hsdivout0_clk", + "hsdiv1_16fft_main_16_hsdivout0_clk", + "hsdiv1_16fft_main_17_hsdivout0_clk", + "hsdiv1_16fft_main_18_hsdivout0_clk", + "hsdiv1_16fft_main_19_hsdivout0_clk", + NULL, + NULL, + NULL, + "hsdiv1_16fft_main_23_hsdivout0_clk", + "hsdiv0_16fft_main_24_hsdivout0_clk", + "hsdiv1_16fft_main_25_hsdivout0_clk", + NULL, + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + "gluelogic_lpxosc_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", + "board_0_hfosc1_clk_out", + "gluelogic_hfosc0_clkout", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0), + CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), + CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0), + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0), + CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0), + CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0), + CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0), + CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0), + CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), + CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0), + CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0), + CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0), + CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0), + CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0), + CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), + CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0), + CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), + CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), + CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), + CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0), + CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0), + CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0), + CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0), + CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0), + CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0), + CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0), + CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), + CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 1, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 10, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), + DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 7, "board_0_ext_refclk1_out"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"), + DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"), + DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 0, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"), + DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), + DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"), + DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"), + DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 104, "gpmc_fclk_sel_out0"), + DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"), + DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"), + DEV_CLK(157, 113, "osbclk0_div_out0"), + DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"), + DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"), + DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"), + DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"), + DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(157, 127, "obsclk1_mux_out0"), + DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"), + DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"), + DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"), + DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"), + DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"), + DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"), + DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"), + DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"), + DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"), + DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"), + DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 144, "board_0_hfosc1_clk_out"), + DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 146, "obsclk1_mux_out0"), + DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"), + DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"), + DEV_CLK(157, 153, "mcu_obsclk_div_out0"), + DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"), + DEV_CLK(157, 172, "clkout_mux_out0"), + DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 175, "mcu_clkout_mux_out0"), + DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"), + DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"), + DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"), + DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"), + DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"), + DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"), + DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"), + DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"), + DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), + DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 15, "usb0_refclk_sel_out0"), + DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"), + DEV_CLK(288, 17, "board_0_hfosc1_clk_out"), + DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), + DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 15, "usb1_refclk_sel_out0"), + DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"), + DEV_CLK(289, 17, "board_0_hfosc1_clk_out"), + DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j721e_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 156, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 171, +}; diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c new file mode 100644 index 00000000000..96393c71327 --- /dev/null +++ b/arch/arm/mach-k3/j721e/dev-data.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific device platform data + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(14, &soc_psc_list[0], NULL), + [2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]), + [4] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [7] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL), + [9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), + [10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL), + [12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL), + [13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL), + [14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL), + [15] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[4], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(146, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(47, &soc_lpsc_list[3]), + PSC_DEV(288, &soc_lpsc_list[4]), + PSC_DEV(289, &soc_lpsc_list[5]), + PSC_DEV(92, &soc_lpsc_list[6]), + PSC_DEV(91, &soc_lpsc_list[7]), + PSC_DEV(4, &soc_lpsc_list[8]), + PSC_DEV(202, &soc_lpsc_list[9]), + PSC_DEV(203, &soc_lpsc_list[10]), + PSC_DEV(102, &soc_lpsc_list[11]), + PSC_DEV(103, &soc_lpsc_list[11]), + PSC_DEV(104, &soc_lpsc_list[11]), + PSC_DEV(154, &soc_lpsc_list[11]), + PSC_DEV(149, &soc_lpsc_list[11]), + PSC_DEV(113, &soc_lpsc_list[12]), + PSC_DEV(197, &soc_lpsc_list[12]), + PSC_DEV(103, &soc_lpsc_list[13]), + PSC_DEV(104, &soc_lpsc_list[14]), + PSC_DEV(102, &soc_lpsc_list[15]), +}; + +const struct ti_k3_pd_platdata j721e_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 5, + .num_lpsc = 16, + .num_devs = 22, +}; From 547b277cd9252408bc7b12abaacda01e3b6e2eba Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:19 +0300 Subject: [PATCH 069/250] arm: mach-k3: add support for detecting firmware images from FIT Add callback routines for parsing the firmware info from FIT image, and use the data to boot up ATF and the MCU R5 firmware. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/common.c | 84 +++++++++++++++++++++++++++++++++---- arch/arm/mach-k3/common.h | 1 + arch/arm/mach-k3/security.c | 3 +- 3 files changed, 78 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 9191f686f05..0a1638ee044 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -28,6 +28,27 @@ #include #include +#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) +enum { + IMAGE_ID_ATF, + IMAGE_ID_OPTEE, + IMAGE_ID_SPL, + IMAGE_ID_DM_FW, + IMAGE_AMT, +}; + +#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) +static const char *image_os_match[IMAGE_AMT] = { + "arm-trusted-firmware", + "tee", + "U-Boot", + "DM", +}; +#endif + +static struct image_info fit_image_info[IMAGE_AMT]; +#endif + struct ti_sci_handle *get_ti_sci_handle(void) { struct udevice *dev; @@ -107,7 +128,7 @@ int early_console_init(void) } #endif -#ifdef CONFIG_SYS_K3_SPL_ATF +#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) void init_env(void) { @@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) typedef void __noreturn (*image_entry_noargs_t)(void); struct ti_sci_handle *ti_sci = get_ti_sci_handle(); u32 loadaddr = 0; - int ret, size; + int ret, size = 0; /* Release all the exclusive devices held by SPL before starting ATF */ ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci); @@ -192,15 +213,20 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) init_env(); start_non_linux_remote_cores(); - size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load", - &loadaddr); + if (!fit_image_info[IMAGE_ID_DM_FW].image_start) + size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load", + &loadaddr); /* * It is assumed that remoteproc device 1 is the corresponding * Cortex-A core which runs ATF. Make sure DT reflects the same. */ - ret = rproc_load(1, spl_image->entry_point, 0x200); + if (!fit_image_info[IMAGE_ID_ATF].image_start) + fit_image_info[IMAGE_ID_ATF].image_start = + spl_image->entry_point; + + ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200); if (ret) panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); @@ -210,7 +236,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) ret = rproc_start(1); if (ret) panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); - if (!(size > 0 && valid_elf_image(loadaddr))) { + if (!fit_image_info[IMAGE_ID_DM_FW].image_len && + !(size > 0 && valid_elf_image(loadaddr))) { debug("Shutting down...\n"); release_resources_for_core_shutdown(); @@ -218,13 +245,54 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) asm volatile("wfe"); } - image_entry_noargs_t image_entry = - (image_entry_noargs_t)load_elf_image_phdr(loadaddr); + if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { + loadaddr = load_elf_image_phdr(loadaddr); + } else { + loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start; + if (valid_elf_image(loadaddr)) + loadaddr = load_elf_image_phdr(loadaddr); + } + + debug("%s: jumping to address %x\n", __func__, loadaddr); + + image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr; image_entry(); } #endif +#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) +{ +#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) + int len; + int i; + const char *os; + u32 addr; + + os = fdt_getprop(fit, node, "os", &len); + addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1); + + debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__, + addr, *p_size, os); + + for (i = 0; i < IMAGE_AMT; i++) { + if (!strcmp(os, image_os_match[i])) { + fit_image_info[i].image_start = addr; + fit_image_info[i].image_len = *p_size; + debug("%s: matched image for ID %d\n", __func__, i); + break; + } + } +#endif + +#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE) + ti_secure_image_post_process(p_image, p_size); +#endif +} +#endif + #if defined(CONFIG_OF_LIBFDT) int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name) { diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index a6dbc7808b8..f421ed1bb18 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -28,3 +28,4 @@ void k3_sysfw_print_ver(void); void spl_enable_dcache(void); void mmr_unlock(phys_addr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); +void ti_secure_image_post_process(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 5b5ff9ba7b3..8de9739a401 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -18,8 +18,7 @@ #include #include -void board_fit_image_post_process(const void *fit, int node, void **p_image, - size_t *p_size) +void ti_secure_image_post_process(void **p_image, size_t *p_size) { struct ti_sci_handle *ti_sci = get_ti_sci_handle(); struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; From 0714580346cc0b3999d62e0949b17561a965a24b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:20 +0300 Subject: [PATCH 070/250] arm: mach-k3: do board config for PM only if supported If the raw PM support is built in, we are operating in the split firmware approach mode where PM support is not available. In this case, skip the board config for this. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/sysfw-loader.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 0bacfc4d077..41449db89d3 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit, ret); /* Apply power/clock (PM) specific configuration to SYSFW */ +#if !CONFIG_IS_ENABLED(K3_DM_FW) ret = board_ops->board_config_pm(ti_sci, (u64)(u32)cfg_fragment_addr, (u32)cfg_fragment_size); if (ret) panic("Failed to set board PM configuration (%d)\n", ret); +#endif /* Extract resource management (RM) specific configuration from FIT */ ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM, From 7acd4d7142e989785ef4e7f7dfcf9ff9fd589074 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 11 Jun 2021 11:45:21 +0300 Subject: [PATCH 071/250] arm: mach-k3: common: Drop main r5 start Only start-up the non-linux remote cores if we are running in legacy boot mode. HSM rearch is not yet supporting this. Signed-off-by: Dave Gerlach Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 0a1638ee044..ab6d9bd3d0e 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -212,11 +212,12 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) panic("rproc failed to be initialized (%d)\n", ret); init_env(); - start_non_linux_remote_cores(); - if (!fit_image_info[IMAGE_ID_DM_FW].image_start) + + if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { + start_non_linux_remote_cores(); size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load", &loadaddr); - + } /* * It is assumed that remoteproc device 1 is the corresponding From 925698daaca552729701935743791a9c737152ed Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:22 +0300 Subject: [PATCH 072/250] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver Copy the contents of the board config loaded from sysfw.itb into an EXTBOOT shared memory buffer that gets passed to sciserver. This only needs to be done if EXTBOOT area has not been populated by ROM code yet. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/sysfw-loader.c | 113 ++++++++++++++++++++++++++++++-- 1 file changed, 106 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 41449db89d3..d213e06afbb 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR; */ #define K3_SYSTEM_CONTROLLER_RPROC_ID 0 +#define COMMON_HEADER_ADDRESS 0x41cffb00 +#define BOARDCFG_ADDRESS 0x41c80000 + +#define COMP_TYPE_SBL_DATA 0x11 +#define DESC_TYPE_BOARDCFG_PM_INDEX 0x2 +#define DESC_TYPE_BOARDCFG_RM_INDEX 0x3 + +#define BOARD_CONFIG_RM_DESC_TYPE 0x000c +#define BOARD_CONFIG_PM_DESC_TYPE 0x000e + +struct extboot_comp { + u32 comp_type; + u32 boot_core; + u32 comp_opts; + u64 dest_addr; + u32 comp_size; +}; + +struct extboot_header { + u8 magic[8]; + u32 num_comps; + struct extboot_comp comps[5]; + u32 reserved; +}; + +struct bcfg_desc { + u16 type; + u16 offset; + u16 size; + u8 devgrp; + u8 reserved; +} __packed; + +struct bcfg_header { + u8 num_elems; + u8 sw_rev; + struct bcfg_desc descs[4]; + u16 reserved; +} __packed; + static bool sysfw_loaded; static void *sysfw_load_address; @@ -131,6 +171,13 @@ static void k3_sysfw_configure_using_fit(void *fit, const void *cfg_fragment_addr; size_t cfg_fragment_size; int ret; + u8 *buf; + struct extboot_header *common_header; + struct bcfg_header *bcfg_header; + struct extboot_comp *comp; + struct bcfg_desc *desc; + u32 addr; + bool copy_bcfg = false; /* Find the node holding the images information */ images = fdt_path_offset(fit, FIT_IMAGES_PATH); @@ -159,13 +206,53 @@ static void k3_sysfw_configure_using_fit(void *fit, ret); /* Apply power/clock (PM) specific configuration to SYSFW */ -#if !CONFIG_IS_ENABLED(K3_DM_FW) - ret = board_ops->board_config_pm(ti_sci, - (u64)(u32)cfg_fragment_addr, - (u32)cfg_fragment_size); - if (ret) - panic("Failed to set board PM configuration (%d)\n", ret); -#endif + if (!IS_ENABLED(CONFIG_K3_DM_FW)) { + ret = board_ops->board_config_pm(ti_sci, + (u64)(u32)cfg_fragment_addr, + (u32)cfg_fragment_size); + if (ret) + panic("Failed to set board PM configuration (%d)\n", ret); + } else { + /* Initialize shared memory boardconfig buffer */ + buf = (u8 *)COMMON_HEADER_ADDRESS; + common_header = (struct extboot_header *)buf; + + /* Check if we have a struct populated by ROM in memory already */ + if (strcmp((char *)common_header->magic, "EXTBOOT")) + copy_bcfg = true; + + if (copy_bcfg) { + strcpy((char *)common_header->magic, "EXTBOOT"); + common_header->num_comps = 1; + + comp = &common_header->comps[0]; + + comp->comp_type = COMP_TYPE_SBL_DATA; + comp->boot_core = 0x10; + comp->comp_opts = 0; + addr = (u32)BOARDCFG_ADDRESS; + comp->dest_addr = addr; + comp->comp_size = sizeof(*bcfg_header); + + bcfg_header = (struct bcfg_header *)addr; + + bcfg_header->num_elems = 2; + bcfg_header->sw_rev = 0; + + desc = &bcfg_header->descs[0]; + + desc->type = BOARD_CONFIG_PM_DESC_TYPE; + desc->offset = sizeof(*bcfg_header); + desc->size = cfg_fragment_size; + comp->comp_size += desc->size; + desc->devgrp = 0; + desc->reserved = 0; + memcpy((u8 *)bcfg_header + desc->offset, + cfg_fragment_addr, cfg_fragment_size); + + bcfg_header->descs[1].offset = desc->offset + desc->size; + } + } /* Extract resource management (RM) specific configuration from FIT */ ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM, @@ -174,6 +261,18 @@ static void k3_sysfw_configure_using_fit(void *fit, panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM, ret); + if (copy_bcfg) { + desc = &bcfg_header->descs[1]; + + desc->type = BOARD_CONFIG_RM_DESC_TYPE; + desc->size = cfg_fragment_size; + comp->comp_size += desc->size; + desc->devgrp = 0; + desc->reserved = 0; + memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr, + cfg_fragment_size); + } + /* Apply resource management (RM) configuration to SYSFW */ ret = board_ops->board_config_rm(ti_sci, (u64)(u32)cfg_fragment_addr, From 61305e00c704aa3c4ccf73598074ada4e55185fd Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 11 Jun 2021 11:45:23 +0300 Subject: [PATCH 073/250] arm: mach-k3: j721e_init: Force early probe of clk-k3 driver Force the clk-k3 driver to probe early during R5 SPL boot to ensure the default system clock configuration is completed. Many other drivers assume a default state of the clock tree and it is currently possible for them to probe before clk-k3 depending on the exact system configuration. Signed-off-by: Dave Gerlach Reported-by: Keerthy Tested-by: Keerthy Signed-off-by: Tero Kristo --- arch/arm/mach-k3/j721e_init.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 76a04a9035d..e9e076c9e72 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -180,6 +180,18 @@ void board_init_f(ulong dummy) k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock, k3_mmc_restart_clock); + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + panic("Failed to initialize clk-k3!\n"); + } + /* Prepare console output */ preloader_console_init(); From a95f8c07815994ae6ab14597aa263c833797099a Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:24 +0300 Subject: [PATCH 074/250] configs: j721e_evm_r5: Enable raw access power management features Sysfw is not going to provide access to power management features in the new architecture, so SPL must implement these itself. Enable all the raw register access based clock + power domain drivers. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- configs/j721e_evm_r5_defconfig | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 8ebbe7348f6..8a9b20141bc 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +# CONFIG_CLK_TI_SCI is not set CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -102,7 +102,7 @@ CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65941=y CONFIG_DM_REGULATOR=y @@ -140,3 +140,11 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y From 6cfb6ff3379c47b0bc2001a71628386783c724c5 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 11 Jun 2021 11:45:25 +0300 Subject: [PATCH 075/250] configs: j7200_evm_r5: Enable raw access power management features Sysfw is not going to provide access to power management features in the new architecture, so SPL must implement these itself. Enable all the raw register access based clock + power domain drivers. Signed-off-by: Dave Gerlach Signed-off-by: Tero Kristo --- configs/j7200_evm_r5_defconfig | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 08fad3e04b1..5c51bd5ae71 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +# CONFIG_CLK_TI_SCI is not set CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -110,7 +110,7 @@ CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y @@ -142,3 +142,13 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y From c3ebc56e2dca4a5db1cfc2268c7822504185fd30 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:26 +0300 Subject: [PATCH 076/250] board: ti: j72xx: README: update build instructions and image formats Update build instructions and image formats based on HSM rearch. A new DM image is added into the build, which gets executed right after R5 SPL finishes its job. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- board/ti/j721e/README | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/board/ti/j721e/README b/board/ti/j721e/README index c33afa496e7..b1c9145c92f 100644 --- a/board/ti/j721e/README +++ b/board/ti/j721e/README @@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow: | | | | +-------------+ | | | | | |<--------|---| Start A72 | | | | | | | | | and jump to | | | | -| | | | | next image | | | | +| | | | | DM fw image | | | | | | | | +-------------+ | | | | | | | | +-----------+ | | | | |---------|-----------------------|---->| Reset rls | | | | | | | | +-----------+ | | -| | DMSC | | | : | | +| | TIFS | | | : | | | |Services | | | +-----------+ | | | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | | | | | | +-----------+ | | @@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 4.2. A72: $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72 -$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72 +$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM= O=/tmp/a72 Target Images -------------- @@ -197,6 +197,9 @@ Image formats: | | A72 OPTEE | | | +-------------------+ | | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | | | A72 SPL | | | +-------------------+ | | | | | From bb318d8dc801586b5e587f7f7d508ad54022fb4b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 11 Jun 2021 11:45:27 +0300 Subject: [PATCH 077/250] arm: dts: k3-j72xx: correct MCU timer1 frequency MCU timer1 is used as the tick timer for MCU R5 SPL, and the clock-frequency defined in DT appears to be incorrect at the moment. Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz. Earlier setup of 25MHz went unnoticed, as there was a separate issue with omap-timer, which caused an error to the clock by a factor of 8 with j7 devices. This problem surfaced once the omap-timer was fixed. Signed-off-by: Tero Kristo --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +- arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index bd037be3504..c3aae65b395 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -33,7 +33,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x40400000 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000000>; + clock-frequency = <250000000>; u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index fe095a6153e..951331831e9 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -46,7 +46,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x40400000 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000000>; + clock-frequency = <250000000>; u-boot,dm-spl; }; From 5d80f1becf721d1e9bb2e17a9074064aaffaf528 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:47 +0530 Subject: [PATCH 078/250] mailbox: k3-sec-proxy: Add DM to DMSC communication thread R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads. Mark these as valid threads in the driver. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-2-vigneshr@ti.com --- drivers/mailbox/k3-sec-proxy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 88f320515ae..20fdb09f314 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -409,7 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev) return 0; } -static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 }; +static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 }; static const struct k3_sec_proxy_desc am654_desc = { .thread_count = 90, From 0e81158b76ad4c07fedee901cef52339249dbfdf Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:48 +0530 Subject: [PATCH 079/250] firmware: ti_sci: Implement GET_RANGE with static data In case of R5 SPL, GET_RANGE API service is not available (as DM services are not yet up), therefore service such calls locally using per SoC static data. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-3-vigneshr@ti.com --- drivers/firmware/ti_sci.c | 36 +++++++++++ drivers/firmware/ti_sci_static_data.h | 92 +++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 drivers/firmware/ti_sci_static_data.h diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 4671a5e3a8a..0318da208e6 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -23,6 +23,7 @@ #include #include "ti_sci.h" +#include "ti_sci_static_data.h" /* List of all TI SCI devices active in system */ static LIST_HEAD(ti_sci_list); @@ -1668,6 +1669,33 @@ fail: return ret; } +static int __maybe_unused +ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start, + u16 *range_num) +{ + struct ti_sci_resource_static_data *data; + int i = 0; + + while (1) { + data = &rm_static_data[i]; + + if (!data->dev_id) + return -EINVAL; + + if (data->dev_id != dev_id || data->subtype != subtype) { + i++; + continue; + } + + *range_start = data->range_start; + *range_num = data->range_num; + + return 0; + } + + return -EINVAL; +} + /** * ti_sci_cmd_get_resource_range - Get a range of resources assigned to host * that is same as ti sci interface host. @@ -1684,6 +1712,11 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u16 *range_start, u16 *range_num) { + if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) + return ti_sci_get_resource_range_static(dev_id, subtype, + range_start, + range_num); + return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, range_start, range_num); @@ -1707,6 +1740,9 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, u16 *range_start, u16 *range_num) { + if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) + return -EINVAL; + return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, range_start, range_num); } diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h new file mode 100644 index 00000000000..3c506e667ac --- /dev/null +++ b/drivers/firmware/ti_sci_static_data.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * + */ + +#ifndef __TI_SCI_STATIC_DATA_H +#define __TI_SCI_STATIC_DATA_H + +struct ti_sci_resource_static_data { + u32 dev_id; + u16 range_start; + u16 range_num; + u8 subtype; +}; + +#if IS_ENABLED(CONFIG_K3_DM_FW) + +#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM) +static struct ti_sci_resource_static_data rm_static_data[] = { + /* Free rings */ + { + .dev_id = 235, + .subtype = 1, + .range_start = 124, + .range_num = 32, + }, + /* TX channels */ + { + .dev_id = 236, + .subtype = 13, + .range_start = 6, + .range_num = 2, + }, + /* RX channels */ + { + .dev_id = 236, + .subtype = 10, + .range_start = 6, + .range_num = 2, + }, + /* RX Free flows */ + { + .dev_id = 236, + .subtype = 0, + .range_start = 60, + .range_num = 8, + }, + { }, +}; +#endif /* CONFIG_TARGET_J721E_R5_EVM */ + +#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM) +static struct ti_sci_resource_static_data rm_static_data[] = { + /* Free rings */ + { + .dev_id = 235, + .subtype = 1, + .range_start = 144, + .range_num = 32, + }, + /* TX channels */ + { + .dev_id = 236, + .subtype = 13, + .range_start = 7, + .range_num = 2, + }, + /* RX channels */ + { + .dev_id = 236, + .subtype = 10, + .range_start = 7, + .range_num = 2, + }, + /* RX Free flows */ + { + .dev_id = 236, + .subtype = 0, + .range_start = 60, + .range_num = 8, + }, + { }, +}; +#endif /* CONFIG_TARGET_J7200_R5_EVM */ + +#else +static struct ti_sci_resource_static_data rm_static_data[] = { + { }, +}; +#endif /* CONFIG_K3_DM_FW */ +#endif /* __TI_SCI_STATIC_DATA_H */ From 5d5a699855a704646b10c4f04dc9ce0650ceace3 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:49 +0530 Subject: [PATCH 080/250] firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. On J721e and J7200, MCU R5 core (boot master) itself would run Device Manager (DM) Firmware and interact with TI Foundational Security (TIFS) firmware to enable DMA and such other Resource Management (RM) services. So, during R5 SPL stage there is no such RM service available and ti_sci driver will have to directly interact with TIFS using DM to DMSC channels to request RM resources. Therefore add DT binding and driver for the same. This driver will handle Resource Management services at R5 SPL stage. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com --- .../firmware/ti,j721e-dm-sci.txt | 32 +++++++ drivers/firmware/ti_sci.c | 91 +++++++++++++++++-- 2 files changed, 113 insertions(+), 10 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt diff --git a/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt new file mode 100644 index 00000000000..0217341f0c3 --- /dev/null +++ b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt @@ -0,0 +1,32 @@ +Bindings for Texas Instruments System Control Interface (TI-SCI) Message +Protocol for Device Manager(DM) to TI Foundational Security(TIFS) +Firmware communication + +Required properties: +-------------------- +- compatible: should be "ti,j721e-dm-sci" +- mbox-names: + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + +- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes + property should contain a phandle to the mailbox controller device + node and an args specifier that will be the phandle to the intended + sub-mailbox child node to be used for communication. + +- ti,host-id: Host ID to use for communication. + +Optional Properties: +-------------------- +- ti,secure-host: If the host is defined as secure. + +Example: +-------- + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + }; diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 0318da208e6..0b6ba35b596 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1670,8 +1670,9 @@ fail: } static int __maybe_unused -ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start, - u16 *range_num) +ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle, + u32 dev_id, u8 subtype, + u16 *range_start, u16 *range_num) { struct ti_sci_resource_static_data *data; int i = 0; @@ -1712,11 +1713,6 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u16 *range_start, u16 *range_num) { - if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) - return ti_sci_get_resource_range_static(dev_id, subtype, - range_start, - range_num); - return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, range_start, range_num); @@ -1740,9 +1736,6 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, u16 *range_start, u16 *range_num) { - if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) - return -EINVAL; - return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, range_start, range_num); } @@ -3052,6 +3045,58 @@ static int ti_sci_probe(struct udevice *dev) return ret; } +/** + * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI + * @dev: corresponding system controller interface device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static __maybe_unused int ti_sci_dm_probe(struct udevice *dev) +{ + struct ti_sci_rm_core_ops *rm_core_ops; + struct ti_sci_rm_udmap_ops *udmap_ops; + struct ti_sci_rm_ringacc_ops *rops; + struct ti_sci_rm_psil_ops *psilops; + struct ti_sci_ops *ops; + struct ti_sci_info *info; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + info = dev_get_priv(dev); + info->desc = (void *)dev_get_driver_data(dev); + + ret = ti_sci_of_to_info(dev, info); + if (ret) { + dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret); + return ret; + } + + info->dev = dev; + info->seq = 0xA; + + list_add_tail(&info->list, &ti_sci_list); + + ops = &info->handle.ops; + + rm_core_ops = &ops->rm_core_ops; + rm_core_ops->get_range = ti_sci_cmd_get_resource_range_static; + + rops = &ops->rm_ring_ops; + rops->config = ti_sci_cmd_ring_config; + + psilops = &ops->rm_psil_ops; + psilops->pair = ti_sci_cmd_rm_psil_pair; + psilops->unpair = ti_sci_cmd_rm_psil_unpair; + + udmap_ops = &ops->rm_udmap_ops; + udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg; + udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg; + udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg; + + return ret; +} + /* * ti_sci_get_free_resource() - Get a free resource from TISCI resource. * @res: Pointer to the TISCI resource @@ -3189,6 +3234,14 @@ static const struct ti_sci_desc ti_sci_pmmc_am654_desc = { .max_msg_size = 60, }; +/* Description for J721e DM to DMSC communication */ +static const struct ti_sci_desc ti_sci_dm_j721e_desc = { + .default_host_id = 3, + .max_rx_timeout_ms = 10000, + .max_msgs = 20, + .max_msg_size = 60, +}; + static const struct udevice_id ti_sci_ids[] = { { .compatible = "ti,k2g-sci", @@ -3201,6 +3254,14 @@ static const struct udevice_id ti_sci_ids[] = { { /* Sentinel */ }, }; +static __maybe_unused const struct udevice_id ti_sci_dm_ids[] = { + { + .compatible = "ti,j721e-dm-sci", + .data = (ulong)&ti_sci_dm_j721e_desc + }, + { /* Sentinel */ }, +}; + U_BOOT_DRIVER(ti_sci) = { .name = "ti_sci", .id = UCLASS_FIRMWARE, @@ -3208,3 +3269,13 @@ U_BOOT_DRIVER(ti_sci) = { .probe = ti_sci_probe, .priv_auto = sizeof(struct ti_sci_info), }; + +#if IS_ENABLED(CONFIG_K3_DM_FW) +U_BOOT_DRIVER(ti_sci_dm) = { + .name = "ti_sci_dm", + .id = UCLASS_FIRMWARE, + .of_match = ti_sci_dm_ids, + .probe = ti_sci_dm_probe, + .priv_auto = sizeof(struct ti_sci_info), +}; +#endif From 00d6fc9c71e53ea2627e022ea55e02c0c676ad9c Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:50 +0530 Subject: [PATCH 081/250] ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node Add DM firmware node which will provide DM services during R5 SPL stage. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 17 +++++++++++++++++ arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 69d8600c19f..8dc18099798 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -79,6 +79,16 @@ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; mbox-names = "tx", "rx"; }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + u-boot,dm-spl; + }; }; &dmsc { @@ -276,4 +286,11 @@ }; }; +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; #include "k3-j7200-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 4e8422e6624..0542b2f8b88 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -76,6 +76,16 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + u-boot,dm-spl; + }; }; &cbass_main { @@ -345,3 +355,11 @@ u-boot,dm-spl; }; }; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; From 2af181b53e286e90c3b36ba608c1c7b209e8ad8e Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:51 +0530 Subject: [PATCH 082/250] ARM: dts: k3: Add cfg register space for ringacc and udmap R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Note that these registers are present within respective IPs but are not populated in Linux DT nodes (as they are configured via TISCI APIs) and hence are added to -u-boot.dtsi for now. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ 3 files changed, 54 insertions(+) diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index b0602d1dad2..28402585182 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -35,11 +35,25 @@ u-boot,dm-spl; ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; ti,dma-ring-reset-quirk; }; dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index c3aae65b395..41ce9fcb59b 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -40,6 +40,32 @@ chipid@43000014 { u-boot,dm-spl; }; + + mcu-navss{ + u-boot,dm-spl; + + ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + u-boot,dm-spl; + }; + + dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + u-boot,dm-spl; + }; + }; }; &secure_proxy_main { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 951331831e9..974dae84161 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -54,10 +54,24 @@ u-boot,dm-spl; ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; }; dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; }; From 86e58800fd7cdba4fa9229aeee3a54a2ccece406 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:52 +0530 Subject: [PATCH 083/250] soc: ti: k3-navss-ringacc: Add support for native configuration of rings In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup Ring Cfg registers. Add support for the same. Note that we still need to send RING_CFG message to TIFS via TISCI client driver in order to open up firewalls around Rings. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-7-vigneshr@ti.com --- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 ++++++++++++++++++++++++ drivers/soc/ti/k3-navss-ringacc.c | 36 ++++++++++++-- 2 files changed, 94 insertions(+), 3 deletions(-) create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c new file mode 100644 index 00000000000..f958239c2af --- /dev/null +++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator + * Manager (RA) subsystem driver + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +struct k3_nav_ring_cfg_regs { + u32 resv_64[16]; + u32 ba_lo; /* Ring Base Address Lo Register */ + u32 ba_hi; /* Ring Base Address Hi Register */ + u32 size; /* Ring Size Register */ + u32 event; /* Ring Event Register */ + u32 orderid; /* Ring OrderID Register */ +}; + +#define KNAV_RINGACC_CFG_REGS_STEP 0x100 + +#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0) + +#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30) +#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30) + +#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24) +#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24) + +static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring) +{ + writel(0, &ring->cfg->size); +} + +static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode) +{ + u32 val; + + val = readl(&ring->cfg->size); + val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; + val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT; + writel(val, &ring->cfg->size); +} + +static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring) +{ + writel(0, &ring->cfg->ba_hi); + writel(0, &ring->cfg->ba_lo); + writel(0, &ring->cfg->size); +} + +static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring) +{ + u32 val; + + writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo); + writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi); + + val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT | + ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT | + ring->size; + writel(val, &ring->cfg->size); +} diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index b5a5c9da98a..f110d78ce10 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -124,6 +124,7 @@ struct k3_nav_ring_state { /** * struct k3_nav_ring - RA Ring descriptor * + * @cfg - Ring configuration registers * @rt - Ring control/status registers * @fifos - Ring queues registers * @ring_mem_dma - Ring buffer dma address @@ -138,6 +139,7 @@ struct k3_nav_ring_state { * @use_count - Use count for shared rings */ struct k3_nav_ring { + struct k3_nav_ring_cfg_regs __iomem *cfg; struct k3_nav_ring_rt_regs __iomem *rt; struct k3_nav_ring_fifo_regs __iomem *fifos; dma_addr_t ring_mem_dma; @@ -195,6 +197,8 @@ struct k3_nav_ringacc { bool dual_ring; }; +#include "k3-navss-ringacc-u-boot.c" + static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring) { return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK; @@ -330,6 +334,9 @@ static void k3_ringacc_ring_reset_sci(struct k3_nav_ring *ring) struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_reset_raw(ring); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID, @@ -362,6 +369,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_nav_ring *ring, struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_reconfig_qmode_raw(ring, mode); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_RING_MODE_VALID, @@ -442,6 +452,9 @@ static void k3_ringacc_ring_free_sci(struct k3_nav_ring *ring) struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_free_raw(ring); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER, @@ -531,11 +544,21 @@ static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring) ring->mode, ring->elm_size, 0); - if (ret) + if (ret) { dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", ret, ring_idx); + return ret; + } - return ret; + /* + * Above TI SCI call handles firewall configuration, cfg + * register configuration still has to be done locally in + * absence of RM services. + */ + if (IS_ENABLED(CONFIG_K3_DM_FW)) + k3_nav_ringacc_ring_cfg_raw(ring); + + return 0; } static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg) @@ -951,13 +974,18 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc) static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc) { - void __iomem *base_rt; + void __iomem *base_cfg, *base_rt; int ret, i; ret = k3_nav_ringacc_probe_dt(ringacc); if (ret) return ret; + base_cfg = dev_remap_addr_name(dev, "cfg"); + pr_debug("cfg %p\n", base_cfg); + if (!base_cfg) + return -EINVAL; + base_rt = (uint32_t *)devfdt_get_addr_name(dev, "rt"); pr_debug("rt %p\n", base_rt); if (IS_ERR(base_rt)) @@ -975,6 +1003,8 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa return -ENOMEM; for (i = 0; i < ringacc->num_rings; i++) { + ringacc->rings[i].cfg = base_cfg + + KNAV_RINGACC_CFG_REGS_STEP * i; ringacc->rings[i].rt = base_rt + KNAV_RINGACC_RT_REGS_STEP * i; ringacc->rings[i].parent = ringacc; From 5abb694d6016eaf497c3d9a3ec79382e217e7508 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:47:53 +0530 Subject: [PATCH 084/250] dma: ti: k3-udma: Add support for native configuration of chan/flow In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers. Add support for the same. Note that we still need to send chan/flow cfg message to TIFS via TISCI client driver in order to open up firewalls around chan/flow but setting up of cfg registers is handled locally. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210607141753.28796-8-vigneshr@ti.com --- drivers/dma/ti/k3-udma-u-boot.c | 177 ++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 42 +++++++- 2 files changed, 215 insertions(+), 4 deletions(-) create mode 100644 drivers/dma/ti/k3-udma-u-boot.c diff --git a/drivers/dma/ti/k3-udma-u-boot.c b/drivers/dma/ti/k3-udma-u-boot.c new file mode 100644 index 00000000000..3e04f551e29 --- /dev/null +++ b/drivers/dma/ti/k3-udma-u-boot.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT (16) + +/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ +#define UDMA_RFLOW_SRCTAG_NONE 0 +#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 +#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 +#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 + +#define UDMA_RFLOW_DSTTAG_NONE 0 +#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 +#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 +#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 +#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 + +#define UDMA_RFLOW_RFC_DEFAULT \ + ((UDMA_RFLOW_SRCTAG_NONE << UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \ + (UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \ + (UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT) | \ + (UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT)) + +#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT (16) + +/* TCHAN */ +static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg) +{ + if (!tchan) + return 0; + return udma_read(tchan->reg_chan, reg); +} + +static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val) +{ + if (!tchan) + return; + udma_write(tchan->reg_chan, reg, val); +} + +static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg, + u32 mask, u32 val) +{ + if (!tchan) + return; + udma_update_bits(tchan->reg_chan, reg, mask, val); +} + +/* RCHAN */ +static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg) +{ + if (!rchan) + return 0; + return udma_read(rchan->reg_chan, reg); +} + +static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val) +{ + if (!rchan) + return; + udma_write(rchan->reg_chan, reg, val); +} + +static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg, + u32 mask, u32 val) +{ + if (!rchan) + return; + udma_update_bits(rchan->reg_chan, reg, mask, val); +} + +/* RFLOW */ +static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg) +{ + if (!rflow) + return 0; + return udma_read(rflow->reg_rflow, reg); +} + +static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val) +{ + if (!rflow) + return; + udma_write(rflow->reg_rflow, reg, val); +} + +static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg, + u32 mask, u32 val) +{ + if (!rflow) + return; + udma_update_bits(rflow->reg_rflow, reg, mask, val); +} + +static void udma_alloc_tchan_raw(struct udma_chan *uc) +{ + u32 mode, fetch_size; + + if (uc->config.pkt_mode) + mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR; + else + mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR; + + udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG, + UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode); + + if (uc->config.dir == DMA_MEM_TO_MEM) + fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + else + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0) >> 2; + + udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG, + UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size); + udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG, + k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring)); +} + +static void udma_alloc_rchan_raw(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring); + int rx_ring = k3_nav_ringacc_get_ring_id(uc->rflow->r_ring); + int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring); + u32 rx_einfo_present = 0, rx_psinfo_present = 0; + u32 mode, fetch_size, rxcq_num; + + if (uc->config.pkt_mode) + mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR; + else + mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR; + + udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG, + UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode); + + if (uc->config.dir == DMA_MEM_TO_MEM) { + fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + rxcq_num = tc_ring; + } else { + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0) >> 2; + rxcq_num = rx_ring; + } + + udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG, + UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size); + udma_rchan_write(uc->rchan, UDMA_RCHAN_RCQ_REG, rxcq_num); + + if (uc->config.dir == DMA_MEM_TO_MEM) + return; + + if (ud->match_data->type == DMA_TYPE_UDMA && + uc->rflow->id != uc->rchan->id && + uc->config.dir != DMA_MEM_TO_MEM) + udma_rchan_write(uc->rchan, UDMA_RCHAN_RFLOW_RNG_REG, uc->rflow->id | + 1 << UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT); + + if (uc->config.needs_epib) + rx_einfo_present = UDMA_RFLOW_RFA_EINFO; + + if (uc->config.psd_size) + rx_psinfo_present = UDMA_RFLOW_RFA_PSINFO; + + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(A), + rx_einfo_present | rx_psinfo_present | rxcq_num); + + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(C), UDMA_RFLOW_RFC_DEFAULT); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(D), + fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(E), + fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(G), fd_ring); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(H), + fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT); +} diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 601868d7fc8..411edef3a76 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -48,6 +48,9 @@ enum udma_mmr { MMR_BCHANRT, MMR_RCHANRT, MMR_TCHANRT, + MMR_RCHAN, + MMR_TCHAN, + MMR_RFLOW, MMR_LAST, }; @@ -56,9 +59,13 @@ static const char * const mmr_names[] = { [MMR_BCHANRT] = "bchanrt", [MMR_RCHANRT] = "rchanrt", [MMR_TCHANRT] = "tchanrt", + [MMR_RCHAN] = "rchan", + [MMR_TCHAN] = "tchan", + [MMR_RFLOW] = "rflow", }; struct udma_tchan { + void __iomem *reg_chan; void __iomem *reg_rt; int id; @@ -71,12 +78,14 @@ struct udma_tchan { #define udma_bchan udma_tchan struct udma_rflow { + void __iomem *reg_rflow; int id; struct k3_nav_ring *fd_ring; /* Free Descriptor ring */ struct k3_nav_ring *r_ring; /* Receive ring */ }; struct udma_rchan { + void __iomem *reg_chan; void __iomem *reg_rt; int id; @@ -335,6 +344,8 @@ static inline char *udma_get_dir_text(enum dma_direction dir) return "invalid"; } +#include "k3-udma-u-boot.c" + static void udma_reset_uchan(struct udma_chan *uc) { memset(&uc->config, 0, sizeof(uc->config)); @@ -1014,10 +1025,20 @@ static int udma_alloc_tchan_sci_req(struct udma_chan *uc) req.txcq_qnum = tc_ring; ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req); - if (ret) + if (ret) { dev_err(ud->dev, "tisci tx alloc failed %d\n", ret); + return ret; + } - return ret; + /* + * Above TI SCI call handles firewall configuration, cfg + * register configuration still has to be done locally in + * absence of RM services. + */ + if (IS_ENABLED(CONFIG_K3_DM_FW)) + udma_alloc_tchan_raw(uc); + + return 0; } static int udma_alloc_rchan_sci_req(struct udma_chan *uc) @@ -1114,11 +1135,21 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc) ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); - if (ret) + if (ret) { dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n", uc->rchan->id, uc->rflow->id, ret); + return ret; + } - return ret; + /* + * Above TI SCI call handles firewall configuration, cfg + * register configuration still has to be done locally in + * absence of RM services. + */ + if (IS_ENABLED(CONFIG_K3_DM_FW)) + udma_alloc_rchan_raw(uc); + + return 0; } static int udma_alloc_chan_resources(struct udma_chan *uc) @@ -1751,6 +1782,7 @@ static int udma_probe(struct udevice *dev) struct udma_tchan *tchan = &ud->tchans[i]; tchan->id = i; + tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i); tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i); } @@ -1758,6 +1790,7 @@ static int udma_probe(struct udevice *dev) struct udma_rchan *rchan = &ud->rchans[i]; rchan->id = i; + rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i); rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i); } @@ -1765,6 +1798,7 @@ static int udma_probe(struct udevice *dev) struct udma_rflow *rflow = &ud->rflows[i]; rflow->id = i; + rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i); } for (i = 0; i < ud->ch_count; i++) { From 86ce3737edfcf0575ee575cb0276c0c3d5453523 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Wed, 26 May 2021 16:05:57 +0300 Subject: [PATCH 085/250] configs: sam boards: add hash command Add hash and hash verify commands. These would be useful for verifying copied data. Signed-off-by: Eugen Hristev --- configs/sam9x60ek_mmc_defconfig | 2 ++ configs/sam9x60ek_nandflash_defconfig | 2 ++ configs/sam9x60ek_qspiflash_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc1_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc_defconfig | 2 ++ configs/sama5d27_som1_ek_qspiflash_defconfig | 2 ++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 2 ++ configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 2 ++ configs/sama5d2_icp_mmc_defconfig | 2 ++ configs/sama5d2_ptc_ek_mmc_defconfig | 2 ++ configs/sama5d2_ptc_ek_nandflash_defconfig | 2 ++ configs/sama5d2_xplained_emmc_defconfig | 2 ++ configs/sama5d2_xplained_mmc_defconfig | 2 ++ configs/sama5d2_xplained_qspiflash_defconfig | 2 ++ configs/sama5d2_xplained_spiflash_defconfig | 2 ++ configs/sama5d3_xplained_mmc_defconfig | 2 ++ configs/sama5d3_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_mmc_defconfig | 2 ++ configs/sama5d4_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_spiflash_defconfig | 2 ++ configs/sama7g5ek_mmc1_defconfig | 2 ++ configs/sama7g5ek_mmc_defconfig | 2 ++ 22 files changed, 44 insertions(+) diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index e5edf45fee5..81899979380 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index bc326f96368..f4ba3485f19 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index 2f50f2fe47b..29071e802fa 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 1a49f23f36c..f867603cef2 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 5ef85bd8cf6..1a63f38a399 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 06bced8a73c..69b4203db83 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index f019e073aba..06c6a16a215 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index d1f7e183883..6e88e3497f2 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -46,6 +46,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index d1f7dc41ad6..f4f4134dc9f 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 0c0dcbb5456..978b4b2cd1e 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 224afea367c..9017e9d7c37 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index f7d8776746d..2750e24d08d 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index a6931f7fb8e..5ac0996d0a6 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 982ec3f7797..fa2e9b83d99 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index c32601a7345..70209efb1f9 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index e35a5752662..dad7f395a63 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 4d8a63fbd71..9c822888718 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index d1cbf32bd01..c5ca92996b8 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index f805cf11820..e264b9c1b68 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index a29bbaed635..b033e38b39f 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index af78ee60f49..8acb5f23a5f 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index 60423b48e7f..2c7a81db7fa 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y From ea83ea5afd181ac2cf5d02b623956a6dac684883 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Mon, 31 May 2021 23:23:48 +0200 Subject: [PATCH 086/250] board: sama5d3_xplained: add Falcon boot support This supports Falcon boot support for Microchip SAMA5D3 Xplained, tested on raw MMC, and on raw NAND. spl_start_uboot() is has the simplest possible implementation. It doesn't test the environment because enabling environment support currently causes the SPL to exceed its maximum size (64 KiB). It doesn't check the serial for incoming characters either because this functionality currently doesn't seem to work from the SPL on this board. Settings for Falcon boot from at FAT partition are also added to avoid compile failures when CONFIG_SPL_OS_BOOT is enabled, but this particular case is currently not functional as adding FAT and partition support cause the SPL to be too big again. Signed-off-by: Michael Opdenacker --- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 7 +++++++ include/configs/sama5d3_xplained.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index db9603f5847..c25bf42e0af 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -132,6 +132,13 @@ void spl_board_init(void) #endif } +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + static void ddr2_conf(struct atmel_mpddrc_config *ddr2) { ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 1113214bcff..4c25964b43a 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -79,4 +79,18 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +/* Falcon boot support on raw MMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +/* U-Boot proper stored by default at 0x200 (256 KiB) */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x22000000 + +/* Falcon boot support on FAT on MMC */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" + +/* Falcon boot support on raw NAND */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x1a0000 + #endif From 6e33eba59f2e695b6549a42507218f04575859fa Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:07 -0400 Subject: [PATCH 087/250] clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- drivers/clk/clk-uclass.c | 27 +++++++++++++++++---------- drivers/clk/rockchip/clk_rk3308.c | 2 +- drivers/core/device.c | 2 +- drivers/net/gmac_rockchip.c | 2 +- include/clk.h | 30 ++++++++++++++++++++++++++---- 5 files changed, 46 insertions(+), 17 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3d2344f009e..cac0f6a0122 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -207,7 +207,8 @@ static struct clk *clk_set_default_get_by_id(struct clk *clk) return c; } -static int clk_set_default_parents(struct udevice *dev, int stage) +static int clk_set_default_parents(struct udevice *dev, + enum clk_defaults_stage stage) { struct clk clk, parent_clk, *c, *p; int index; @@ -260,10 +261,10 @@ static int clk_set_default_parents(struct udevice *dev, int stage) * It cannot be done right now but need to wait after the * device is probed */ - if (stage == 0 && clk.dev == dev) + if (stage == CLK_DEFAULTS_PRE && clk.dev == dev) continue; - if (stage > 0 && clk.dev != dev) + if (stage != CLK_DEFAULTS_PRE && clk.dev != dev) /* do not setup twice the parent clocks */ continue; @@ -289,7 +290,8 @@ static int clk_set_default_parents(struct udevice *dev, int stage) return 0; } -static int clk_set_default_rates(struct udevice *dev, int stage) +static int clk_set_default_rates(struct udevice *dev, + enum clk_defaults_stage stage) { struct clk clk, *c; int index; @@ -338,10 +340,10 @@ static int clk_set_default_rates(struct udevice *dev, int stage) * It cannot be done right now but need to wait after the * device is probed */ - if (stage == 0 && clk.dev == dev) + if (stage == CLK_DEFAULTS_PRE && clk.dev == dev) continue; - if (stage > 0 && clk.dev != dev) + if (stage != CLK_DEFAULTS_PRE && clk.dev != dev) /* do not setup twice the parent clocks */ continue; @@ -364,16 +366,21 @@ fail: return ret; } -int clk_set_defaults(struct udevice *dev, int stage) +int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage) { int ret; if (!dev_has_ofnode(dev)) return 0; - /* If this not in SPL and pre-reloc state, don't take any action. */ + /* + * To avoid setting defaults twice, don't set them before relocation. + * However, still set them for SPL. And still set them if explicitly + * asked. + */ if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC))) - return 0; + if (stage != CLK_DEFAULTS_POST_FORCE) + return 0; debug("%s(%s)\n", __func__, dev_read_name(dev)); @@ -844,7 +851,7 @@ int clk_uclass_post_probe(struct udevice *dev) * where the DT is used to setup default parents and rates * using assigned-clocks */ - clk_set_defaults(dev, 1); + clk_set_defaults(dev, CLK_DEFAULTS_POST); return 0; } diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 5a838b9e9a5..5248e596853 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -1014,7 +1014,7 @@ static int rk3308_clk_probe(struct udevice *dev) rk3308_clk_init(dev); /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ - ret = clk_set_defaults(dev, 1); + ret = clk_set_defaults(dev, CLK_DEFAULTS_POST); if (ret) debug("%s clk_set_defaults failed %d\n", __func__, ret); diff --git a/drivers/core/device.c b/drivers/core/device.c index cb960f8ec44..9f1400768de 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -561,7 +561,7 @@ int device_probe(struct udevice *dev) * Process 'assigned-{clocks/clock-parents/clock-rates}' * properties */ - ret = clk_set_defaults(dev, 0); + ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE); if (ret) goto fail; } diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index f9096604840..04008d2b198 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -565,7 +565,7 @@ static int gmac_rockchip_probe(struct udevice *dev) ulong rate; int ret; - ret = clk_set_defaults(dev, 0); + ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE); if (ret) debug("%s clk_set_defaults failed %d\n", __func__, ret); diff --git a/include/clk.h b/include/clk.h index ca6b85fa6fe..f3c88fe68aa 100644 --- a/include/clk.h +++ b/include/clk.h @@ -277,19 +277,41 @@ static inline int clk_release_all(struct clk *clk, int count) } #endif +/** + * enum clk_defaults_stage - What stage clk_set_defaults() is called at + * @CLK_DEFAULTS_PRE: Called before probe. Setting of defaults for clocks owned + * by this clock driver will be defered until after probing. + * @CLK_DEFAULTS_POST: Called after probe. Only defaults for clocks owned by + * this clock driver will be set. + * @CLK_DEFAULTS_POST_FORCE: Called after probe, and always set defaults, even + * before relocation. Usually, defaults are not set + * pre-relocation to avoid setting them twice (when + * the device is probed again post-relocation). This + * may incur a performance cost as device tree + * properties must be parsed for a second time. + * However, when not using SPL, pre-relocation may be + * the only time we can set defaults for some clocks + * (such as those used for the RAM we will relocate + * into). + */ +enum clk_defaults_stage { + CLK_DEFAULTS_PRE = 0, + CLK_DEFAULTS_POST = 1, + CLK_DEFAULTS_POST_FORCE, +}; + #if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ CONFIG_IS_ENABLED(CLK) + /** * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}' * properties to configure clocks * * @dev: A device to process (the ofnode associated with this device * will be processed). - * @stage: A integer. 0 indicates that this is called before the device - * is probed. 1 indicates that this is called just after the - * device has been probed + * @stage: The stage of the probing process this function is called during. */ -int clk_set_defaults(struct udevice *dev, int stage); +int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage); #else static inline int clk_set_defaults(struct udevice *dev, int stage) { From 609bd60b943b17784b1cd245dc1bfb6384dab640 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:08 -0400 Subject: [PATCH 088/250] clk: k210: Rewrite to remove CCF This is effectively a complete rewrite to remove all dependency on CCF. The code is now smaller, and so is the binary. It also takes up less memory at runtime (since we don't have to create 40 udevices). In general, I am much happier with this driver as much of the complexity and late binding has been removed. The k210_*_params structs which were previously used to initialize CCF clocks are now used as the complete configuration. Since we can write our own division logic, we can now do away with several "half" clocks which only existed to provide constant factors of two. The clock IDs have been renumbered to remove unused clocks. This may not be the last time they are renumbered, since we have diverged with Linux. There are also still a few clocks left out which may need to be added back in. In general, I have tried to leave out behavioral changes. However, there is a small bugfix regarding ACLK. According to the technical reference manual, its mux comes *after* its divider (which is present only for PLL0). This would have required yet another intermediate clock to fix with CCF, but with the new driver it is just 2 lines of code :) Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/kendryte/Kconfig | 2 +- drivers/clk/kendryte/clk.c | 848 +++++++++++------------- drivers/clk/kendryte/pll.c | 114 ++-- include/dt-bindings/clock/k210-sysctl.h | 94 ++- include/kendryte/pll.h | 26 +- 5 files changed, 499 insertions(+), 585 deletions(-) diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig index 073fca07816..0dc8e3f889f 100644 --- a/drivers/clk/kendryte/Kconfig +++ b/drivers/clk/kendryte/Kconfig @@ -1,6 +1,6 @@ config CLK_K210 bool "Clock support for Kendryte K210" - depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF + depends on CLK help This enables support clock driver for Kendryte K210 platforms. diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index 41c712e03f1..34e8e742a69 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include @@ -14,77 +14,6 @@ #include #include -/* All methods are delegated to CCF clocks */ - -static ulong k210_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - return clk_get_rate(c); -} - -static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *c; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - return clk_set_rate(c, rate); -} - -static int k210_clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *c, *p; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - - err = clk_get_by_id(parent->id, &p); - if (err) - return err; - - return clk_set_parent(c, p); -} - -static int k210_clk_endisable(struct clk *clk, bool enable) -{ - struct clk *c; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - return enable ? clk_enable(c) : clk_disable(c); -} - -static int k210_clk_enable(struct clk *clk) -{ - return k210_clk_endisable(clk, true); -} - -static int k210_clk_disable(struct clk *clk) -{ - return k210_clk_endisable(clk, false); -} - -static const struct clk_ops k210_clk_ops = { - .set_rate = k210_clk_set_rate, - .get_rate = k210_clk_get_rate, - .set_parent = k210_clk_set_parent, - .enable = k210_clk_enable, - .disable = k210_clk_disable, -}; - -/* Parents for muxed clocks */ -static const char * const generic_sels[] = { "in0_half", "pll0_half" }; -/* The first clock is in0, which is filled in by k210_clk_probe */ -static const char *aclk_sels[] = { NULL, "pll0_half" }; -static const char *pll2_sels[] = { NULL, "pll0", "pll1" }; - /* * All parameters for different sub-clocks are collected into parameter arrays. * These parameters are then initialized by the clock which uses them during @@ -97,68 +26,113 @@ static const char *pll2_sels[] = { NULL, "pll0", "pll1" }; * easy to find bugs in the code. */ -#define DIV(id, off, shift, width) DIV_FLAGS(id, off, shift, width, 0) +/** + * enum k210_clk_div_type - The type of divider + * @K210_DIV_ONE: freq = parent / (reg + 1) + * @K210_DIV_EVEN: freq = parent / 2 / (reg + 1) + * @K210_DIV_POWER: freq = parent / (2 << reg) + * @K210_DIV_FIXED: freq = parent / factor + */ +enum k210_clk_div_type { + K210_DIV_ONE, + K210_DIV_EVEN, + K210_DIV_POWER, + K210_DIV_FIXED, +}; + +/** + * struct k210_div_params - Parameters for dividing clocks + * @type: An &enum k210_clk_div_type specifying the dividing formula + * @off: The offset of the divider from the sysctl base address + * @shift: The offset of the LSB of the divider + * @width: The number of bits in the divider + * @div: The fixed divisor for this divider + */ +struct k210_div_params { + u8 type; + union { + struct { + u8 off; + u8 shift; + u8 width; + }; + u8 div; + }; +}; + #define DIV_LIST \ - DIV_FLAGS(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, \ - CLK_DIVIDER_POWER_OF_TWO) \ - DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3) \ - DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3) \ - DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3) \ - DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4) \ - DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4) \ - DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4) \ - DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4) \ - DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4) \ - DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8) \ - DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8) \ - DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8) \ - DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8) \ - DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8) \ - DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8) \ - DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8) \ - DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16) \ - DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16) \ - DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16) \ - DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8) \ - DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8) \ - DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8) \ - DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8) \ - DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8) \ - DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8) \ - DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8) \ - DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8) + DIV(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, K210_DIV_POWER) \ + DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE) \ + DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE) \ + DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE) \ + DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE) \ + DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE) \ + DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE) \ + DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE) \ + DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE) \ + DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16, K210_DIV_EVEN) \ + DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16, K210_DIV_EVEN) \ + DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16, K210_DIV_EVEN) \ + DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8, K210_DIV_EVEN) \ + DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8, K210_DIV_EVEN) \ + DIV_FIXED(K210_CLK_CLINT, 50) \ #define _DIVIFY(id) K210_CLK_DIV_##id #define DIVIFY(id) _DIVIFY(id) -enum k210_div_ids { -#define DIV_FLAGS(id, ...) DIVIFY(id), +enum k210_div_id { +#define DIV(id, ...) DIVIFY(id), +#define DIV_FIXED DIV DIV_LIST -#undef DIV_FLAGS -}; - -struct k210_div_params { - u8 off; - u8 shift; - u8 width; - u8 flags; +#undef DIV +#undef DIV_FIXED + K210_CLK_DIV_NONE, }; static const struct k210_div_params k210_divs[] = { -#define DIV_FLAGS(id, _off, _shift, _width, _flags) \ +#define DIV(id, _off, _shift, _width, _type) \ [DIVIFY(id)] = { \ + .type = (_type), \ .off = (_off), \ .shift = (_shift), \ .width = (_width), \ - .flags = (_flags), \ + }, +#define DIV_FIXED(id, _div) \ + [DIVIFY(id)] = { \ + .type = K210_DIV_FIXED, \ + .div = (_div) \ }, DIV_LIST -#undef DIV_FLAGS +#undef DIV +#undef DIV_FIXED }; #undef DIV #undef DIV_LIST +/** + * struct k210_gate_params - Parameters for gated clocks + * @off: The offset of the gate from the sysctl base address + * @bit_idx: The index of the bit within the register + */ +struct k210_gate_params { + u8 off; + u8 bit_idx; +}; + #define GATE_LIST \ GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \ GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \ @@ -199,15 +173,11 @@ static const struct k210_div_params k210_divs[] = { #define _GATEIFY(id) K210_CLK_GATE_##id #define GATEIFY(id) _GATEIFY(id) -enum k210_gate_ids { +enum k210_gate_id { #define GATE(id, ...) GATEIFY(id), GATE_LIST #undef GATE -}; - -struct k210_gate_params { - u8 off; - u8 bit_idx; + K210_CLK_GATE_NONE, }; static const struct k210_gate_params k210_gates[] = { @@ -222,11 +192,31 @@ static const struct k210_gate_params k210_gates[] = { #undef GATE_LIST +/* The most parents is PLL2 */ +#define K210_CLK_MAX_PARENTS 3 + +/** + * struct k210_mux_params - Parameters for muxed clocks + * @parents: A list of parent clock ids + * @num_parents: The number of parent clocks + * @off: The offset of the mux from the base sysctl address + * @shift: The offset of the LSB of the mux selector + * @width: The number of bits in the mux selector + */ +struct k210_mux_params { + u8 parents[K210_CLK_MAX_PARENTS]; + u8 num_parents; + u8 off; + u8 shift; + u8 width; +}; + #define MUX(id, reg, shift, width) \ - MUX_PARENTS(id, generic_sels, reg, shift, width) + MUX_PARENTS(id, reg, shift, width, K210_CLK_IN0, K210_CLK_PLL0) #define MUX_LIST \ - MUX_PARENTS(K210_CLK_PLL2, pll2_sels, K210_SYSCTL_PLL2, 26, 2) \ - MUX_PARENTS(K210_CLK_ACLK, aclk_sels, K210_SYSCTL_SEL0, 0, 1) \ + MUX_PARENTS(K210_CLK_PLL2, K210_SYSCTL_PLL2, 26, 2, \ + K210_CLK_IN0, K210_CLK_PLL0, K210_CLK_PLL1) \ + MUX(K210_CLK_ACLK, K210_SYSCTL_SEL0, 0, 1) \ MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \ MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \ MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \ @@ -235,26 +225,18 @@ static const struct k210_gate_params k210_gates[] = { #define _MUXIFY(id) K210_CLK_MUX_##id #define MUXIFY(id) _MUXIFY(id) -enum k210_mux_ids { +enum k210_mux_id { #define MUX_PARENTS(id, ...) MUXIFY(id), MUX_LIST #undef MUX_PARENTS K210_CLK_MUX_NONE, }; -struct k210_mux_params { - const char *const *parent_names; - u8 num_parents; - u8 off; - u8 shift; - u8 width; -}; - static const struct k210_mux_params k210_muxes[] = { -#define MUX_PARENTS(id, parents, _off, _shift, _width) \ +#define MUX_PARENTS(id, _off, _shift, _width, ...) \ [MUXIFY(id)] = { \ - .parent_names = (const char * const *)(parents), \ - .num_parents = ARRAY_SIZE(parents), \ + .parents = { __VA_ARGS__ }, \ + .num_parents = __count_args(__VA_ARGS__), \ .off = (_off), \ .shift = (_shift), \ .width = (_width), \ @@ -266,389 +248,321 @@ static const struct k210_mux_params k210_muxes[] = { #undef MUX #undef MUX_LIST -struct k210_pll_params { - u8 off; - u8 lock_off; - u8 shift; - u8 width; +/** + * enum k210_clk_flags - The type of a K210 clock + * @K210_CLKF_MUX: This clock has a mux and not a static parent + * @K210_CLKF_PLL: This clock is a PLL + */ +enum k210_clk_flags { + K210_CLKF_MUX = BIT(0), + K210_CLKF_PLL = BIT(1), }; -static const struct k210_pll_params k210_plls[] = { -#define PLL(_off, _shift, _width) { \ - .off = (_off), \ - .lock_off = K210_SYSCTL_PLL_LOCK, \ - .shift = (_shift), \ - .width = (_width), \ -} - [0] = PLL(K210_SYSCTL_PLL0, 0, 2), - [1] = PLL(K210_SYSCTL_PLL1, 8, 1), - [2] = PLL(K210_SYSCTL_PLL2, 16, 1), -#undef PLL +/** + * struct k210_clk_params - The parameters defining a K210 clock + * @name: The name of the clock + * @flags: A set of &enum k210_clk_flags defining which fields are valid + * @mux: An &enum k210_mux_id of this clock's mux + * @parent: The clock id of this clock's parent + * @pll: The id of the PLL (if this clock is a PLL) + * @div: An &enum k210_div_id of this clock's divider + * @gate: An &enum k210_gate_id of this clock's gate + */ +struct k210_clk_params { +#if CONFIG_IS_ENABLED(CMD_CLK) + const char *name; +#endif + u8 flags; + union { + u8 parent; + u8 mux; + }; + union { + u8 pll; + struct { + u8 div; + u8 gate; + }; + }; }; -#define COMP(id) \ - COMP_FULL(id, MUXIFY(id), DIVIFY(id), GATEIFY(id)) -#define COMP_NOMUX(id) \ - COMP_FULL(id, K210_CLK_MUX_NONE, DIVIFY(id), GATEIFY(id)) -#define COMP_LIST \ - COMP(K210_CLK_SPI3) \ - COMP(K210_CLK_TIMER0) \ - COMP(K210_CLK_TIMER1) \ - COMP(K210_CLK_TIMER2) \ - COMP_NOMUX(K210_CLK_SRAM0) \ - COMP_NOMUX(K210_CLK_SRAM1) \ - COMP_NOMUX(K210_CLK_ROM) \ - COMP_NOMUX(K210_CLK_DVP) \ - COMP_NOMUX(K210_CLK_APB0) \ - COMP_NOMUX(K210_CLK_APB1) \ - COMP_NOMUX(K210_CLK_APB2) \ - COMP_NOMUX(K210_CLK_AI) \ - COMP_NOMUX(K210_CLK_I2S0) \ - COMP_NOMUX(K210_CLK_I2S1) \ - COMP_NOMUX(K210_CLK_I2S2) \ - COMP_NOMUX(K210_CLK_WDT0) \ - COMP_NOMUX(K210_CLK_WDT1) \ - COMP_NOMUX(K210_CLK_SPI0) \ - COMP_NOMUX(K210_CLK_SPI1) \ - COMP_NOMUX(K210_CLK_SPI2) \ - COMP_NOMUX(K210_CLK_I2C0) \ - COMP_NOMUX(K210_CLK_I2C1) \ - COMP_NOMUX(K210_CLK_I2C2) -#define _COMPIFY(id) K210_CLK_COMP_##id -#define COMPIFY(id) _COMPIFY(id) - -enum k210_comp_ids { -#define COMP_FULL(id, ...) COMPIFY(id), - COMP_LIST -#undef COMP_FULL -}; - -struct k210_comp_params { - u8 mux; - u8 div; - u8 gate; -}; - -static const struct k210_comp_params k210_comps[] = { -#define COMP_FULL(id, _mux, _div, _gate) \ - [COMPIFY(id)] = { \ +static const struct k210_clk_params k210_clks[] = { +#if CONFIG_IS_ENABLED(CMD_CLK) +#define NAME(_name) .name = (_name), +#else +#define NAME(name) +#endif +#define CLK(id, _name, _parent, _div, _gate) \ + [id] = { \ + NAME(_name) \ + .parent = (_parent), \ + .div = (_div), \ + .gate = (_gate), \ + } +#define CLK_MUX(id, _name, _mux, _div, _gate) \ + [id] = { \ + NAME(_name) \ + .flags = K210_CLKF_MUX, \ .mux = (_mux), \ .div = (_div), \ .gate = (_gate), \ + } +#define CLK_PLL(id, _pll, _parent) \ + [id] = { \ + NAME("pll" #_pll) \ + .flags = K210_CLKF_PLL, \ + .parent = (_parent), \ + .pll = (_pll), \ + } +#define CLK_FULL(id, name) \ + CLK_MUX(id, name, MUXIFY(id), DIVIFY(id), GATEIFY(id)) +#define CLK_NOMUX(id, name, parent) \ + CLK(id, name, parent, DIVIFY(id), GATEIFY(id)) +#define CLK_DIV(id, name, parent) \ + CLK(id, name, parent, DIVIFY(id), K210_CLK_GATE_NONE) +#define CLK_GATE(id, name, parent) \ + CLK(id, name, parent, K210_CLK_DIV_NONE, GATEIFY(id)) + CLK_PLL(K210_CLK_PLL0, 0, K210_CLK_IN0), + CLK_PLL(K210_CLK_PLL1, 1, K210_CLK_IN0), + [K210_CLK_PLL2] = { + NAME("pll2") + .flags = K210_CLKF_MUX | K210_CLKF_PLL, + .mux = MUXIFY(K210_CLK_PLL2), + .pll = 2, }, - COMP_LIST -#undef COMP_FULL + CLK_MUX(K210_CLK_ACLK, "aclk", MUXIFY(K210_CLK_ACLK), + DIVIFY(K210_CLK_ACLK), K210_CLK_GATE_NONE), + CLK_FULL(K210_CLK_SPI3, "spi3"), + CLK_FULL(K210_CLK_TIMER0, "timer0"), + CLK_FULL(K210_CLK_TIMER1, "timer1"), + CLK_FULL(K210_CLK_TIMER2, "timer2"), + CLK_NOMUX(K210_CLK_SRAM0, "sram0", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_SRAM1, "sram1", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_ROM, "rom", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_DVP, "dvp", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_APB0, "apb0", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_APB1, "apb1", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_APB2, "apb2", K210_CLK_ACLK), + CLK_NOMUX(K210_CLK_AI, "ai", K210_CLK_PLL1), + CLK_NOMUX(K210_CLK_I2S0, "i2s0", K210_CLK_PLL2), + CLK_NOMUX(K210_CLK_I2S1, "i2s1", K210_CLK_PLL2), + CLK_NOMUX(K210_CLK_I2S2, "i2s2", K210_CLK_PLL2), + CLK_NOMUX(K210_CLK_WDT0, "wdt0", K210_CLK_IN0), + CLK_NOMUX(K210_CLK_WDT1, "wdt1", K210_CLK_IN0), + CLK_NOMUX(K210_CLK_SPI0, "spi0", K210_CLK_PLL0), + CLK_NOMUX(K210_CLK_SPI1, "spi1", K210_CLK_PLL0), + CLK_NOMUX(K210_CLK_SPI2, "spi2", K210_CLK_PLL0), + CLK_NOMUX(K210_CLK_I2C0, "i2c0", K210_CLK_PLL0), + CLK_NOMUX(K210_CLK_I2C1, "i2c1", K210_CLK_PLL0), + CLK_NOMUX(K210_CLK_I2C2, "i2c2", K210_CLK_PLL0), + CLK_DIV(K210_CLK_I2S0_M, "i2s0_m", K210_CLK_PLL2), + CLK_DIV(K210_CLK_I2S1_M, "i2s1_m", K210_CLK_PLL2), + CLK_DIV(K210_CLK_I2S2_M, "i2s2_m", K210_CLK_PLL2), + CLK_DIV(K210_CLK_CLINT, "clint", K210_CLK_ACLK), + CLK_GATE(K210_CLK_CPU, "cpu", K210_CLK_ACLK), + CLK_GATE(K210_CLK_DMA, "dma", K210_CLK_ACLK), + CLK_GATE(K210_CLK_FFT, "fft", K210_CLK_ACLK), + CLK_GATE(K210_CLK_GPIO, "gpio", K210_CLK_APB0), + CLK_GATE(K210_CLK_UART1, "uart1", K210_CLK_APB0), + CLK_GATE(K210_CLK_UART2, "uart2", K210_CLK_APB0), + CLK_GATE(K210_CLK_UART3, "uart3", K210_CLK_APB0), + CLK_GATE(K210_CLK_FPIOA, "fpioa", K210_CLK_APB0), + CLK_GATE(K210_CLK_SHA, "sha", K210_CLK_APB0), + CLK_GATE(K210_CLK_AES, "aes", K210_CLK_APB1), + CLK_GATE(K210_CLK_OTP, "otp", K210_CLK_APB1), + CLK_GATE(K210_CLK_RTC, "rtc", K210_CLK_IN0), +#undef NAME +#undef CLK_PLL +#undef CLK +#undef CLK_FULL +#undef CLK_NOMUX +#undef CLK_DIV +#undef CLK_GATE +#undef CLK_LIST }; -#undef COMP -#undef COMP_ID -#undef COMP_NOMUX -#undef COMP_NOMUX_ID -#undef COMP_LIST - -static struct clk *k210_bypass_children __section(".data"); - -/* Helper functions to create sub-clocks */ -static struct clk_mux *k210_create_mux(const struct k210_mux_params *params, - void *base) +static u32 k210_clk_readl(struct k210_clk_priv *priv, u8 off, u8 shift, + u8 width) { - struct clk_mux *mux = kzalloc(sizeof(*mux), GFP_KERNEL); + u32 reg = readl(priv->base + off); - if (!mux) - return mux; - - mux->reg = base + params->off; - mux->mask = BIT(params->width) - 1; - mux->shift = params->shift; - mux->parent_names = params->parent_names; - mux->num_parents = params->num_parents; - - return mux; + return (reg >> shift) & (BIT(width) - 1); } -static struct clk_divider *k210_create_div(const struct k210_div_params *params, - void *base) +static void k210_clk_writel(struct k210_clk_priv *priv, u8 off, u8 shift, + u8 width, u32 val) { - struct clk_divider *div = kzalloc(sizeof(*div), GFP_KERNEL); + u32 reg = readl(priv->base + off); + u32 mask = (BIT(width) - 1) << shift; - if (!div) - return div; - - div->reg = base + params->off; - div->shift = params->shift; - div->width = params->width; - div->flags = params->flags; - - return div; + reg &= ~mask; + reg |= mask & (val << shift); + writel(reg, priv->base + off); } -static struct clk_gate *k210_create_gate(const struct k210_gate_params *params, - void *base) +static int k210_clk_get_parent(struct k210_clk_priv *priv, int id) { - struct clk_gate *gate = kzalloc(sizeof(*gate), GFP_KERNEL); + u32 sel; + const struct k210_mux_params *mux; - if (!gate) - return gate; + if (!(k210_clks[id].flags & K210_CLKF_MUX)) + return k210_clks[id].parent; + mux = &k210_muxes[k210_clks[id].mux]; - gate->reg = base + params->off; - gate->bit_idx = params->bit_idx; - - return gate; + sel = k210_clk_readl(priv, mux->off, mux->shift, mux->width); + assert(sel < mux->num_parents); + return mux->parents[sel]; } -static struct k210_pll *k210_create_pll(const struct k210_pll_params *params, - void *base) +static ulong do_k210_clk_get_rate(struct k210_clk_priv *priv, int id) { - struct k210_pll *pll = kzalloc(sizeof(*pll), GFP_KERNEL); + int parent; + u32 val; + ulong parent_rate; + const struct k210_div_params *div; - if (!pll) - return pll; + if (id == K210_CLK_IN0) + return clk_get_rate(&priv->in0); - pll->reg = base + params->off; - pll->lock = base + params->lock_off; - pll->shift = params->shift; - pll->width = params->width; + parent = k210_clk_get_parent(priv, id); + parent_rate = do_k210_clk_get_rate(priv, parent); - return pll; + if (k210_clks[id].flags & K210_CLKF_PLL) + return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate); + + if (k210_clks[id].div == K210_CLK_DIV_NONE) + return parent_rate; + div = &k210_divs[k210_clks[id].div]; + + if (div->type == K210_DIV_FIXED) + return parent_rate / div->div; + + val = k210_clk_readl(priv, div->off, div->shift, div->width); + switch (div->type) { + case K210_DIV_ONE: + return parent_rate / (val + 1); + case K210_DIV_EVEN: + return parent_rate / 2 / (val + 1); + case K210_DIV_POWER: + /* This is ACLK, which has no divider on IN0 */ + if (parent == K210_CLK_IN0) + return parent_rate; + return parent_rate / (2 << val); + default: + assert(false); + return -EINVAL; + }; } -/* Create all sub-clocks, and then register the composite clock */ -static struct clk *k210_register_comp(const struct k210_comp_params *params, - void *base, const char *name, - const char *parent) +static ulong k210_clk_get_rate(struct clk *clk) { - const char *const *parent_names; - int num_parents; - struct clk *comp; - const struct clk_ops *mux_ops; - struct clk_mux *mux; - struct clk_divider *div; - struct clk_gate *gate; + return do_k210_clk_get_rate(dev_get_priv(clk->dev), clk->id); +} - if (params->mux == K210_CLK_MUX_NONE) { - if (!parent) - return ERR_PTR(-EINVAL); +static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate) +{ + return -ENOSYS; +} - mux_ops = NULL; - mux = NULL; - parent_names = &parent; - num_parents = 1; - } else { - mux_ops = &clk_mux_ops; - mux = k210_create_mux(&k210_muxes[params->mux], base); - if (!mux) - return ERR_PTR(-ENOMEM); +static int do_k210_clk_set_parent(struct k210_clk_priv *priv, int id, int new) +{ + int i; + const struct k210_mux_params *mux; - parent_names = mux->parent_names; - num_parents = mux->num_parents; + if (!(k210_clks[id].flags & K210_CLKF_MUX)) + return -ENOSYS; + mux = &k210_muxes[k210_clks[id].mux]; + + for (i = 0; i < mux->num_parents; i++) { + if (mux->parents[i] == new) { + k210_clk_writel(priv, mux->off, mux->shift, mux->width, + i); + return 0; + } + } + return -EINVAL; +} + +static int k210_clk_set_parent(struct clk *clk, struct clk *parent) +{ + return do_k210_clk_set_parent(dev_get_priv(clk->dev), clk->id, + parent->id); +} + +static int k210_clk_endisable(struct k210_clk_priv *priv, int id, bool enable) +{ + int parent = k210_clk_get_parent(priv, id); + const struct k210_gate_params *gate; + + if (id == K210_CLK_IN0) { + if (enable) + return clk_enable(&priv->in0); + else + return clk_disable(&priv->in0); } - div = k210_create_div(&k210_divs[params->div], base); - if (!div) { - comp = ERR_PTR(-ENOMEM); - goto cleanup_mux; + /* Only recursively enable clocks since we don't track refcounts */ + if (enable) { + int ret = k210_clk_endisable(priv, parent, true); + + if (ret && ret != -ENOSYS) + return ret; } - gate = k210_create_gate(&k210_gates[params->gate], base); - if (!gate) { - comp = ERR_PTR(-ENOMEM); - goto cleanup_div; + if (k210_clks[id].flags & K210_CLKF_PLL) { + if (enable) + return k210_pll_enable(priv, k210_clks[id].pll); + else + return k210_pll_disable(priv, k210_clks[id].pll); } - comp = clk_register_composite(NULL, name, parent_names, num_parents, - &mux->clk, mux_ops, - &div->clk, &clk_divider_ops, - &gate->clk, &clk_gate_ops, 0); - if (IS_ERR(comp)) - goto cleanup_gate; - return comp; + if (k210_clks[id].gate == K210_CLK_GATE_NONE) + return -ENOSYS; + gate = &k210_gates[k210_clks[id].gate]; -cleanup_gate: - free(gate); -cleanup_div: - free(div); -cleanup_mux: - free(mux); - return comp; -} - -static bool __section(".data") probed; - -/* reset probed so we will probe again post-relocation */ -static int k210_clk_bind(struct udevice *dev) -{ - probed = false; + k210_clk_writel(priv, gate->off, gate->bit_idx, 1, enable); return 0; } +static int k210_clk_enable(struct clk *clk) +{ + return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, true); +} + +static int k210_clk_disable(struct clk *clk) +{ + return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, false); +} + +static int k210_clk_request(struct clk *clk) +{ + if (clk->id >= ARRAY_SIZE(k210_clks)) + return -EINVAL; + return 0; +} + +static const struct clk_ops k210_clk_ops = { + .request = k210_clk_request, + .set_rate = k210_clk_set_rate, + .get_rate = k210_clk_get_rate, + .set_parent = k210_clk_set_parent, + .enable = k210_clk_enable, + .disable = k210_clk_disable, +}; + static int k210_clk_probe(struct udevice *dev) { int ret; - const char *in0; - struct clk *in0_clk, *bypass; - struct clk_mux *mux; - struct clk_divider *div; - struct k210_pll *pll; - void *base; + struct k210_clk_priv *priv = dev_get_priv(dev); - /* - * Only one instance of this driver allowed. This prevents weird bugs - * when the driver fails part-way through probing. Some clocks will - * already have been registered, and re-probing will register them - * again, creating a bunch of duplicates. Better error-handling/cleanup - * could fix this, but it's Probably Not Worth It (TM). - */ - if (probed) + priv->base = dev_read_addr_ptr(dev_get_parent(dev)); + if (!priv->base) return -EINVAL; - base = dev_read_addr_ptr(dev_get_parent(dev)); - if (!base) - return -EINVAL; - - in0_clk = kzalloc(sizeof(*in0_clk), GFP_KERNEL); - if (!in0_clk) - return -ENOMEM; - - ret = clk_get_by_index(dev, 0, in0_clk); + ret = clk_get_by_index(dev, 0, &priv->in0); if (ret) return ret; - in0 = in0_clk->dev->name; - - probed = true; - - aclk_sels[0] = in0; - pll2_sels[0] = in0; - - /* - * All PLLs have a broken bypass, but pll0 has the CPU downstream, so we - * need to manually reparent it whenever we configure pll0 - */ - pll = k210_create_pll(&k210_plls[0], base); - if (pll) { - bypass = k210_register_bypass("pll0", in0, &pll->clk, - &k210_pll_ops, in0_clk); - clk_dm(K210_CLK_PLL0, bypass); - } else { - return -ENOMEM; - } - - pll = k210_create_pll(&k210_plls[1], base); - if (pll) - clk_dm(K210_CLK_PLL1, - k210_register_pll_struct("pll1", in0, pll)); - - /* PLL2 is muxed, so set up a composite clock */ - mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base); - pll = k210_create_pll(&k210_plls[2], base); - if (!mux || !pll) { - free(mux); - free(pll); - } else { - clk_dm(K210_CLK_PLL2, - clk_register_composite(NULL, "pll2", pll2_sels, - ARRAY_SIZE(pll2_sels), - &mux->clk, &clk_mux_ops, - &pll->clk, &k210_pll_ops, - &pll->clk, &k210_pll_ops, 0)); - } - - /* Half-frequency clocks for "even" dividers */ - clk_dm(K210_CLK_IN0_H, k210_clk_half("in0_half", in0)); - clk_dm(K210_CLK_PLL0_H, k210_clk_half("pll0_half", "pll0")); - clk_dm(K210_CLK_PLL2_H, k210_clk_half("pll2_half", "pll2")); - - /* ACLK has no gate */ - mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_ACLK)], base); - div = k210_create_div(&k210_divs[DIVIFY(K210_CLK_ACLK)], base); - if (!mux || !div) { - free(mux); - free(div); - } else { - struct clk *aclk = - clk_register_composite(NULL, "aclk", aclk_sels, - ARRAY_SIZE(aclk_sels), - &mux->clk, &clk_mux_ops, - &div->clk, &clk_divider_ops, - NULL, NULL, 0); - clk_dm(K210_CLK_ACLK, aclk); - if (!IS_ERR(aclk)) { - k210_bypass_children = aclk; - k210_bypass_set_children(bypass, - &k210_bypass_children, 1); - } - } - -#define REGISTER_COMP(id, name) \ - clk_dm(id, \ - k210_register_comp(&k210_comps[COMPIFY(id)], base, name, NULL)) - REGISTER_COMP(K210_CLK_SPI3, "spi3"); - REGISTER_COMP(K210_CLK_TIMER0, "timer0"); - REGISTER_COMP(K210_CLK_TIMER1, "timer1"); - REGISTER_COMP(K210_CLK_TIMER2, "timer2"); -#undef REGISTER_COMP - - /* Dividing clocks, no mux */ -#define REGISTER_COMP_NOMUX(id, name, parent) \ - clk_dm(id, \ - k210_register_comp(&k210_comps[COMPIFY(id)], base, name, parent)) - REGISTER_COMP_NOMUX(K210_CLK_SRAM0, "sram0", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_SRAM1, "sram1", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_ROM, "rom", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_DVP, "dvp", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_APB0, "apb0", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_APB1, "apb1", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_APB2, "apb2", "aclk"); - REGISTER_COMP_NOMUX(K210_CLK_AI, "ai", "pll1"); - REGISTER_COMP_NOMUX(K210_CLK_I2S0, "i2s0", "pll2_half"); - REGISTER_COMP_NOMUX(K210_CLK_I2S1, "i2s1", "pll2_half"); - REGISTER_COMP_NOMUX(K210_CLK_I2S2, "i2s2", "pll2_half"); - REGISTER_COMP_NOMUX(K210_CLK_WDT0, "wdt0", "in0_half"); - REGISTER_COMP_NOMUX(K210_CLK_WDT1, "wdt1", "in0_half"); - REGISTER_COMP_NOMUX(K210_CLK_SPI0, "spi0", "pll0_half"); - REGISTER_COMP_NOMUX(K210_CLK_SPI1, "spi1", "pll0_half"); - REGISTER_COMP_NOMUX(K210_CLK_SPI2, "spi2", "pll0_half"); - REGISTER_COMP_NOMUX(K210_CLK_I2C0, "i2c0", "pll0_half"); - REGISTER_COMP_NOMUX(K210_CLK_I2C1, "i2c1", "pll0_half"); - REGISTER_COMP_NOMUX(K210_CLK_I2C2, "i2c2", "pll0_half"); -#undef REGISTER_COMP_NOMUX - - /* Dividing clocks */ -#define REGISTER_DIV(id, name, parent) do {\ - const struct k210_div_params *params = &k210_divs[DIVIFY(id)]; \ - clk_dm(id, \ - clk_register_divider(NULL, name, parent, 0, base + params->off, \ - params->shift, params->width, 0)); \ -} while (false) - REGISTER_DIV(K210_CLK_I2S0_M, "i2s0_m", "pll2_half"); - REGISTER_DIV(K210_CLK_I2S1_M, "i2s1_m", "pll2_half"); - REGISTER_DIV(K210_CLK_I2S2_M, "i2s2_m", "pll2_half"); -#undef REGISTER_DIV - - /* Gated clocks */ -#define REGISTER_GATE(id, name, parent) do { \ - const struct k210_gate_params *params = &k210_gates[GATEIFY(id)]; \ - clk_dm(id, \ - clk_register_gate(NULL, name, parent, 0, base + params->off, \ - params->bit_idx, 0, NULL)); \ -} while (false) - REGISTER_GATE(K210_CLK_CPU, "cpu", "aclk"); - REGISTER_GATE(K210_CLK_DMA, "dma", "aclk"); - REGISTER_GATE(K210_CLK_FFT, "fft", "aclk"); - REGISTER_GATE(K210_CLK_GPIO, "gpio", "apb0"); - REGISTER_GATE(K210_CLK_UART1, "uart1", "apb0"); - REGISTER_GATE(K210_CLK_UART2, "uart2", "apb0"); - REGISTER_GATE(K210_CLK_UART3, "uart3", "apb0"); - REGISTER_GATE(K210_CLK_FPIOA, "fpioa", "apb0"); - REGISTER_GATE(K210_CLK_SHA, "sha", "apb0"); - REGISTER_GATE(K210_CLK_AES, "aes", "apb1"); - REGISTER_GATE(K210_CLK_OTP, "otp", "apb1"); - REGISTER_GATE(K210_CLK_RTC, "rtc", in0); -#undef REGISTER_GATE - - /* The MTIME register in CLINT runs at one 50th the CPU clock speed */ - clk_dm(K210_CLK_CLINT, - clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50)); return 0; } @@ -663,6 +577,6 @@ U_BOOT_DRIVER(k210_clk) = { .id = UCLASS_CLK, .of_match = k210_clk_ids, .ops = &k210_clk_ops, - .bind = k210_clk_bind, .probe = k210_clk_probe, + .priv_auto = sizeof(struct k210_clk_priv), }; diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index 184f37aaf20..1f0275c83f7 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -12,17 +12,41 @@ #include #include #include +#include #include #include #include #include #include -#define CLK_K210_PLL "k210_clk_pll" +/** + * struct k210_pll_params - K210 PLL parameters + * @off: The offset of the PLL from the base sysctl address + * @shift: The offset of the LSB of the lock status + * @width: The number of bits in the lock status + */ +struct k210_pll_params { + u8 off; + u8 shift; + u8 width; +}; + +static const struct k210_pll_params k210_plls[] = { +#define PLL(_off, _shift, _width) { \ + .off = (_off), \ + .shift = (_shift), \ + .width = (_width), \ +} + [0] = PLL(K210_SYSCTL_PLL0, 0, 2), + [1] = PLL(K210_SYSCTL_PLL1, 8, 1), + [2] = PLL(K210_SYSCTL_PLL2, 16, 1), +#undef PLL +}; #ifdef CONFIG_CLK_K210_SET_RATE -static int k210_pll_enable(struct clk *clk); -static int k210_pll_disable(struct clk *clk); +int k210_pll_enable(struct k210_clk_priv *priv, int id); +int k210_pll_disable(struct k210_clk_priv *priv, int id); +ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in); /* * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc. @@ -423,12 +447,12 @@ TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, return 0; } -static ulong k210_pll_set_rate(struct clk *clk, ulong rate) +static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, + ulong rate_in) { int err; - long long rate_in = clk_get_parent_rate(clk); + const struct k210_pll_params *pll = &k210_plls[id]; struct k210_pll_config config = {}; - struct k210_pll *pll = to_k210_pll(clk); u32 reg; if (rate_in < 0) @@ -447,7 +471,7 @@ static ulong k210_pll_set_rate(struct clk *clk, ulong rate) */ k210_pll_disable(clk); - reg = readl(pll->reg); + reg = readl(priv->base + pll->off); reg &= ~K210_PLL_CLKR & ~K210_PLL_CLKF & ~K210_PLL_CLKOD @@ -456,7 +480,7 @@ static ulong k210_pll_set_rate(struct clk *clk, ulong rate) | FIELD_PREP(K210_PLL_CLKF, config.f - 1) | FIELD_PREP(K210_PLL_CLKOD, config.od - 1) | FIELD_PREP(K210_PLL_BWADJ, config.f - 1); - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); err = k210_pll_enable(clk); if (err) @@ -465,14 +489,18 @@ static ulong k210_pll_set_rate(struct clk *clk, ulong rate) serial_setbrg(); return clk_get_rate(clk); } +#else +ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, + ulong rate_in) +{ + return -ENOSYS; +} #endif /* CONFIG_CLK_K210_SET_RATE */ -static ulong k210_pll_get_rate(struct clk *clk) +ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in) { - long long rate_in = clk_get_parent_rate(clk); - struct k210_pll *pll = to_k210_pll(clk); u64 r, f, od; - u32 reg = readl(pll->reg); + u32 reg = readl(priv->base + k210_plls[id].off); if (rate_in < 0 || (reg & K210_PLL_BYPASS)) return rate_in; @@ -491,57 +519,58 @@ static ulong k210_pll_get_rate(struct clk *clk) * Wait for the PLL to be locked. If the PLL is not locked, try clearing the * slip before retrying */ -static void k210_pll_waitfor_lock(struct k210_pll *pll) +void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id) { + const struct k210_pll_params *pll = &k210_plls[id]; u32 mask = GENMASK(pll->width - 1, 0) << pll->shift; while (true) { - u32 reg = readl(pll->lock); + u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK); if ((reg & mask) == mask) break; reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP); - writel(reg, pll->lock); + writel(reg, priv->base + K210_SYSCTL_PLL_LOCK); } } /* Adapted from sysctl_pll_enable */ -static int k210_pll_enable(struct clk *clk) +int k210_pll_enable(struct k210_clk_priv *priv, int id) { - struct k210_pll *pll = to_k210_pll(clk); - u32 reg = readl(pll->reg); + const struct k210_pll_params *pll = &k210_plls[id]; + u32 reg = readl(priv->base + pll->off); if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && !(reg & K210_PLL_RESET)) return 0; reg |= K210_PLL_PWRD; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); /* Ensure reset is low before asserting it */ reg &= ~K210_PLL_RESET; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); reg |= K210_PLL_RESET; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); nop(); nop(); reg &= ~K210_PLL_RESET; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); - k210_pll_waitfor_lock(pll); + k210_pll_waitfor_lock(priv, id); reg &= ~K210_PLL_BYPASS; reg |= K210_PLL_EN; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); return 0; } -static int k210_pll_disable(struct clk *clk) +int k210_pll_disable(struct k210_clk_priv *priv, int id) { - struct k210_pll *pll = to_k210_pll(clk); - u32 reg = readl(pll->reg); + const struct k210_pll_params *pll = &k210_plls[id]; + u32 reg = readl(priv->base + pll->off); /* * Bypassing before powering off is important so child clocks don't stop @@ -549,37 +578,10 @@ static int k210_pll_disable(struct clk *clk) * of the cpu clock. */ reg |= K210_PLL_BYPASS; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); reg &= ~K210_PLL_PWRD; reg &= ~K210_PLL_EN; - writel(reg, pll->reg); + writel(reg, priv->base + pll->off); return 0; } - -const struct clk_ops k210_pll_ops = { - .get_rate = k210_pll_get_rate, -#ifdef CONFIG_CLK_K210_SET_RATE - .set_rate = k210_pll_set_rate, -#endif - .enable = k210_pll_enable, - .disable = k210_pll_disable, -}; - -struct clk *k210_register_pll_struct(const char *name, const char *parent_name, - struct k210_pll *pll) -{ - int ret; - struct clk *clk = &pll->clk; - - ret = clk_register(clk, CLK_K210_PLL, name, parent_name); - if (ret) - return ERR_PTR(ret); - return clk; -} - -U_BOOT_DRIVER(k210_pll) = { - .name = CLK_K210_PLL, - .id = UCLASS_CLK, - .ops = &k210_pll_ops, -}; diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h index fe852bbd92a..6b0d5b46f87 100644 --- a/include/dt-bindings/clock/k210-sysctl.h +++ b/include/dt-bindings/clock/k210-sysctl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2019-21 Sean Anderson */ #ifndef CLOCK_K210_SYSCTL_H @@ -9,52 +9,50 @@ /* * Arbitrary identifiers for clocks. */ -#define K210_CLK_NONE 0 -#define K210_CLK_IN0_H 1 -#define K210_CLK_PLL0_H 2 -#define K210_CLK_PLL0 3 -#define K210_CLK_PLL1 4 -#define K210_CLK_PLL2 5 -#define K210_CLK_PLL2_H 6 -#define K210_CLK_CPU 7 -#define K210_CLK_SRAM0 8 -#define K210_CLK_SRAM1 9 -#define K210_CLK_APB0 10 -#define K210_CLK_APB1 11 -#define K210_CLK_APB2 12 -#define K210_CLK_ROM 13 -#define K210_CLK_DMA 14 -#define K210_CLK_AI 15 -#define K210_CLK_DVP 16 -#define K210_CLK_FFT 17 -#define K210_CLK_GPIO 18 -#define K210_CLK_SPI0 19 -#define K210_CLK_SPI1 20 -#define K210_CLK_SPI2 21 -#define K210_CLK_SPI3 22 -#define K210_CLK_I2S0 23 -#define K210_CLK_I2S1 24 -#define K210_CLK_I2S2 25 -#define K210_CLK_I2S0_M 26 -#define K210_CLK_I2S1_M 27 -#define K210_CLK_I2S2_M 28 -#define K210_CLK_I2C0 29 -#define K210_CLK_I2C1 30 -#define K210_CLK_I2C2 31 -#define K210_CLK_UART1 32 -#define K210_CLK_UART2 33 -#define K210_CLK_UART3 34 -#define K210_CLK_AES 35 -#define K210_CLK_FPIOA 36 -#define K210_CLK_TIMER0 37 -#define K210_CLK_TIMER1 38 -#define K210_CLK_TIMER2 39 -#define K210_CLK_WDT0 40 -#define K210_CLK_WDT1 41 -#define K210_CLK_SHA 42 -#define K210_CLK_OTP 43 -#define K210_CLK_RTC 44 -#define K210_CLK_ACLK 45 -#define K210_CLK_CLINT 46 + +#define K210_CLK_PLL0 0 +#define K210_CLK_PLL1 1 +#define K210_CLK_PLL2 2 +#define K210_CLK_CPU 3 +#define K210_CLK_SRAM0 4 +#define K210_CLK_SRAM1 5 +#define K210_CLK_ACLK 6 +#define K210_CLK_CLINT 7 +#define K210_CLK_APB0 8 +#define K210_CLK_APB1 9 +#define K210_CLK_APB2 10 +#define K210_CLK_ROM 11 +#define K210_CLK_DMA 12 +#define K210_CLK_AI 13 +#define K210_CLK_DVP 14 +#define K210_CLK_FFT 15 +#define K210_CLK_GPIO 16 +#define K210_CLK_SPI0 17 +#define K210_CLK_SPI1 18 +#define K210_CLK_SPI2 19 +#define K210_CLK_SPI3 20 +#define K210_CLK_I2S0 21 +#define K210_CLK_I2S1 22 +#define K210_CLK_I2S2 23 +#define K210_CLK_I2S0_M 24 +#define K210_CLK_I2S1_M 25 +#define K210_CLK_I2S2_M 26 +#define K210_CLK_I2C0 27 +#define K210_CLK_I2C1 28 +#define K210_CLK_I2C2 29 +#define K210_CLK_UART1 30 +#define K210_CLK_UART2 31 +#define K210_CLK_UART3 32 +#define K210_CLK_AES 33 +#define K210_CLK_FPIOA 34 +#define K210_CLK_TIMER0 35 +#define K210_CLK_TIMER1 36 +#define K210_CLK_TIMER2 37 +#define K210_CLK_WDT0 38 +#define K210_CLK_WDT1 39 +#define K210_CLK_SHA 40 +#define K210_CLK_OTP 41 +#define K210_CLK_RTC 42 +#define K210_CLK_IN0 43 #endif /* CLOCK_K210_SYSCTL_H */ diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h index 95b8494f40f..16fd5a5b688 100644 --- a/include/kendryte/pll.h +++ b/include/kendryte/pll.h @@ -25,16 +25,6 @@ #define K210_PLL_CLEAR_SLIP 2 #define K210_PLL_TEST_OUT 3 -struct k210_pll { - struct clk clk; - void __iomem *reg; /* Base PLL register */ - void __iomem *lock; /* Common PLL lock register */ - u8 shift; /* Offset of bits in lock register */ - u8 width; /* Width of lock bits to test against */ -}; - -#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk) - struct k210_pll_config { u8 r; u8 f; @@ -51,8 +41,18 @@ TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, #endif -extern const struct clk_ops k210_pll_ops; +/** + * struct k210_clk_priv - K210 clock driver private data + * @base: The base address of the sysctl device + * @in0: The "in0" external oscillator + */ +struct k210_clk_priv { + void __iomem *base; + struct clk in0; +}; -struct clk *k210_register_pll_struct(const char *name, const char *parent_name, - struct k210_pll *pll); +ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, ulong rate_in); +ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in); +int k210_pll_enable(struct k210_clk_priv *priv, int id); +int k210_pll_disable(struct k210_clk_priv *priv, int id); #endif /* K210_PLL_H */ From af9f997436595495748fccf6232987c72b2e58c8 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:09 -0400 Subject: [PATCH 089/250] clk: k210: Move pll into the rest of the driver Now that there no separate PLL driver, we can no longer make the PLL functions static. By moving the PLL driver in with the rest of the clock code, we can make these functions static again. We still keep the pll header for unit testing, but it is pretty reduced. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/kendryte/Makefile | 2 +- drivers/clk/kendryte/clk.c | 606 +++++++++++++++++++++++++++++++++- drivers/clk/kendryte/pll.c | 587 -------------------------------- include/kendryte/clk.h | 35 -- include/kendryte/pll.h | 34 -- 5 files changed, 601 insertions(+), 663 deletions(-) delete mode 100644 drivers/clk/kendryte/pll.c delete mode 100644 include/kendryte/clk.h diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile index 6fb68253ae0..6710a1db723 100644 --- a/drivers/clk/kendryte/Makefile +++ b/drivers/clk/kendryte/Makefile @@ -1 +1 @@ -obj-y += bypass.o clk.o pll.o +obj-y += bypass.o clk.o diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index 34e8e742a69..de9db843615 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -2,17 +2,30 @@ /* * Copyright (C) 2019-20 Sean Anderson */ -#include +#define LOG_CATEGORY UCLASS_CLK #include -#include -#include +#include +#include +#include #include #include #include - -#include +#include +#include +#include #include +#include + +/** + * struct k210_clk_priv - K210 clock driver private data + * @base: The base address of the sysctl device + * @in0: The "in0" external oscillator + */ +struct k210_clk_priv { + void __iomem *base; + struct clk in0; +}; /* * All parameters for different sub-clocks are collected into parameter arrays. @@ -248,6 +261,30 @@ static const struct k210_mux_params k210_muxes[] = { #undef MUX #undef MUX_LIST +/** + * struct k210_pll_params - K210 PLL parameters + * @off: The offset of the PLL from the base sysctl address + * @shift: The offset of the LSB of the lock status + * @width: The number of bits in the lock status + */ +struct k210_pll_params { + u8 off; + u8 shift; + u8 width; +}; + +static const struct k210_pll_params k210_plls[] = { +#define PLL(_off, _shift, _width) { \ + .off = (_off), \ + .shift = (_shift), \ + .width = (_width), \ +} + [0] = PLL(K210_SYSCTL_PLL0, 0, 2), + [1] = PLL(K210_SYSCTL_PLL1, 8, 1), + [2] = PLL(K210_SYSCTL_PLL2, 16, 1), +#undef PLL +}; + /** * enum k210_clk_flags - The type of a K210 clock * @K210_CLKF_MUX: This clock has a mux and not a static parent @@ -286,7 +323,6 @@ struct k210_clk_params { }; }; - static const struct k210_clk_params k210_clks[] = { #if CONFIG_IS_ENABLED(CMD_CLK) #define NAME(_name) .name = (_name), @@ -382,6 +418,564 @@ static const struct k210_clk_params k210_clks[] = { #undef CLK_LIST }; +#define K210_PLL_CLKR GENMASK(3, 0) +#define K210_PLL_CLKF GENMASK(9, 4) +#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */ +#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */ +#define K210_PLL_RESET BIT(20) +#define K210_PLL_PWRD BIT(21) /* PoWeReD */ +#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */ +#define K210_PLL_BYPASS BIT(23) +#define K210_PLL_TEST BIT(24) +#define K210_PLL_EN BIT(25) +#define K210_PLL_TEST_EN BIT(26) + +#define K210_PLL_LOCK 0 +#define K210_PLL_CLEAR_SLIP 2 +#define K210_PLL_TEST_OUT 3 + +#ifdef CONFIG_CLK_K210_SET_RATE +static int k210_pll_enable(struct k210_clk_priv *priv, int id); +static int k210_pll_disable(struct k210_clk_priv *priv, int id); +static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in); + +/* + * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc. + * General-Purpose PLL. The logical layout of the PLL with internal feedback is + * approximately the following: + * + * +---------------+ + * |reference clock| + * +---------------+ + * | + * v + * +--+ + * |/r| + * +--+ + * | + * v + * +-------------+ + * |divided clock| + * +-------------+ + * | + * v + * +--------------+ + * |phase detector|<---+ + * +--------------+ | + * | | + * v +--------------+ + * +---+ |feedback clock| + * |VCO| +--------------+ + * +---+ ^ + * | +--+ | + * +--->|/f|---+ + * | +--+ + * v + * +---+ + * |/od| + * +---+ + * | + * v + * +------+ + * |output| + * +------+ + * + * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode, + * the effect of the division by f is to multiply the input frequency. The + * equation for the output rate is + * rate = (rate_in * f) / (r * od). + * Moving knowns to one side of the equation, we get + * rate / rate_in = f / (r * od) + * Rearranging slightly, + * abs_error = abs((rate / rate_in) - (f / (r * od))). + * To get relative, error, we divide by the expected ratio + * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in). + * Simplifying, + * error = abs(1 - f / (r * od)) / (rate / rate_in) + * error = abs(1 - (f * rate_in) / (r * od * rate)) + * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate, + * error = abs((f * inv_ratio) / (r * od) - 1) + * This is the error used in evaluating parameters. + * + * r and od are four bits each, while f is six bits. Because r and od are + * multiplied together, instead of the full 256 values possible if both bits + * were used fully, there are only 97 distinct products. Combined with f, there + * are 6208 theoretical settings for the PLL. However, most of these settings + * can be ruled out immediately because they do not have the correct ratio. + * + * In addition to the constraint of approximating the desired ratio, parameters + * must also keep internal pll frequencies within acceptable ranges. The divided + * clock's minimum and maximum frequencies have a ratio of around 128. This + * leaves fairly substantial room to work with, especially since the only + * affected parameter is r. The VCO's minimum and maximum frequency have a ratio + * of 5, which is considerably more restrictive. + * + * The r and od factors are stored in a table. This is to make it easy to find + * the next-largest product. Some products have multiple factorizations, but + * only when one factor has at least a 2.5x ratio to the factors of the other + * factorization. This is because any smaller ratio would not make a difference + * when ensuring the VCO's frequency is within spec. + * + * Throughout the calculation function, fixed point arithmetic is used. Because + * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit + * 32.32 fixed-point numbers are used to represent ratios. In general, to + * implement division, the numerator is first multiplied by 2^32. This gives a + * result where the whole number part is in the upper 32 bits, and the fraction + * is in the lower 32 bits. + * + * In general, rounding is done to the closest integer. This helps find the best + * approximation for the ratio. Rounding in one direction (e.g down) could cause + * the function to miss a better ratio with one of the parameters increased by + * one. + */ + +/* + * The factors table was generated with the following python code: + * + * def p(x, y): + * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5) + * + * factors = {} + * for i in range(1, 17): + * for j in range(1, 17): + * fs = factors.get(i*j) or [] + * if fs == [] or all([ + * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y)) + * for (x, y) in fs]): + * fs.append((i, j)) + * factors[i*j] = fs + * + * for k, l in sorted(factors.items()): + * for v in l: + * print("PACK(%s, %s)," % v) + */ +#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF)) +#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1) +#define UNPACK_OD(val) (((val) & 0xF) + 1) +static const u8 factors[] = { + PACK(1, 1), + PACK(1, 2), + PACK(1, 3), + PACK(1, 4), + PACK(1, 5), + PACK(1, 6), + PACK(1, 7), + PACK(1, 8), + PACK(1, 9), + PACK(3, 3), + PACK(1, 10), + PACK(1, 11), + PACK(1, 12), + PACK(3, 4), + PACK(1, 13), + PACK(1, 14), + PACK(1, 15), + PACK(3, 5), + PACK(1, 16), + PACK(4, 4), + PACK(2, 9), + PACK(2, 10), + PACK(3, 7), + PACK(2, 11), + PACK(2, 12), + PACK(5, 5), + PACK(2, 13), + PACK(3, 9), + PACK(2, 14), + PACK(2, 15), + PACK(2, 16), + PACK(3, 11), + PACK(5, 7), + PACK(3, 12), + PACK(3, 13), + PACK(4, 10), + PACK(3, 14), + PACK(4, 11), + PACK(3, 15), + PACK(3, 16), + PACK(7, 7), + PACK(5, 10), + PACK(4, 13), + PACK(6, 9), + PACK(5, 11), + PACK(4, 14), + PACK(4, 15), + PACK(7, 9), + PACK(4, 16), + PACK(5, 13), + PACK(6, 11), + PACK(5, 14), + PACK(6, 12), + PACK(5, 15), + PACK(7, 11), + PACK(6, 13), + PACK(5, 16), + PACK(9, 9), + PACK(6, 14), + PACK(8, 11), + PACK(6, 15), + PACK(7, 13), + PACK(6, 16), + PACK(7, 14), + PACK(9, 11), + PACK(10, 10), + PACK(8, 13), + PACK(7, 15), + PACK(9, 12), + PACK(10, 11), + PACK(7, 16), + PACK(9, 13), + PACK(8, 15), + PACK(11, 11), + PACK(9, 14), + PACK(8, 16), + PACK(10, 13), + PACK(11, 12), + PACK(9, 15), + PACK(10, 14), + PACK(11, 13), + PACK(9, 16), + PACK(10, 15), + PACK(11, 14), + PACK(12, 13), + PACK(10, 16), + PACK(11, 15), + PACK(12, 14), + PACK(13, 13), + PACK(11, 16), + PACK(12, 15), + PACK(13, 14), + PACK(12, 16), + PACK(13, 15), + PACK(14, 14), + PACK(13, 16), + PACK(14, 15), + PACK(14, 16), + PACK(15, 15), + PACK(15, 16), + PACK(16, 16), +}; + +TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, + struct k210_pll_config *best) +{ + int i; + s64 error, best_error; + u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */ + u64 max_r; + u64 r, f, od; + + /* + * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the + * VCO frequency. These are not the same limits as below because od can + * reduce the output frequency by 16. + */ + if (rate > 1750000000 || rate < 21250000) + return -EINVAL; + + /* Similar restrictions on the input rate */ + if (rate_in > 1750000000 || rate_in < 13300000) + return -EINVAL; + + ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in); + inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate); + /* Can't increase by more than 64 or reduce by more than 256 */ + if (rate > rate_in && ratio > (64ULL << 32)) + return -EINVAL; + else if (rate <= rate_in && inv_ratio > (256ULL << 32)) + return -EINVAL; + + /* + * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3 + * MHz. There is no minimum, since the only way to get a higher input + * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs + * cannot output frequencies greater than 1.75 GHz, the minimum would + * never be greater than one. + */ + max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000); + + /* Variables get immediately incremented, so start at -1th iteration */ + i = -1; + f = 0; + r = 0; + od = 0; + best_error = S64_MAX; + error = best_error; + /* do-while here so we always try at least one ratio */ + do { + /* + * Whether we swapped r and od while enforcing frequency limits + */ + bool swapped = false; + u64 last_od = od; + u64 last_r = r; + + /* + * Try the next largest value for f (or r and od) and + * recalculate the other parameters based on that + */ + if (rate > rate_in) { + /* + * Skip factors of the same product if we already tried + * out that product + */ + do { + i++; + r = UNPACK_R(factors[i]); + od = UNPACK_OD(factors[i]); + } while (i + 1 < ARRAY_SIZE(factors) && + r * od == last_r * last_od); + + /* Round close */ + f = (r * od * ratio + BIT(31)) >> 32; + if (f > 64) + f = 64; + } else { + u64 tmp = ++f * inv_ratio; + bool round_up = !!(tmp & BIT(31)); + u32 goal = (tmp >> 32) + round_up; + u32 err, last_err; + + /* Get the next r/od pair in factors */ + while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) { + i++; + r = UNPACK_R(factors[i]); + od = UNPACK_OD(factors[i]); + } + + /* + * This is a case of double rounding. If we rounded up + * above, we need to round down (in cases of ties) here. + * This prevents off-by-one errors resulting from + * choosing X+2 over X when X.Y rounds up to X+1 and + * there is no r * od = X+1. For the converse, when X.Y + * is rounded down to X, we should choose X+1 over X-1. + */ + err = abs(r * od - goal); + last_err = abs(last_r * last_od - goal); + if (last_err < err || (round_up && last_err == err)) { + i--; + r = last_r; + od = last_od; + } + } + + /* + * Enforce limits on internal clock frequencies. If we + * aren't in spec, try swapping r and od. If everything is + * in-spec, calculate the relative error. + */ + while (true) { + /* + * Whether the intermediate frequencies are out-of-spec + */ + bool out_of_spec = false; + + if (r > max_r) { + out_of_spec = true; + } else { + /* + * There is no way to only divide once; we need + * to examine the frequency with and without the + * effect of od. + */ + u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); + + if (vco > 1750000000 || vco < 340000000) + out_of_spec = true; + } + + if (out_of_spec) { + if (!swapped) { + u64 tmp = r; + + r = od; + od = tmp; + swapped = true; + continue; + } else { + /* + * Try looking ahead to see if there are + * additional factors for the same + * product. + */ + if (i + 1 < ARRAY_SIZE(factors)) { + u64 new_r, new_od; + + i++; + new_r = UNPACK_R(factors[i]); + new_od = UNPACK_OD(factors[i]); + if (r * od == new_r * new_od) { + r = new_r; + od = new_od; + swapped = false; + continue; + } + i--; + } + break; + } + } + + error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); + /* The lower 16 bits are spurious */ + error = abs((error - BIT(32))) >> 16; + + if (error < best_error) { + best->r = r; + best->f = f; + best->od = od; + best_error = error; + } + break; + } + } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0); + + if (best_error == S64_MAX) + return -EINVAL; + + log_debug("best error %lld\n", best_error); + return 0; +} + +static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, + ulong rate_in) +{ + int err; + const struct k210_pll_params *pll = &k210_plls[id]; + struct k210_pll_config config = {}; + u32 reg; + + if (rate_in < 0) + return rate_in; + + log_debug("Calculating parameters with rate=%lu and rate_in=%lu\n", + rate, rate_in); + err = k210_pll_calc_config(rate, rate_in, &config); + if (err) + return err; + log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od); + + /* + * Don't use clk_disable as it might not actually disable the pll due to + * refcounting + */ + k210_pll_disable(priv, id); + + reg = readl(priv->base + pll->off); + reg &= ~K210_PLL_CLKR + & ~K210_PLL_CLKF + & ~K210_PLL_CLKOD + & ~K210_PLL_BWADJ; + reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1) + | FIELD_PREP(K210_PLL_CLKF, config.f - 1) + | FIELD_PREP(K210_PLL_CLKOD, config.od - 1) + | FIELD_PREP(K210_PLL_BWADJ, config.f - 1); + writel(reg, priv->base + pll->off); + + err = k210_pll_enable(priv, id); + + serial_setbrg(); + return k210_pll_get_rate(priv, id, rate); +} +#else +static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, + ulong rate_in) +{ + return -ENOSYS; +} +#endif /* CONFIG_CLK_K210_SET_RATE */ + +static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, + ulong rate_in) +{ + u64 r, f, od; + u32 reg = readl(priv->base + k210_plls[id].off); + + if (rate_in < 0 || (reg & K210_PLL_BYPASS)) + return rate_in; + + if (!(reg & K210_PLL_PWRD)) + return 0; + + r = FIELD_GET(K210_PLL_CLKR, reg) + 1; + f = FIELD_GET(K210_PLL_CLKF, reg) + 1; + od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; + + return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od); +} + +/* + * Wait for the PLL to be locked. If the PLL is not locked, try clearing the + * slip before retrying + */ +static void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id) +{ + const struct k210_pll_params *pll = &k210_plls[id]; + u32 mask = (BIT(pll->width) - 1) << pll->shift; + + while (true) { + u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK); + + if ((reg & mask) == mask) + break; + + reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP); + writel(reg, priv->base + K210_SYSCTL_PLL_LOCK); + } +} + +/* Adapted from sysctl_pll_enable */ +static int k210_pll_enable(struct k210_clk_priv *priv, int id) +{ + const struct k210_pll_params *pll = &k210_plls[id]; + u32 reg = readl(priv->base + pll->off); + + if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && + !(reg & K210_PLL_RESET)) + return 0; + + reg |= K210_PLL_PWRD; + writel(reg, priv->base + pll->off); + + /* Ensure reset is low before asserting it */ + reg &= ~K210_PLL_RESET; + writel(reg, priv->base + pll->off); + reg |= K210_PLL_RESET; + writel(reg, priv->base + pll->off); + nop(); + nop(); + reg &= ~K210_PLL_RESET; + writel(reg, priv->base + pll->off); + + k210_pll_waitfor_lock(priv, id); + + reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; + writel(reg, priv->base + pll->off); + + return 0; +} + +static int k210_pll_disable(struct k210_clk_priv *priv, int id) +{ + const struct k210_pll_params *pll = &k210_plls[id]; + u32 reg = readl(priv->base + pll->off); + + /* + * Bypassing before powering off is important so child clocks don't stop + * working. This is especially important for pll0, the indirect parent + * of the cpu clock. + */ + reg |= K210_PLL_BYPASS; + writel(reg, priv->base + pll->off); + + reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; + writel(reg, priv->base + pll->off); + return 0; +} + static u32 k210_clk_readl(struct k210_clk_priv *priv, u8 off, u8 shift, u8 width) { diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c deleted file mode 100644 index 1f0275c83f7..00000000000 --- a/drivers/clk/kendryte/pll.c +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019-20 Sean Anderson - */ -#define LOG_CATEGORY UCLASS_CLK - -#include -#include -/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - * struct k210_pll_params - K210 PLL parameters - * @off: The offset of the PLL from the base sysctl address - * @shift: The offset of the LSB of the lock status - * @width: The number of bits in the lock status - */ -struct k210_pll_params { - u8 off; - u8 shift; - u8 width; -}; - -static const struct k210_pll_params k210_plls[] = { -#define PLL(_off, _shift, _width) { \ - .off = (_off), \ - .shift = (_shift), \ - .width = (_width), \ -} - [0] = PLL(K210_SYSCTL_PLL0, 0, 2), - [1] = PLL(K210_SYSCTL_PLL1, 8, 1), - [2] = PLL(K210_SYSCTL_PLL2, 16, 1), -#undef PLL -}; - -#ifdef CONFIG_CLK_K210_SET_RATE -int k210_pll_enable(struct k210_clk_priv *priv, int id); -int k210_pll_disable(struct k210_clk_priv *priv, int id); -ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in); - -/* - * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc. - * General-Purpose PLL. The logical layout of the PLL with internal feedback is - * approximately the following: - * - * +---------------+ - * |reference clock| - * +---------------+ - * | - * v - * +--+ - * |/r| - * +--+ - * | - * v - * +-------------+ - * |divided clock| - * +-------------+ - * | - * v - * +--------------+ - * |phase detector|<---+ - * +--------------+ | - * | | - * v +--------------+ - * +---+ |feedback clock| - * |VCO| +--------------+ - * +---+ ^ - * | +--+ | - * +--->|/f|---+ - * | +--+ - * v - * +---+ - * |/od| - * +---+ - * | - * v - * +------+ - * |output| - * +------+ - * - * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode, - * the effect of the division by f is to multiply the input frequency. The - * equation for the output rate is - * rate = (rate_in * f) / (r * od). - * Moving knowns to one side of the equation, we get - * rate / rate_in = f / (r * od) - * Rearranging slightly, - * abs_error = abs((rate / rate_in) - (f / (r * od))). - * To get relative, error, we divide by the expected ratio - * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in). - * Simplifying, - * error = abs(1 - f / (r * od)) / (rate / rate_in) - * error = abs(1 - (f * rate_in) / (r * od * rate)) - * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate, - * error = abs((f * inv_ratio) / (r * od) - 1) - * This is the error used in evaluating parameters. - * - * r and od are four bits each, while f is six bits. Because r and od are - * multiplied together, instead of the full 256 values possible if both bits - * were used fully, there are only 97 distinct products. Combined with f, there - * are 6208 theoretical settings for the PLL. However, most of these settings - * can be ruled out immediately because they do not have the correct ratio. - * - * In addition to the constraint of approximating the desired ratio, parameters - * must also keep internal pll frequencies within acceptable ranges. The divided - * clock's minimum and maximum frequencies have a ratio of around 128. This - * leaves fairly substantial room to work with, especially since the only - * affected parameter is r. The VCO's minimum and maximum frequency have a ratio - * of 5, which is considerably more restrictive. - * - * The r and od factors are stored in a table. This is to make it easy to find - * the next-largest product. Some products have multiple factorizations, but - * only when one factor has at least a 2.5x ratio to the factors of the other - * factorization. This is because any smaller ratio would not make a difference - * when ensuring the VCO's frequency is within spec. - * - * Throughout the calculation function, fixed point arithmetic is used. Because - * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit - * 32.32 fixed-point numbers are used to represent ratios. In general, to - * implement division, the numerator is first multiplied by 2^32. This gives a - * result where the whole number part is in the upper 32 bits, and the fraction - * is in the lower 32 bits. - * - * In general, rounding is done to the closest integer. This helps find the best - * approximation for the ratio. Rounding in one direction (e.g down) could cause - * the function to miss a better ratio with one of the parameters increased by - * one. - */ - -/* - * The factors table was generated with the following python code: - * - * def p(x, y): - * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5) - * - * factors = {} - * for i in range(1, 17): - * for j in range(1, 17): - * fs = factors.get(i*j) or [] - * if fs == [] or all([ - * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y)) - * for (x, y) in fs]): - * fs.append((i, j)) - * factors[i*j] = fs - * - * for k, l in sorted(factors.items()): - * for v in l: - * print("PACK(%s, %s)," % v) - */ -#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF)) -#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1) -#define UNPACK_OD(val) (((val) & 0xF) + 1) -static const u8 factors[] = { - PACK(1, 1), - PACK(1, 2), - PACK(1, 3), - PACK(1, 4), - PACK(1, 5), - PACK(1, 6), - PACK(1, 7), - PACK(1, 8), - PACK(1, 9), - PACK(3, 3), - PACK(1, 10), - PACK(1, 11), - PACK(1, 12), - PACK(3, 4), - PACK(1, 13), - PACK(1, 14), - PACK(1, 15), - PACK(3, 5), - PACK(1, 16), - PACK(4, 4), - PACK(2, 9), - PACK(2, 10), - PACK(3, 7), - PACK(2, 11), - PACK(2, 12), - PACK(5, 5), - PACK(2, 13), - PACK(3, 9), - PACK(2, 14), - PACK(2, 15), - PACK(2, 16), - PACK(3, 11), - PACK(5, 7), - PACK(3, 12), - PACK(3, 13), - PACK(4, 10), - PACK(3, 14), - PACK(4, 11), - PACK(3, 15), - PACK(3, 16), - PACK(7, 7), - PACK(5, 10), - PACK(4, 13), - PACK(6, 9), - PACK(5, 11), - PACK(4, 14), - PACK(4, 15), - PACK(7, 9), - PACK(4, 16), - PACK(5, 13), - PACK(6, 11), - PACK(5, 14), - PACK(6, 12), - PACK(5, 15), - PACK(7, 11), - PACK(6, 13), - PACK(5, 16), - PACK(9, 9), - PACK(6, 14), - PACK(8, 11), - PACK(6, 15), - PACK(7, 13), - PACK(6, 16), - PACK(7, 14), - PACK(9, 11), - PACK(10, 10), - PACK(8, 13), - PACK(7, 15), - PACK(9, 12), - PACK(10, 11), - PACK(7, 16), - PACK(9, 13), - PACK(8, 15), - PACK(11, 11), - PACK(9, 14), - PACK(8, 16), - PACK(10, 13), - PACK(11, 12), - PACK(9, 15), - PACK(10, 14), - PACK(11, 13), - PACK(9, 16), - PACK(10, 15), - PACK(11, 14), - PACK(12, 13), - PACK(10, 16), - PACK(11, 15), - PACK(12, 14), - PACK(13, 13), - PACK(11, 16), - PACK(12, 15), - PACK(13, 14), - PACK(12, 16), - PACK(13, 15), - PACK(14, 14), - PACK(13, 16), - PACK(14, 15), - PACK(14, 16), - PACK(15, 15), - PACK(15, 16), - PACK(16, 16), -}; - -TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, - struct k210_pll_config *best) -{ - int i; - s64 error, best_error; - u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */ - u64 max_r; - u64 r, f, od; - - /* - * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the - * VCO frequency. These are not the same limits as below because od can - * reduce the output frequency by 16. - */ - if (rate > 1750000000 || rate < 21250000) - return -EINVAL; - - /* Similar restrictions on the input rate */ - if (rate_in > 1750000000 || rate_in < 13300000) - return -EINVAL; - - ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in); - inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate); - /* Can't increase by more than 64 or reduce by more than 256 */ - if (rate > rate_in && ratio > (64ULL << 32)) - return -EINVAL; - else if (rate <= rate_in && inv_ratio > (256ULL << 32)) - return -EINVAL; - - /* - * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3 - * MHz. There is no minimum, since the only way to get a higher input - * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs - * cannot output frequencies greater than 1.75 GHz, the minimum would - * never be greater than one. - */ - max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000); - - /* Variables get immediately incremented, so start at -1th iteration */ - i = -1; - f = 0; - r = 0; - od = 0; - best_error = S64_MAX; - error = best_error; - /* do-while here so we always try at least one ratio */ - do { - /* - * Whether we swapped r and od while enforcing frequency limits - */ - bool swapped = false; - u64 last_od = od; - u64 last_r = r; - - /* - * Try the next largest value for f (or r and od) and - * recalculate the other parameters based on that - */ - if (rate > rate_in) { - /* - * Skip factors of the same product if we already tried - * out that product - */ - do { - i++; - r = UNPACK_R(factors[i]); - od = UNPACK_OD(factors[i]); - } while (i + 1 < ARRAY_SIZE(factors) && - r * od == last_r * last_od); - - /* Round close */ - f = (r * od * ratio + BIT(31)) >> 32; - if (f > 64) - f = 64; - } else { - u64 tmp = ++f * inv_ratio; - bool round_up = !!(tmp & BIT(31)); - u32 goal = (tmp >> 32) + round_up; - u32 err, last_err; - - /* Get the next r/od pair in factors */ - while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) { - i++; - r = UNPACK_R(factors[i]); - od = UNPACK_OD(factors[i]); - } - - /* - * This is a case of double rounding. If we rounded up - * above, we need to round down (in cases of ties) here. - * This prevents off-by-one errors resulting from - * choosing X+2 over X when X.Y rounds up to X+1 and - * there is no r * od = X+1. For the converse, when X.Y - * is rounded down to X, we should choose X+1 over X-1. - */ - err = abs(r * od - goal); - last_err = abs(last_r * last_od - goal); - if (last_err < err || (round_up && last_err == err)) { - i--; - r = last_r; - od = last_od; - } - } - - /* - * Enforce limits on internal clock frequencies. If we - * aren't in spec, try swapping r and od. If everything is - * in-spec, calculate the relative error. - */ - while (true) { - /* - * Whether the intermediate frequencies are out-of-spec - */ - bool out_of_spec = false; - - if (r > max_r) { - out_of_spec = true; - } else { - /* - * There is no way to only divide once; we need - * to examine the frequency with and without the - * effect of od. - */ - u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); - - if (vco > 1750000000 || vco < 340000000) - out_of_spec = true; - } - - if (out_of_spec) { - if (!swapped) { - u64 tmp = r; - - r = od; - od = tmp; - swapped = true; - continue; - } else { - /* - * Try looking ahead to see if there are - * additional factors for the same - * product. - */ - if (i + 1 < ARRAY_SIZE(factors)) { - u64 new_r, new_od; - - i++; - new_r = UNPACK_R(factors[i]); - new_od = UNPACK_OD(factors[i]); - if (r * od == new_r * new_od) { - r = new_r; - od = new_od; - swapped = false; - continue; - } - i--; - } - break; - } - } - - error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); - /* The lower 16 bits are spurious */ - error = abs((error - BIT(32))) >> 16; - - if (error < best_error) { - best->r = r; - best->f = f; - best->od = od; - best_error = error; - } - break; - } - } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0); - - if (best_error == S64_MAX) - return -EINVAL; - - log_debug("best error %lld\n", best_error); - return 0; -} - -static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, - ulong rate_in) -{ - int err; - const struct k210_pll_params *pll = &k210_plls[id]; - struct k210_pll_config config = {}; - u32 reg; - - if (rate_in < 0) - return rate_in; - - log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n", - rate, rate_in); - err = k210_pll_calc_config(rate, rate_in, &config); - if (err) - return err; - log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od); - - /* - * Don't use clk_disable as it might not actually disable the pll due to - * refcounting - */ - k210_pll_disable(clk); - - reg = readl(priv->base + pll->off); - reg &= ~K210_PLL_CLKR - & ~K210_PLL_CLKF - & ~K210_PLL_CLKOD - & ~K210_PLL_BWADJ; - reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1) - | FIELD_PREP(K210_PLL_CLKF, config.f - 1) - | FIELD_PREP(K210_PLL_CLKOD, config.od - 1) - | FIELD_PREP(K210_PLL_BWADJ, config.f - 1); - writel(reg, priv->base + pll->off); - - err = k210_pll_enable(clk); - if (err) - return err; - - serial_setbrg(); - return clk_get_rate(clk); -} -#else -ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, - ulong rate_in) -{ - return -ENOSYS; -} -#endif /* CONFIG_CLK_K210_SET_RATE */ - -ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in) -{ - u64 r, f, od; - u32 reg = readl(priv->base + k210_plls[id].off); - - if (rate_in < 0 || (reg & K210_PLL_BYPASS)) - return rate_in; - - if (!(reg & K210_PLL_PWRD)) - return 0; - - r = FIELD_GET(K210_PLL_CLKR, reg) + 1; - f = FIELD_GET(K210_PLL_CLKF, reg) + 1; - od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; - - return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od); -} - -/* - * Wait for the PLL to be locked. If the PLL is not locked, try clearing the - * slip before retrying - */ -void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id) -{ - const struct k210_pll_params *pll = &k210_plls[id]; - u32 mask = GENMASK(pll->width - 1, 0) << pll->shift; - - while (true) { - u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK); - - if ((reg & mask) == mask) - break; - - reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP); - writel(reg, priv->base + K210_SYSCTL_PLL_LOCK); - } -} - -/* Adapted from sysctl_pll_enable */ -int k210_pll_enable(struct k210_clk_priv *priv, int id) -{ - const struct k210_pll_params *pll = &k210_plls[id]; - u32 reg = readl(priv->base + pll->off); - - if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && - !(reg & K210_PLL_RESET)) - return 0; - - reg |= K210_PLL_PWRD; - writel(reg, priv->base + pll->off); - - /* Ensure reset is low before asserting it */ - reg &= ~K210_PLL_RESET; - writel(reg, priv->base + pll->off); - reg |= K210_PLL_RESET; - writel(reg, priv->base + pll->off); - nop(); - nop(); - reg &= ~K210_PLL_RESET; - writel(reg, priv->base + pll->off); - - k210_pll_waitfor_lock(priv, id); - - reg &= ~K210_PLL_BYPASS; - reg |= K210_PLL_EN; - writel(reg, priv->base + pll->off); - - return 0; -} - -int k210_pll_disable(struct k210_clk_priv *priv, int id) -{ - const struct k210_pll_params *pll = &k210_plls[id]; - u32 reg = readl(priv->base + pll->off); - - /* - * Bypassing before powering off is important so child clocks don't stop - * working. This is especially important for pll0, the indirect parent - * of the cpu clock. - */ - reg |= K210_PLL_BYPASS; - writel(reg, priv->base + pll->off); - - reg &= ~K210_PLL_PWRD; - reg &= ~K210_PLL_EN; - writel(reg, priv->base + pll->off); - return 0; -} diff --git a/include/kendryte/clk.h b/include/kendryte/clk.h deleted file mode 100644 index 9c6245d468b..00000000000 --- a/include/kendryte/clk.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019-20 Sean Anderson - */ - -#ifndef K210_CLK_H -#define K210_CLK_H - -#define LOG_CATEGORY UCLASS_CLK -#include -#include - -static inline struct clk *k210_clk_gate(const char *name, - const char *parent_name, - void __iomem *reg, u8 bit_idx) -{ - return clk_register_gate(NULL, name, parent_name, 0, reg, bit_idx, 0, - NULL); -} - -static inline struct clk *k210_clk_half(const char *name, - const char *parent_name) -{ - return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 2); -} - -static inline struct clk *k210_clk_div(const char *name, - const char *parent_name, - void __iomem *reg, u8 shift, u8 width) -{ - return clk_register_divider(NULL, name, parent_name, 0, reg, shift, - width, 0); -} - -#endif /* K210_CLK_H */ diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h index 16fd5a5b688..fd16a89cb20 100644 --- a/include/kendryte/pll.h +++ b/include/kendryte/pll.h @@ -5,25 +5,7 @@ #ifndef K210_PLL_H #define K210_PLL_H -#include #include -#include - -#define K210_PLL_CLKR GENMASK(3, 0) -#define K210_PLL_CLKF GENMASK(9, 4) -#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */ -#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */ -#define K210_PLL_RESET BIT(20) -#define K210_PLL_PWRD BIT(21) /* PoWeReD */ -#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */ -#define K210_PLL_BYPASS BIT(23) -#define K210_PLL_TEST BIT(24) -#define K210_PLL_EN BIT(25) -#define K210_PLL_TEST_EN BIT(26) - -#define K210_PLL_LOCK 0 -#define K210_PLL_CLEAR_SLIP 2 -#define K210_PLL_TEST_OUT 3 struct k210_pll_config { u8 r; @@ -34,25 +16,9 @@ struct k210_pll_config { #ifdef CONFIG_UNIT_TEST TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, struct k210_pll_config *best); - #ifndef nop #define nop() #endif #endif - -/** - * struct k210_clk_priv - K210 clock driver private data - * @base: The base address of the sysctl device - * @in0: The "in0" external oscillator - */ -struct k210_clk_priv { - void __iomem *base; - struct clk in0; -}; - -ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, ulong rate_in); -ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in); -int k210_pll_enable(struct k210_clk_priv *priv, int id); -int k210_pll_disable(struct k210_clk_priv *priv, int id); #endif /* K210_PLL_H */ From 612a8334cd16a6a5310605244a44ce7f29430f0e Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:10 -0400 Subject: [PATCH 090/250] clk: k210: Implement soc_clk_dump Since we are no longer using CCF we cannot use the default soc_clk_dump. Instead, implement our own. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/kendryte/clk.c | 68 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index de9db843615..203d5f741c9 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -925,14 +925,19 @@ static void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id) } } +static bool k210_pll_enabled(u32 reg) +{ + return (reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && + !(reg & K210_PLL_RESET); +} + /* Adapted from sysctl_pll_enable */ static int k210_pll_enable(struct k210_clk_priv *priv, int id) { const struct k210_pll_params *pll = &k210_plls[id]; u32 reg = readl(priv->base + pll->off); - if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && - !(reg & K210_PLL_RESET)) + if (k210_pll_enabled(reg)) return 0; reg |= K210_PLL_PWRD; @@ -1174,3 +1179,62 @@ U_BOOT_DRIVER(k210_clk) = { .probe = k210_clk_probe, .priv_auto = sizeof(struct k210_clk_priv), }; + +#if CONFIG_IS_ENABLED(CMD_CLK) +static char show_enabled(struct k210_clk_priv *priv, int id) +{ + bool enabled; + + if (k210_clks[id].flags & K210_CLKF_PLL) { + const struct k210_pll_params *pll = + &k210_plls[k210_clks[id].pll]; + + enabled = k210_pll_enabled(readl(priv->base + pll->off)); + } else if (k210_clks[id].gate == K210_CLK_GATE_NONE) { + return '-'; + } else { + const struct k210_gate_params *gate = + &k210_gates[k210_clks[id].gate]; + + enabled = k210_clk_readl(priv, gate->off, gate->bit_idx, 1); + } + + return enabled ? 'y' : 'n'; +} + +static void show_clks(struct k210_clk_priv *priv, int id, int depth) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(k210_clks); i++) { + if (k210_clk_get_parent(priv, i) != id) + continue; + + printf(" %-9lu %-7c %*s%s\n", do_k210_clk_get_rate(priv, i), + show_enabled(priv, i), depth * 4, "", + k210_clks[i].name); + + show_clks(priv, i, depth + 1); + } +} + +int soc_clk_dump(void) +{ + int ret; + struct udevice *dev; + struct k210_clk_priv *priv; + + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk), + &dev); + if (ret) + return ret; + priv = dev_get_priv(dev); + + puts(" Rate Enabled Name\n"); + puts("------------------------\n"); + printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "", + priv->in0.dev->name); + show_clks(priv, K210_CLK_IN0, 1); + return 0; +} +#endif From 29e3067d911b498c9676a695312fa3d3e83a7e4f Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:11 -0400 Subject: [PATCH 091/250] clk: k210: Re-add support for setting rate This adds support for setting clock rates, which was left out of the initial CCF expunging. There are several tricky bits here, mostly related to the PLLS: * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks will be stopped. * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent stopping the CPU while we configure PLL0's rate, ACLK is reparented to IN0 while PLL0 is disabled. * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented, so we instead just disallow changing PLL1's rate after relocation (when we are using the AISRAM). Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/kendryte/clk.c | 89 +++++++++++++++++++++++++++++++++++--- 1 file changed, 84 insertions(+), 5 deletions(-) diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index 203d5f741c9..a2901f9b965 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -17,6 +17,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /** * struct k210_clk_priv - K210 clock driver private data * @base: The base address of the sysctl device @@ -1059,11 +1061,6 @@ static ulong k210_clk_get_rate(struct clk *clk) return do_k210_clk_get_rate(dev_get_priv(clk->dev), clk->id); } -static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate) -{ - return -ENOSYS; -} - static int do_k210_clk_set_parent(struct k210_clk_priv *priv, int id, int new) { int i; @@ -1089,6 +1086,81 @@ static int k210_clk_set_parent(struct clk *clk, struct clk *parent) parent->id); } +static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate) +{ + int parent, ret, err; + ulong rate_in, val; + const struct k210_div_params *div; + struct k210_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id == K210_CLK_IN0) + return clk_set_rate(&priv->in0, rate); + + parent = k210_clk_get_parent(priv, clk->id); + rate_in = do_k210_clk_get_rate(priv, parent); + + log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in); + + if (clk->id == K210_CLK_PLL0) { + /* Bypass ACLK so the CPU keeps going */ + ret = do_k210_clk_set_parent(priv, K210_CLK_ACLK, K210_CLK_IN0); + if (ret) + return ret; + } else if (clk->id == K210_CLK_PLL1 && gd->flags & GD_FLG_RELOC) { + /* + * We can't bypass the AI clock like we can ACLK, and after + * relocation we are using the AI ram. + */ + return -EPERM; + } + + if (k210_clks[clk->id].flags & K210_CLKF_PLL) { + ret = k210_pll_set_rate(priv, k210_clks[clk->id].pll, rate, + rate_in); + if (!IS_ERR_VALUE(ret) && clk->id == K210_CLK_PLL0) { + /* + * This may have the side effect of reparenting ACLK, + * but I don't really want to keep track of what the old + * parent was. + */ + err = do_k210_clk_set_parent(priv, K210_CLK_ACLK, + K210_CLK_PLL0); + if (err) + return err; + } + return ret; + } + + if (k210_clks[clk->id].div == K210_CLK_DIV_NONE) + return -ENOSYS; + div = &k210_divs[k210_clks[clk->id].div]; + + switch (div->type) { + case K210_DIV_ONE: + val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate); + val = val ? val - 1 : 0; + break; + case K210_DIV_EVEN: + val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, 2 * rate); + break; + case K210_DIV_POWER: + /* This is ACLK, which has no divider on IN0 */ + if (parent == K210_CLK_IN0) + return -ENOSYS; + + val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate); + val = __ffs(val); + break; + default: + assert(false); + return -EINVAL; + }; + + val = val ? val - 1 : 0; + k210_clk_writel(priv, div->off, div->shift, div->width, val); + return do_k210_clk_get_rate(priv, clk->id); +} + static int k210_clk_endisable(struct k210_clk_priv *priv, int id, bool enable) { int parent = k210_clk_get_parent(priv, id); @@ -1163,6 +1235,13 @@ static int k210_clk_probe(struct udevice *dev) if (ret) return ret; + /* + * Force setting defaults, even before relocation. This is so we can + * set the clock rate for PLL1 before we relocate into aisram. + */ + if (!(gd->flags & GD_FLG_RELOC)) + clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE); + return 0; } From df79e2b48baa2f3434645b0c74cda01d67a126e7 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:12 -0400 Subject: [PATCH 092/250] clk: k210: Don't set PLL rates if we are already at the correct rate This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/kendryte/clk.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index a2901f9b965..31487569686 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -847,21 +847,22 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, const struct k210_pll_params *pll = &k210_plls[id]; struct k210_pll_config config = {}; u32 reg; + ulong calc_rate; if (rate_in < 0) return rate_in; - log_debug("Calculating parameters with rate=%lu and rate_in=%lu\n", - rate, rate_in); err = k210_pll_calc_config(rate, rate_in, &config); if (err) return err; log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od); - /* - * Don't use clk_disable as it might not actually disable the pll due to - * refcounting - */ + /* Don't bother setting the rate if we're already at that rate */ + calc_rate = DIV_ROUND_DOWN_ULL(((u64)rate_in) * config.f, + config.r * config.od); + if (calc_rate == k210_pll_get_rate(priv, id, rate)) + return calc_rate; + k210_pll_disable(priv, id); reg = readl(priv->base + pll->off); @@ -875,7 +876,7 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, | FIELD_PREP(K210_PLL_BWADJ, config.f - 1); writel(reg, priv->base + pll->off); - err = k210_pll_enable(priv, id); + k210_pll_enable(priv, id); serial_setbrg(); return k210_pll_get_rate(priv, id, rate); From c29efc157d3bd9cf4f021df9ea522383aa304ce6 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:13 -0400 Subject: [PATCH 093/250] clk: k210: Remove bypass driver This driver no longer serves a purpose now that we have moved away from CCF. Drop it. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/kendryte/Makefile | 2 +- drivers/clk/kendryte/bypass.c | 273 ---------------------------------- include/kendryte/bypass.h | 31 ---- 3 files changed, 1 insertion(+), 305 deletions(-) delete mode 100644 drivers/clk/kendryte/bypass.c delete mode 100644 include/kendryte/bypass.h diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile index 6710a1db723..0303c0b99cd 100644 --- a/drivers/clk/kendryte/Makefile +++ b/drivers/clk/kendryte/Makefile @@ -1 +1 @@ -obj-y += bypass.o clk.o +obj-y += clk.o diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c deleted file mode 100644 index bbdbd9a10de..00000000000 --- a/drivers/clk/kendryte/bypass.c +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Sean Anderson - */ - -#define LOG_CATEGORY UCLASS_CLK - -#include -#include -#include -#include -#include -#include -#include -#include - -#define CLK_K210_BYPASS "k210_clk_bypass" - -/* - * This is a small driver to do a software bypass of a clock if hardware bypass - * is not working. I have tried to write this in a generic fashion, so that it - * could be potentially broken out of the kendryte code at some future date. - * - * Say you have the following clock configuration - * - * +---+ +---+ - * |osc| |pll| - * +---+ +---+ - * ^ - * /| - * / | - * / | - * / | - * / | - * +---+ +---+ - * |clk| |clk| - * +---+ +---+ - * - * But the pll does not have a bypass, so when you configure the pll, the - * configuration needs to change to look like - * - * +---+ +---+ - * |osc| |pll| - * +---+ +---+ - * ^ - * |\ - * | \ - * | \ - * | \ - * | \ - * +---+ +---+ - * |clk| |clk| - * +---+ +---+ - * - * To set this up, create a bypass clock with bypassee=pll and alt=osc. When - * creating the child clocks, set their parent to the bypass clock. After - * creating all the children, call k210_bypass_setchildren(). - */ - -static int k210_bypass_dobypass(struct k210_bypass *bypass) -{ - int ret, i; - - /* - * If we already have saved parents, then the children are already - * bypassed - */ - if (bypass->child_count && bypass->saved_parents[0]) - return 0; - - for (i = 0; i < bypass->child_count; i++) { - struct clk *child = bypass->children[i]; - struct clk *parent = clk_get_parent(child); - - if (IS_ERR(parent)) { - for (; i; i--) - bypass->saved_parents[i] = NULL; - return PTR_ERR(parent); - } - bypass->saved_parents[i] = parent; - } - - for (i = 0; i < bypass->child_count; i++) { - struct clk *child = bypass->children[i]; - - ret = clk_set_parent(child, bypass->alt); - if (ret) { - for (; i; i--) - clk_set_parent(bypass->children[i], - bypass->saved_parents[i]); - for (i = 0; i < bypass->child_count; i++) - bypass->saved_parents[i] = NULL; - return ret; - } - } - - return 0; -} - -static int k210_bypass_unbypass(struct k210_bypass *bypass) -{ - int err, ret, i; - - if (!bypass->child_count && !bypass->saved_parents[0]) { - log_warning("Cannot unbypass children; dobypass not called first\n"); - return 0; - } - - ret = 0; - for (i = 0; i < bypass->child_count; i++) { - err = clk_set_parent(bypass->children[i], - bypass->saved_parents[i]); - if (err) - ret = err; - bypass->saved_parents[i] = NULL; - } - return ret; -} - -static ulong k210_bypass_get_rate(struct clk *clk) -{ - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - if (ops->get_rate) - return ops->get_rate(bypass->bypassee); - else - return clk_get_parent_rate(bypass->bypassee); -} - -static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate) -{ - int ret; - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - /* Don't bother bypassing if we aren't going to set the rate */ - if (!ops->set_rate) - return k210_bypass_get_rate(clk); - - ret = k210_bypass_dobypass(bypass); - if (ret) - return ret; - - ret = ops->set_rate(bypass->bypassee, rate); - if (ret < 0) - return ret; - - return k210_bypass_unbypass(bypass); -} - -static int k210_bypass_set_parent(struct clk *clk, struct clk *parent) -{ - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - if (ops->set_parent) - return ops->set_parent(bypass->bypassee, parent); - else - return -EINVAL; -} - -/* - * For these next two functions, do the bypassing even if there is no - * en-/-disable function, since the bypassing itself can be observed in between - * calls. - */ -static int k210_bypass_enable(struct clk *clk) -{ - int ret; - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - ret = k210_bypass_dobypass(bypass); - if (ret) - return ret; - - if (ops->enable) - ret = ops->enable(bypass->bypassee); - else - ret = 0; - if (ret) - return ret; - - return k210_bypass_unbypass(bypass); -} - -static int k210_bypass_disable(struct clk *clk) -{ - int ret; - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - ret = k210_bypass_dobypass(bypass); - if (ret) - return ret; - - if (ops->disable) - return ops->disable(bypass->bypassee); - else - return 0; -} - -static const struct clk_ops k210_bypass_ops = { - .get_rate = k210_bypass_get_rate, - .set_rate = k210_bypass_set_rate, - .set_parent = k210_bypass_set_parent, - .enable = k210_bypass_enable, - .disable = k210_bypass_disable, -}; - -int k210_bypass_set_children(struct clk *clk, struct clk **children, - size_t child_count) -{ - struct k210_bypass *bypass = to_k210_bypass(clk); - - kfree(bypass->saved_parents); - if (child_count) { - bypass->saved_parents = - kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL); - if (!bypass->saved_parents) - return -ENOMEM; - } - bypass->child_count = child_count; - bypass->children = children; - - return 0; -} - -struct clk *k210_register_bypass_struct(const char *name, - const char *parent_name, - struct k210_bypass *bypass) -{ - int ret; - struct clk *clk; - - clk = &bypass->clk; - - ret = clk_register(clk, CLK_K210_BYPASS, name, parent_name); - if (ret) - return ERR_PTR(ret); - - bypass->bypassee->dev = clk->dev; - return clk; -} - -struct clk *k210_register_bypass(const char *name, const char *parent_name, - struct clk *bypassee, - const struct clk_ops *bypassee_ops, - struct clk *alt) -{ - struct clk *clk; - struct k210_bypass *bypass; - - bypass = kzalloc(sizeof(*bypass), GFP_KERNEL); - if (!bypass) - return ERR_PTR(-ENOMEM); - - bypass->bypassee = bypassee; - bypass->bypassee_ops = bypassee_ops; - bypass->alt = alt; - - clk = k210_register_bypass_struct(name, parent_name, bypass); - if (IS_ERR(clk)) - kfree(bypass); - return clk; -} - -U_BOOT_DRIVER(k210_bypass) = { - .name = CLK_K210_BYPASS, - .id = UCLASS_CLK, - .ops = &k210_bypass_ops, -}; diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h deleted file mode 100644 index ab85bbcbfca..00000000000 --- a/include/kendryte/bypass.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 Sean Anderson - */ -#ifndef K210_BYPASS_H -#define K210_BYPASS_H - -struct clk; - -struct k210_bypass { - struct clk clk; - struct clk **children; /* Clocks to reparent */ - struct clk **saved_parents; /* Parents saved over en-/dis-able */ - struct clk *bypassee; /* Clock to bypass */ - const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */ - struct clk *alt; /* Clock to set children to when bypassing */ - size_t child_count; -}; - -#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk) - -int k210_bypass_set_children(struct clk *clk, struct clk **children, - size_t child_count); -struct clk *k210_register_bypass_struct(const char *name, - const char *parent_name, - struct k210_bypass *bypass); -struct clk *k210_register_bypass(const char *name, const char *parent_name, - struct clk *bypassee, - const struct clk_ops *bypassee_ops, - struct clk *alt); -#endif /* K210_BYPASS_H */ From 493110cc499539f42a2786e8306ba29ac0ba2435 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:14 -0400 Subject: [PATCH 094/250] clk: k210: Move k210 clock out of its own subdirectory Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- MAINTAINERS | 4 ++-- drivers/clk/Kconfig | 14 +++++++++++++- drivers/clk/Makefile | 2 +- drivers/clk/{kendryte/clk.c => clk_kendryte.c} | 0 drivers/clk/kendryte/Kconfig | 12 ------------ drivers/clk/kendryte/Makefile | 1 - 6 files changed, 16 insertions(+), 17 deletions(-) rename drivers/clk/{kendryte/clk.c => clk_kendryte.c} (100%) delete mode 100644 drivers/clk/kendryte/Kconfig delete mode 100644 drivers/clk/kendryte/Makefile diff --git a/MAINTAINERS b/MAINTAINERS index 86ff5e04a62..effcf5469d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -999,8 +999,8 @@ M: Sean Anderson S: Maintained F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt -F: drivers/clk/kendryte/ -F: drivers/pinctrl/kendryte/ +F: drivers/clk/clk_kendryte.c +F: drivers/pinctrl/pinctrl-kendryte.c F: include/kendryte/ RNG diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 40a5a5dd883..4bc66801215 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -159,11 +159,23 @@ config CLK_SCMI by a SCMI agent based on SCMI clock protocol communication with a SCMI server. +config CLK_K210 + bool "Clock support for Kendryte K210" + depends on CLK + help + This enables support clock driver for Kendryte K210 platforms. + +config CLK_K210_SET_RATE + bool "Enable setting the Kendryte K210 PLL rate" + depends on CLK_K210 + help + Add functionality to calculate new rates for K210 PLLs. Enabling this + feature adds around 1K to U-Boot's final size. + source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" -source "drivers/clk/kendryte/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 645709b855e..f06164bb49d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -28,7 +28,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o -obj-$(CONFIG_CLK_K210) += kendryte/ +obj-$(CONFIG_CLK_K210) += clk_kendryte.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_MPFS) += microchip/ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/clk_kendryte.c similarity index 100% rename from drivers/clk/kendryte/clk.c rename to drivers/clk/clk_kendryte.c diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig deleted file mode 100644 index 0dc8e3f889f..00000000000 --- a/drivers/clk/kendryte/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -config CLK_K210 - bool "Clock support for Kendryte K210" - depends on CLK - help - This enables support clock driver for Kendryte K210 platforms. - -config CLK_K210_SET_RATE - bool "Enable setting the Kendryte K210 PLL rate" - depends on CLK_K210 - help - Add functionality to calculate new rates for K210 PLLs. Enabling this - feature adds around 1K to U-Boot's final size. diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile deleted file mode 100644 index 0303c0b99cd..00000000000 --- a/drivers/clk/kendryte/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += clk.o From 9cd637f84bc3dc60e0201012494982479621b5bd Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:15 -0400 Subject: [PATCH 095/250] k210: dts: Set PLL1 to the same rate as PLL0 Linux has had some stability issues when using AISRAM with a different frequency from SRAM. Mirror their change here now that we relocate into AISRAM. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/k210.dtsi | 2 ++ configs/sipeed_maix_bitm_defconfig | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 2492af80389..8bcd3cebdef 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -501,6 +501,8 @@ #clock-cells = <1>; compatible = "kendryte,k210-clk"; clocks = <&in0>; + assigned-clocks = <&sysclk K210_CLK_PLL1>; + assigned-clock-rates = <390000000>; u-boot,dm-pre-reloc; }; diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index bd877cd0554..6a06f650ea2 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -13,6 +13,7 @@ CONFIG_HUSH_PARSER=y CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" # CONFIG_NET is not set +CONFIG_CLK_K210_SET_RATE=y # CONFIG_INPUT is not set CONFIG_SF_DEFAULT_BUS=3 # CONFIG_DM_ETH is not set From 55dac94ab8a3634056f44ce66b06af4c04011c9f Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:16 -0400 Subject: [PATCH 096/250] k210: Don't imply CCF Now that the k210 clock driver does not depend on CCF, we should no longer imply it (and probably should not have in the first place). We can also reduce the pre-relocation malloc arena back to something sensible. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- board/sipeed/maix/Kconfig | 2 -- configs/sipeed_maix_bitm_defconfig | 1 - 2 files changed, 3 deletions(-) diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index adf6abb5726..b1d7a7ad936 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -37,8 +37,6 @@ config BOARD_SPECIFIC_OPTIONS imply SIFIVE_CLINT imply POWER_DOMAIN imply SIMPLE_PM_BUS - imply CLK_CCF - imply CLK_COMPOSITE_CCF imply CLK_K210 imply DM_RESET imply RESET_SYSCON diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 6a06f650ea2..33c67c0b540 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,5 +1,4 @@ CONFIG_RISCV=y -CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 From 446b4f346e006e2f87cebc9665c0139c7e17c905 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 11 Jun 2021 00:16:17 -0400 Subject: [PATCH 097/250] test: Add K210 PLL tests to sandbox defconfigs This adds the unit test for the K210 PLL to the sandbox defconfigs. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- configs/sandbox64_defconfig | 2 ++ configs/sandbox_defconfig | 2 ++ configs/sandbox_flattree_defconfig | 2 ++ 3 files changed, 6 insertions(+) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 9a373bab6fe..9cd746107de 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -107,6 +107,8 @@ CONFIG_AXI_SANDBOX=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK=y +CONFIG_CLK_K210=y +CONFIG_CLK_K210_SET_RATE=y CONFIG_CPU=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 60cdad10848..0275ddaca18 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -131,6 +131,8 @@ CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_SCMI=y +CONFIG_CLK_K210=y +CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 853c9440ea0..772230ce47f 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -86,6 +86,8 @@ CONFIG_AXI=y CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_K210=y +CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y CONFIG_DM_DEMO=y From b40a034a637fef883de033fe40009afa0807fd3c Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 2 Jun 2021 19:08:23 +0200 Subject: [PATCH 098/250] arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SDMMC2 interface hosts an eMMC. Replace the interface properties that would only apply to SD cards—“broken-cd” and “disable-wp”—with relevant ones: “non-removable”, “no-sd” and “no-sdio”. Signed-off-by: Grzegorz Szymaszek Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi index e367a311c42..ed399c00d13 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -267,8 +267,9 @@ pinctrl-0 = <&sdmmc2_b4_pins_a>; pinctrl-1 = <&sdmmc2_b4_od_pins_a>; pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; - broken-cd; - disable-wp; + non-removable; + no-sd; + no-sdio; st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; From b1c8ad53f5df284b7ba989cb9e2cda52c15277c4 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 2 Jun 2021 19:09:03 +0200 Subject: [PATCH 099/250] arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the “sdmmc2_d47_pins_d” pins to the SDMMC2 pinctrls. Increase the bus width from four to eight. Signed-off-by: Grzegorz Szymaszek Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi index ed399c00d13..7323325e604 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -264,14 +264,14 @@ &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; non-removable; no-sd; no-sdio; st,neg-edge; - bus-width = <4>; + bus-width = <8>; vmmc-supply = <&v3v3>; status = "okay"; }; From 51a2ac966e2ce45ae3b6d43975977db84759ed91 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 2 Jun 2021 19:09:08 +0200 Subject: [PATCH 100/250] arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply Set the SDMMC2 VQMMC supply to vdd (buck3). Note that in the corresponding Linux kernel device tree, the supply is set to v3v3 (buck4), which is wrong. Signed-off-by: Grzegorz Szymaszek Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi index 7323325e604..583812f1375 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -273,6 +273,7 @@ st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; status = "okay"; }; From 7db3307848f2d4734861fda45320345e688ccdac Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 2 Jun 2021 19:09:13 +0200 Subject: [PATCH 101/250] arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the corresponding Linux kernel device tree. Signed-off-by: Grzegorz Szymaszek Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi index 583812f1375..1510a5b3644 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -274,6 +274,7 @@ bus-width = <8>; vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; status = "okay"; }; From 95a34eb42ec1319afaf5e27012744570588e034b Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 2 Jun 2021 19:09:18 +0200 Subject: [PATCH 102/250] arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL Enable the SDMMC2 device tree node, as well as the pins it uses, in U-Boot SPL. Signed-off-by: Grzegorz Szymaszek Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- .../dts/stm32mp157c-odyssey-som-u-boot.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index 6be728846e2..4ff848350de 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -123,3 +123,24 @@ u-boot,dm-pre-reloc; }; }; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_d { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; From 19ec205de0678e75c7f11e31afe9e6d76468b7e1 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 26 May 2021 17:01:16 +0800 Subject: [PATCH 103/250] rockchip: rk3568: add device tree file Add dts binding header for rk3568, files origin from kernel. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3568-cru.h | 925 +++++++++++++++++++++++++ 1 file changed, 925 insertions(+) create mode 100644 include/dt-bindings/clock/rk3568-cru.h diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h new file mode 100644 index 00000000000..c1942422a43 --- /dev/null +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -0,0 +1,925 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H + +/* pmucru-clocks indices */ + +/* pmucru plls */ +#define PLL_PPLL 1 +#define PLL_HPLL 2 + +/* pmucru clocks */ +#define XIN_OSC0_DIV 4 +#define CLK_RTC_32K 5 +#define CLK_PMU 6 +#define CLK_I2C0 7 +#define CLK_RTC32K_FRAC 8 +#define CLK_UART0_DIV 9 +#define CLK_UART0_FRAC 10 +#define SCLK_UART0 11 +#define DBCLK_GPIO0 12 +#define CLK_PWM0 13 +#define CLK_CAPTURE_PWM0_NDFT 14 +#define CLK_PMUPVTM 15 +#define CLK_CORE_PMUPVTM 16 +#define CLK_REF24M 17 +#define XIN_OSC0_USBPHY0_G 18 +#define CLK_USBPHY0_REF 19 +#define XIN_OSC0_USBPHY1_G 20 +#define CLK_USBPHY1_REF 21 +#define XIN_OSC0_MIPIDSIPHY0_G 22 +#define CLK_MIPIDSIPHY0_REF 23 +#define XIN_OSC0_MIPIDSIPHY1_G 24 +#define CLK_MIPIDSIPHY1_REF 25 +#define CLK_WIFI_DIV 26 +#define CLK_WIFI_OSC0 27 +#define CLK_WIFI 28 +#define CLK_PCIEPHY0_DIV 29 +#define CLK_PCIEPHY0_OSC0 30 +#define CLK_PCIEPHY0_REF 31 +#define CLK_PCIEPHY1_DIV 32 +#define CLK_PCIEPHY1_OSC0 33 +#define CLK_PCIEPHY1_REF 34 +#define CLK_PCIEPHY2_DIV 35 +#define CLK_PCIEPHY2_OSC0 36 +#define CLK_PCIEPHY2_REF 37 +#define CLK_PCIE30PHY_REF_M 38 +#define CLK_PCIE30PHY_REF_N 39 +#define CLK_HDMI_REF 40 +#define XIN_OSC0_EDPPHY_G 41 +#define PCLK_PDPMU 42 +#define PCLK_PMU 43 +#define PCLK_UART0 44 +#define PCLK_I2C0 45 +#define PCLK_GPIO0 46 +#define PCLK_PMUPVTM 47 +#define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 + +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_VPLL 5 +#define PLL_NPLL 6 + +/* cru clocks */ +#define CPLL_333M 9 +#define ARMCLK 10 +#define USB480M 11 +#define ACLK_CORE_NIU2BUS 18 +#define CLK_CORE_PVTM 19 +#define CLK_CORE_PVTM_CORE 20 +#define CLK_CORE_PVTPLL 21 +#define CLK_GPU_SRC 22 +#define CLK_GPU_PRE_NDFT 23 +#define CLK_GPU_PRE_MUX 24 +#define ACLK_GPU_PRE 25 +#define PCLK_GPU_PRE 26 +#define CLK_GPU 27 +#define CLK_GPU_NP5 28 +#define PCLK_GPU_PVTM 29 +#define CLK_GPU_PVTM 30 +#define CLK_GPU_PVTM_CORE 31 +#define CLK_GPU_PVTPLL 32 +#define CLK_NPU_SRC 33 +#define CLK_NPU_PRE_NDFT 34 +#define CLK_NPU 35 +#define CLK_NPU_NP5 36 +#define HCLK_NPU_PRE 37 +#define PCLK_NPU_PRE 38 +#define ACLK_NPU_PRE 39 +#define ACLK_NPU 40 +#define HCLK_NPU 41 +#define PCLK_NPU_PVTM 42 +#define CLK_NPU_PVTM 43 +#define CLK_NPU_PVTM_CORE 44 +#define CLK_NPU_PVTPLL 45 +#define CLK_DDRPHY1X_SRC 46 +#define CLK_DDRPHY1X_HWFFC_SRC 47 +#define CLK_DDR1X 48 +#define CLK_MSCH 49 +#define CLK24_DDRMON 50 +#define ACLK_GIC_AUDIO 51 +#define HCLK_GIC_AUDIO 52 +#define HCLK_SDMMC_BUFFER 53 +#define DCLK_SDMMC_BUFFER 54 +#define ACLK_GIC600 55 +#define ACLK_SPINLOCK 56 +#define HCLK_I2S0_8CH 57 +#define HCLK_I2S1_8CH 58 +#define HCLK_I2S2_2CH 59 +#define HCLK_I2S3_2CH 60 +#define CLK_I2S0_8CH_TX_SRC 61 +#define CLK_I2S0_8CH_TX_FRAC 62 +#define MCLK_I2S0_8CH_TX 63 +#define I2S0_MCLKOUT_TX 64 +#define CLK_I2S0_8CH_RX_SRC 65 +#define CLK_I2S0_8CH_RX_FRAC 66 +#define MCLK_I2S0_8CH_RX 67 +#define I2S0_MCLKOUT_RX 68 +#define CLK_I2S1_8CH_TX_SRC 69 +#define CLK_I2S1_8CH_TX_FRAC 70 +#define MCLK_I2S1_8CH_TX 71 +#define I2S1_MCLKOUT_TX 72 +#define CLK_I2S1_8CH_RX_SRC 73 +#define CLK_I2S1_8CH_RX_FRAC 74 +#define MCLK_I2S1_8CH_RX 75 +#define I2S1_MCLKOUT_RX 76 +#define CLK_I2S2_2CH_SRC 77 +#define CLK_I2S2_2CH_FRAC 78 +#define MCLK_I2S2_2CH 79 +#define I2S2_MCLKOUT 80 +#define CLK_I2S3_2CH_TX_SRC 81 +#define CLK_I2S3_2CH_TX_FRAC 82 +#define MCLK_I2S3_2CH_TX 83 +#define I2S3_MCLKOUT_TX 84 +#define CLK_I2S3_2CH_RX_SRC 85 +#define CLK_I2S3_2CH_RX_FRAC 86 +#define MCLK_I2S3_2CH_RX 87 +#define I2S3_MCLKOUT_RX 88 +#define HCLK_PDM 89 +#define MCLK_PDM 90 +#define HCLK_VAD 91 +#define HCLK_SPDIF_8CH 92 +#define MCLK_SPDIF_8CH_SRC 93 +#define MCLK_SPDIF_8CH_FRAC 94 +#define MCLK_SPDIF_8CH 95 +#define HCLK_AUDPWM 96 +#define SCLK_AUDPWM_SRC 97 +#define SCLK_AUDPWM_FRAC 98 +#define SCLK_AUDPWM 99 +#define HCLK_ACDCDIG 100 +#define CLK_ACDCDIG_I2C 101 +#define CLK_ACDCDIG_DAC 102 +#define CLK_ACDCDIG_ADC 103 +#define ACLK_SECURE_FLASH 104 +#define HCLK_SECURE_FLASH 105 +#define ACLK_CRYPTO_NS 106 +#define HCLK_CRYPTO_NS 107 +#define CLK_CRYPTO_NS_CORE 108 +#define CLK_CRYPTO_NS_PKA 109 +#define CLK_CRYPTO_NS_RNG 110 +#define HCLK_TRNG_NS 111 +#define CLK_TRNG_NS 112 +#define PCLK_OTPC_NS 113 +#define CLK_OTPC_NS_SBPI 114 +#define CLK_OTPC_NS_USR 115 +#define HCLK_NANDC 116 +#define NCLK_NANDC 117 +#define HCLK_SFC 118 +#define HCLK_SFC_XIP 119 +#define SCLK_SFC 120 +#define ACLK_EMMC 121 +#define HCLK_EMMC 122 +#define BCLK_EMMC 123 +#define CCLK_EMMC 124 +#define TCLK_EMMC 125 +#define ACLK_PIPE 126 +#define PCLK_PIPE 127 +#define PCLK_PIPE_GRF 128 +#define ACLK_PCIE20_MST 129 +#define ACLK_PCIE20_SLV 130 +#define ACLK_PCIE20_DBI 131 +#define PCLK_PCIE20 132 +#define CLK_PCIE20_AUX_NDFT 133 +#define CLK_PCIE20_AUX_DFT 134 +#define CLK_PCIE20_PIPE_DFT 135 +#define ACLK_PCIE30X1_MST 136 +#define ACLK_PCIE30X1_SLV 137 +#define ACLK_PCIE30X1_DBI 138 +#define PCLK_PCIE30X1 139 +#define CLK_PCIE30X1_AUX_NDFT 140 +#define CLK_PCIE30X1_AUX_DFT 141 +#define CLK_PCIE30X1_PIPE_DFT 142 +#define ACLK_PCIE30X2_MST 143 +#define ACLK_PCIE30X2_SLV 144 +#define ACLK_PCIE30X2_DBI 145 +#define PCLK_PCIE30X2 146 +#define CLK_PCIE30X2_AUX_NDFT 147 +#define CLK_PCIE30X2_AUX_DFT 148 +#define CLK_PCIE30X2_PIPE_DFT 149 +#define ACLK_SATA0 150 +#define CLK_SATA0_PMALIVE 151 +#define CLK_SATA0_RXOOB 152 +#define CLK_SATA0_PIPE_NDFT 153 +#define CLK_SATA0_PIPE_DFT 154 +#define ACLK_SATA1 155 +#define CLK_SATA1_PMALIVE 156 +#define CLK_SATA1_RXOOB 157 +#define CLK_SATA1_PIPE_NDFT 158 +#define CLK_SATA1_PIPE_DFT 159 +#define ACLK_SATA2 160 +#define CLK_SATA2_PMALIVE 161 +#define CLK_SATA2_RXOOB 162 +#define CLK_SATA2_PIPE_NDFT 163 +#define CLK_SATA2_PIPE_DFT 164 +#define ACLK_USB3OTG0 165 +#define CLK_USB3OTG0_REF 166 +#define CLK_USB3OTG0_SUSPEND 167 +#define ACLK_USB3OTG1 168 +#define CLK_USB3OTG1_REF 169 +#define CLK_USB3OTG1_SUSPEND 170 +#define CLK_XPCS_EEE 171 +#define PCLK_XPCS 172 +#define ACLK_PHP 173 +#define HCLK_PHP 174 +#define PCLK_PHP 175 +#define HCLK_SDMMC0 176 +#define CLK_SDMMC0 177 +#define HCLK_SDMMC1 178 +#define CLK_SDMMC1 179 +#define ACLK_GMAC0 180 +#define PCLK_GMAC0 181 +#define CLK_MAC0_2TOP 182 +#define CLK_MAC0_OUT 183 +#define CLK_MAC0_REFOUT 184 +#define CLK_GMAC0_PTP_REF 185 +#define ACLK_USB 186 +#define HCLK_USB 187 +#define PCLK_USB 188 +#define HCLK_USB2HOST0 189 +#define HCLK_USB2HOST0_ARB 190 +#define HCLK_USB2HOST1 191 +#define HCLK_USB2HOST1_ARB 192 +#define HCLK_SDMMC2 193 +#define CLK_SDMMC2 194 +#define ACLK_GMAC1 195 +#define PCLK_GMAC1 196 +#define CLK_MAC1_2TOP 197 +#define CLK_MAC1_OUT 198 +#define CLK_MAC1_REFOUT 199 +#define CLK_GMAC1_PTP_REF 200 +#define ACLK_PERIMID 201 +#define HCLK_PERIMID 202 +#define ACLK_VI 203 +#define HCLK_VI 204 +#define PCLK_VI 205 +#define ACLK_VICAP 206 +#define HCLK_VICAP 207 +#define DCLK_VICAP 208 +#define ICLK_VICAP_G 209 +#define ACLK_ISP 210 +#define HCLK_ISP 211 +#define CLK_ISP 212 +#define PCLK_CSI2HOST1 213 +#define CLK_CIF_OUT 214 +#define CLK_CAM0_OUT 215 +#define CLK_CAM1_OUT 216 +#define ACLK_VO 217 +#define HCLK_VO 218 +#define PCLK_VO 219 +#define ACLK_VOP_PRE 220 +#define ACLK_VOP 221 +#define HCLK_VOP 222 +#define DCLK_VOP0 223 +#define DCLK_VOP1 224 +#define DCLK_VOP2 225 +#define CLK_VOP_PWM 226 +#define ACLK_HDCP 227 +#define HCLK_HDCP 228 +#define PCLK_HDCP 229 +#define PCLK_HDMI_HOST 230 +#define CLK_HDMI_SFR 231 +#define PCLK_DSITX_0 232 +#define PCLK_DSITX_1 233 +#define PCLK_EDP_CTRL 234 +#define CLK_EDP_200M 235 +#define ACLK_VPU_PRE 236 +#define HCLK_VPU_PRE 237 +#define ACLK_VPU 238 +#define HCLK_VPU 239 +#define ACLK_RGA_PRE 240 +#define HCLK_RGA_PRE 241 +#define PCLK_RGA_PRE 242 +#define ACLK_RGA 243 +#define HCLK_RGA 244 +#define CLK_RGA_CORE 245 +#define ACLK_IEP 246 +#define HCLK_IEP 247 +#define CLK_IEP_CORE 248 +#define HCLK_EBC 249 +#define DCLK_EBC 250 +#define ACLK_JDEC 251 +#define HCLK_JDEC 252 +#define ACLK_JENC 253 +#define HCLK_JENC 254 +#define PCLK_EINK 255 +#define HCLK_EINK 256 +#define ACLK_RKVENC_PRE 257 +#define HCLK_RKVENC_PRE 258 +#define ACLK_RKVENC 259 +#define HCLK_RKVENC 260 +#define CLK_RKVENC_CORE 261 +#define ACLK_RKVDEC_PRE 262 +#define HCLK_RKVDEC_PRE 263 +#define ACLK_RKVDEC 264 +#define HCLK_RKVDEC 265 +#define CLK_RKVDEC_CA 266 +#define CLK_RKVDEC_CORE 267 +#define CLK_RKVDEC_HEVC_CA 268 +#define ACLK_BUS 269 +#define PCLK_BUS 270 +#define PCLK_TSADC 271 +#define CLK_TSADC_TSEN 272 +#define CLK_TSADC 273 +#define PCLK_SARADC 274 +#define CLK_SARADC 275 +#define PCLK_SCR 276 +#define PCLK_WDT_NS 277 +#define TCLK_WDT_NS 278 +#define ACLK_DMAC0 279 +#define ACLK_DMAC1 280 +#define ACLK_MCU 281 +#define PCLK_INTMUX 282 +#define PCLK_MAILBOX 283 +#define PCLK_UART1 284 +#define CLK_UART1_SRC 285 +#define CLK_UART1_FRAC 286 +#define SCLK_UART1 287 +#define PCLK_UART2 288 +#define CLK_UART2_SRC 289 +#define CLK_UART2_FRAC 290 +#define SCLK_UART2 291 +#define PCLK_UART3 292 +#define CLK_UART3_SRC 293 +#define CLK_UART3_FRAC 294 +#define SCLK_UART3 295 +#define PCLK_UART4 296 +#define CLK_UART4_SRC 297 +#define CLK_UART4_FRAC 298 +#define SCLK_UART4 299 +#define PCLK_UART5 300 +#define CLK_UART5_SRC 301 +#define CLK_UART5_FRAC 302 +#define SCLK_UART5 303 +#define PCLK_UART6 304 +#define CLK_UART6_SRC 305 +#define CLK_UART6_FRAC 306 +#define SCLK_UART6 307 +#define PCLK_UART7 308 +#define CLK_UART7_SRC 309 +#define CLK_UART7_FRAC 310 +#define SCLK_UART7 311 +#define PCLK_UART8 312 +#define CLK_UART8_SRC 313 +#define CLK_UART8_FRAC 314 +#define SCLK_UART8 315 +#define PCLK_UART9 316 +#define CLK_UART9_SRC 317 +#define CLK_UART9_FRAC 318 +#define SCLK_UART9 319 +#define PCLK_CAN0 320 +#define CLK_CAN0 321 +#define PCLK_CAN1 322 +#define CLK_CAN1 323 +#define PCLK_CAN2 324 +#define CLK_CAN2 325 +#define CLK_I2C 326 +#define PCLK_I2C1 327 +#define CLK_I2C1 328 +#define PCLK_I2C2 329 +#define CLK_I2C2 330 +#define PCLK_I2C3 331 +#define CLK_I2C3 332 +#define PCLK_I2C4 333 +#define CLK_I2C4 334 +#define PCLK_I2C5 335 +#define CLK_I2C5 336 +#define PCLK_SPI0 337 +#define CLK_SPI0 338 +#define PCLK_SPI1 339 +#define CLK_SPI1 340 +#define PCLK_SPI2 341 +#define CLK_SPI2 342 +#define PCLK_SPI3 343 +#define CLK_SPI3 344 +#define PCLK_PWM1 345 +#define CLK_PWM1 346 +#define CLK_PWM1_CAPTURE 347 +#define PCLK_PWM2 348 +#define CLK_PWM2 349 +#define CLK_PWM2_CAPTURE 350 +#define PCLK_PWM3 351 +#define CLK_PWM3 352 +#define CLK_PWM3_CAPTURE 353 +#define DBCLK_GPIO 354 +#define PCLK_GPIO1 355 +#define DBCLK_GPIO1 356 +#define PCLK_GPIO2 357 +#define DBCLK_GPIO2 358 +#define PCLK_GPIO3 359 +#define DBCLK_GPIO3 360 +#define PCLK_GPIO4 361 +#define DBCLK_GPIO4 362 +#define OCC_SCAN_CLK_GPIO 363 +#define PCLK_TIMER 364 +#define CLK_TIMER0 365 +#define CLK_TIMER1 366 +#define CLK_TIMER2 367 +#define CLK_TIMER3 368 +#define CLK_TIMER4 369 +#define CLK_TIMER5 370 +#define ACLK_TOP_HIGH 371 +#define ACLK_TOP_LOW 372 +#define HCLK_TOP 373 +#define PCLK_TOP 374 +#define PCLK_PCIE30PHY 375 +#define CLK_OPTC_ARB 376 +#define PCLK_MIPICSIPHY 377 +#define PCLK_MIPIDSIPHY0 378 +#define PCLK_MIPIDSIPHY1 379 +#define PCLK_PIPEPHY0 380 +#define PCLK_PIPEPHY1 381 +#define PCLK_PIPEPHY2 382 +#define PCLK_CPU_BOOST 383 +#define CLK_CPU_BOOST 384 +#define PCLK_OTPPHY 385 +#define SCLK_GMAC0 386 +#define SCLK_GMAC0_RGMII_SPEED 387 +#define SCLK_GMAC0_RMII_SPEED 388 +#define SCLK_GMAC0_RX_TX 389 +#define SCLK_GMAC1 390 +#define SCLK_GMAC1_RGMII_SPEED 391 +#define SCLK_GMAC1_RMII_SPEED 392 +#define SCLK_GMAC1_RX_TX 393 +#define SCLK_SDMMC0_DRV 394 +#define SCLK_SDMMC0_SAMPLE 395 +#define SCLK_SDMMC1_DRV 396 +#define SCLK_SDMMC1_SAMPLE 397 +#define SCLK_SDMMC2_DRV 398 +#define SCLK_SDMMC2_SAMPLE 399 +#define SCLK_EMMC_DRV 400 +#define SCLK_EMMC_SAMPLE 401 +#define PCLK_EDPPHY_GRF 402 +#define CLK_HDMI_CEC 403 +#define CLK_I2S0_8CH_TX 404 +#define CLK_I2S0_8CH_RX 405 +#define CLK_I2S1_8CH_TX 406 +#define CLK_I2S1_8CH_RX 407 +#define CLK_I2S2_2CH 408 +#define CLK_I2S3_2CH_TX 409 +#define CLK_I2S3_2CH_RX 410 +#define CPLL_500M 411 +#define CPLL_250M 412 +#define CPLL_125M 413 +#define CPLL_62P5M 414 +#define CPLL_50M 415 +#define CPLL_25M 416 +#define CPLL_100M 417 + +#define PCLK_CORE_PVTM 450 + +#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) + +/* pmu soft-reset indices */ +/* pmucru_softrst_con0 */ +#define SRST_P_PDPMU_NIU 0 +#define SRST_P_PMUCRU 1 +#define SRST_P_PMUGRF 2 +#define SRST_P_I2C0 3 +#define SRST_I2C0 4 +#define SRST_P_UART0 5 +#define SRST_S_UART0 6 +#define SRST_P_PWM0 7 +#define SRST_PWM0 8 +#define SRST_P_GPIO0 9 +#define SRST_GPIO0 10 +#define SRST_P_PMUPVTM 11 +#define SRST_PMUPVTM 12 + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_NCORERESET0 0 +#define SRST_NCORERESET1 1 +#define SRST_NCORERESET2 2 +#define SRST_NCORERESET3 3 +#define SRST_NCPUPORESET0 4 +#define SRST_NCPUPORESET1 5 +#define SRST_NCPUPORESET2 6 +#define SRST_NCPUPORESET3 7 +#define SRST_NSRESET 8 +#define SRST_NSPORESET 9 +#define SRST_NATRESET 10 +#define SRST_NGICRESET 11 +#define SRST_NPRESET 12 +#define SRST_NPERIPHRESET 13 + +/* cru_softrst_con1 */ +#define SRST_A_CORE_NIU2DDR 16 +#define SRST_A_CORE_NIU2BUS 17 +#define SRST_P_DBG_NIU 18 +#define SRST_P_DBG 19 +#define SRST_P_DBG_DAPLITE 20 +#define SRST_DAP 21 +#define SRST_A_ADB400_CORE2GIC 22 +#define SRST_A_ADB400_GIC2CORE 23 +#define SRST_P_CORE_GRF 24 +#define SRST_P_CORE_PVTM 25 +#define SRST_CORE_PVTM 26 +#define SRST_CORE_PVTPLL 27 + +/* cru_softrst_con2 */ +#define SRST_GPU 32 +#define SRST_A_GPU_NIU 33 +#define SRST_P_GPU_NIU 34 +#define SRST_P_GPU_PVTM 35 +#define SRST_GPU_PVTM 36 +#define SRST_GPU_PVTPLL 37 +#define SRST_A_NPU_NIU 40 +#define SRST_H_NPU_NIU 41 +#define SRST_P_NPU_NIU 42 +#define SRST_A_NPU 43 +#define SRST_H_NPU 44 +#define SRST_P_NPU_PVTM 45 +#define SRST_NPU_PVTM 46 +#define SRST_NPU_PVTPLL 47 + +/* cru_softrst_con3 */ +#define SRST_A_MSCH 51 +#define SRST_HWFFC_CTRL 52 +#define SRST_DDR_ALWAYSON 53 +#define SRST_A_DDRSPLIT 54 +#define SRST_DDRDFI_CTL 55 +#define SRST_A_DMA2DDR 57 + +/* cru_softrst_con4 */ +#define SRST_A_PERIMID_NIU 64 +#define SRST_H_PERIMID_NIU 65 +#define SRST_A_GIC_AUDIO_NIU 66 +#define SRST_H_GIC_AUDIO_NIU 67 +#define SRST_A_GIC600 68 +#define SRST_A_GIC600_DEBUG 69 +#define SRST_A_GICADB_CORE2GIC 70 +#define SRST_A_GICADB_GIC2CORE 71 +#define SRST_A_SPINLOCK 72 +#define SRST_H_SDMMC_BUFFER 73 +#define SRST_D_SDMMC_BUFFER 74 +#define SRST_H_I2S0_8CH 75 +#define SRST_H_I2S1_8CH 76 +#define SRST_H_I2S2_2CH 77 +#define SRST_H_I2S3_2CH 78 + +/* cru_softrst_con5 */ +#define SRST_M_I2S0_8CH_TX 80 +#define SRST_M_I2S0_8CH_RX 81 +#define SRST_M_I2S1_8CH_TX 82 +#define SRST_M_I2S1_8CH_RX 83 +#define SRST_M_I2S2_2CH 84 +#define SRST_M_I2S3_2CH_TX 85 +#define SRST_M_I2S3_2CH_RX 86 +#define SRST_H_PDM 87 +#define SRST_M_PDM 88 +#define SRST_H_VAD 89 +#define SRST_H_SPDIF_8CH 90 +#define SRST_M_SPDIF_8CH 91 +#define SRST_H_AUDPWM 92 +#define SRST_S_AUDPWM 93 +#define SRST_H_ACDCDIG 94 +#define SRST_ACDCDIG 95 + +/* cru_softrst_con6 */ +#define SRST_A_SECURE_FLASH_NIU 96 +#define SRST_H_SECURE_FLASH_NIU 97 +#define SRST_A_CRYPTO_NS 103 +#define SRST_H_CRYPTO_NS 104 +#define SRST_CRYPTO_NS_CORE 105 +#define SRST_CRYPTO_NS_PKA 106 +#define SRST_CRYPTO_NS_RNG 107 +#define SRST_H_TRNG_NS 108 +#define SRST_TRNG_NS 109 + +/* cru_softrst_con7 */ +#define SRST_H_NANDC 112 +#define SRST_N_NANDC 113 +#define SRST_H_SFC 114 +#define SRST_H_SFC_XIP 115 +#define SRST_S_SFC 116 +#define SRST_A_EMMC 117 +#define SRST_H_EMMC 118 +#define SRST_B_EMMC 119 +#define SRST_C_EMMC 120 +#define SRST_T_EMMC 121 + +/* cru_softrst_con8 */ +#define SRST_A_PIPE_NIU 128 +#define SRST_P_PIPE_NIU 130 +#define SRST_P_PIPE_GRF 133 +#define SRST_A_SATA0 134 +#define SRST_SATA0_PIPE 135 +#define SRST_SATA0_PMALIVE 136 +#define SRST_SATA0_RXOOB 137 +#define SRST_A_SATA1 138 +#define SRST_SATA1_PIPE 139 +#define SRST_SATA1_PMALIVE 140 +#define SRST_SATA1_RXOOB 141 + +/* cru_softrst_con9 */ +#define SRST_A_SATA2 144 +#define SRST_SATA2_PIPE 145 +#define SRST_SATA2_PMALIVE 146 +#define SRST_SATA2_RXOOB 147 +#define SRST_USB3OTG0 148 +#define SRST_USB3OTG1 149 +#define SRST_XPCS 150 +#define SRST_XPCS_TX_DIV10 151 +#define SRST_XPCS_RX_DIV10 152 +#define SRST_XPCS_XGXS_RX 153 + +/* cru_softrst_con10 */ +#define SRST_P_PCIE20 160 +#define SRST_PCIE20_POWERUP 161 +#define SRST_MSTR_ARESET_PCIE20 162 +#define SRST_SLV_ARESET_PCIE20 163 +#define SRST_DBI_ARESET_PCIE20 164 +#define SRST_BRESET_PCIE20 165 +#define SRST_PERST_PCIE20 166 +#define SRST_CORE_RST_PCIE20 167 +#define SRST_NSTICKY_RST_PCIE20 168 +#define SRST_STICKY_RST_PCIE20 169 +#define SRST_PWR_RST_PCIE20 170 + +/* cru_softrst_con11 */ +#define SRST_P_PCIE30X1 176 +#define SRST_PCIE30X1_POWERUP 177 +#define SRST_M_ARESET_PCIE30X1 178 +#define SRST_S_ARESET_PCIE30X1 179 +#define SRST_D_ARESET_PCIE30X1 180 +#define SRST_BRESET_PCIE30X1 181 +#define SRST_PERST_PCIE30X1 182 +#define SRST_CORE_RST_PCIE30X1 183 +#define SRST_NSTC_RST_PCIE30X1 184 +#define SRST_STC_RST_PCIE30X1 185 +#define SRST_PWR_RST_PCIE30X1 186 + +/* cru_softrst_con12 */ +#define SRST_P_PCIE30X2 192 +#define SRST_PCIE30X2_POWERUP 193 +#define SRST_M_ARESET_PCIE30X2 194 +#define SRST_S_ARESET_PCIE30X2 195 +#define SRST_D_ARESET_PCIE30X2 196 +#define SRST_BRESET_PCIE30X2 197 +#define SRST_PERST_PCIE30X2 198 +#define SRST_CORE_RST_PCIE30X2 199 +#define SRST_NSTC_RST_PCIE30X2 200 +#define SRST_STC_RST_PCIE30X2 201 +#define SRST_PWR_RST_PCIE30X2 202 + +/* cru_softrst_con13 */ +#define SRST_A_PHP_NIU 208 +#define SRST_H_PHP_NIU 209 +#define SRST_P_PHP_NIU 210 +#define SRST_H_SDMMC0 211 +#define SRST_SDMMC0 212 +#define SRST_H_SDMMC1 213 +#define SRST_SDMMC1 214 +#define SRST_A_GMAC0 215 +#define SRST_GMAC0_TIMESTAMP 216 + +/* cru_softrst_con14 */ +#define SRST_A_USB_NIU 224 +#define SRST_H_USB_NIU 225 +#define SRST_P_USB_NIU 226 +#define SRST_P_USB_GRF 227 +#define SRST_H_USB2HOST0 228 +#define SRST_H_USB2HOST0_ARB 229 +#define SRST_USB2HOST0_UTMI 230 +#define SRST_H_USB2HOST1 231 +#define SRST_H_USB2HOST1_ARB 232 +#define SRST_USB2HOST1_UTMI 233 +#define SRST_H_SDMMC2 234 +#define SRST_SDMMC2 235 +#define SRST_A_GMAC1 236 +#define SRST_GMAC1_TIMESTAMP 237 + +/* cru_softrst_con15 */ +#define SRST_A_VI_NIU 240 +#define SRST_H_VI_NIU 241 +#define SRST_P_VI_NIU 242 +#define SRST_A_VICAP 247 +#define SRST_H_VICAP 248 +#define SRST_D_VICAP 249 +#define SRST_I_VICAP 250 +#define SRST_P_VICAP 251 +#define SRST_H_ISP 252 +#define SRST_ISP 253 +#define SRST_P_CSI2HOST1 255 + +/* cru_softrst_con16 */ +#define SRST_A_VO_NIU 256 +#define SRST_H_VO_NIU 257 +#define SRST_P_VO_NIU 258 +#define SRST_A_VOP_NIU 259 +#define SRST_A_VOP 260 +#define SRST_H_VOP 261 +#define SRST_VOP0 262 +#define SRST_VOP1 263 +#define SRST_VOP2 264 +#define SRST_VOP_PWM 265 +#define SRST_A_HDCP 266 +#define SRST_H_HDCP 267 +#define SRST_P_HDCP 268 +#define SRST_P_HDMI_HOST 270 +#define SRST_HDMI_HOST 271 + +/* cru_softrst_con17 */ +#define SRST_P_DSITX_0 272 +#define SRST_P_DSITX_1 273 +#define SRST_P_EDP_CTRL 274 +#define SRST_EDP_24M 275 +#define SRST_A_VPU_NIU 280 +#define SRST_H_VPU_NIU 281 +#define SRST_A_VPU 282 +#define SRST_H_VPU 283 +#define SRST_H_EINK 286 +#define SRST_P_EINK 287 + +/* cru_softrst_con18 */ +#define SRST_A_RGA_NIU 288 +#define SRST_H_RGA_NIU 289 +#define SRST_P_RGA_NIU 290 +#define SRST_A_RGA 292 +#define SRST_H_RGA 293 +#define SRST_RGA_CORE 294 +#define SRST_A_IEP 295 +#define SRST_H_IEP 296 +#define SRST_IEP_CORE 297 +#define SRST_H_EBC 298 +#define SRST_D_EBC 299 +#define SRST_A_JDEC 300 +#define SRST_H_JDEC 301 +#define SRST_A_JENC 302 +#define SRST_H_JENC 303 + +/* cru_softrst_con19 */ +#define SRST_A_VENC_NIU 304 +#define SRST_H_VENC_NIU 305 +#define SRST_A_RKVENC 307 +#define SRST_H_RKVENC 308 +#define SRST_RKVENC_CORE 309 + +/* cru_softrst_con20 */ +#define SRST_A_RKVDEC_NIU 320 +#define SRST_H_RKVDEC_NIU 321 +#define SRST_A_RKVDEC 322 +#define SRST_H_RKVDEC 323 +#define SRST_RKVDEC_CA 324 +#define SRST_RKVDEC_CORE 325 +#define SRST_RKVDEC_HEVC_CA 326 + +/* cru_softrst_con21 */ +#define SRST_A_BUS_NIU 336 +#define SRST_P_BUS_NIU 338 +#define SRST_P_CAN0 340 +#define SRST_CAN0 341 +#define SRST_P_CAN1 342 +#define SRST_CAN1 343 +#define SRST_P_CAN2 344 +#define SRST_CAN2 345 +#define SRST_P_GPIO1 346 +#define SRST_GPIO1 347 +#define SRST_P_GPIO2 348 +#define SRST_GPIO2 349 +#define SRST_P_GPIO3 350 +#define SRST_GPIO3 351 + +/* cru_softrst_con22 */ +#define SRST_P_GPIO4 352 +#define SRST_GPIO4 353 +#define SRST_P_I2C1 354 +#define SRST_I2C1 355 +#define SRST_P_I2C2 356 +#define SRST_I2C2 357 +#define SRST_P_I2C3 358 +#define SRST_I2C3 359 +#define SRST_P_I2C4 360 +#define SRST_I2C4 361 +#define SRST_P_I2C5 362 +#define SRST_I2C5 363 +#define SRST_P_OTPC_NS 364 +#define SRST_OTPC_NS_SBPI 365 +#define SRST_OTPC_NS_USR 366 + +/* cru_softrst_con23 */ +#define SRST_P_PWM1 368 +#define SRST_PWM1 369 +#define SRST_P_PWM2 370 +#define SRST_PWM2 371 +#define SRST_P_PWM3 372 +#define SRST_PWM3 373 +#define SRST_P_SPI0 374 +#define SRST_SPI0 375 +#define SRST_P_SPI1 376 +#define SRST_SPI1 377 +#define SRST_P_SPI2 378 +#define SRST_SPI2 379 +#define SRST_P_SPI3 380 +#define SRST_SPI3 381 + +/* cru_softrst_con24 */ +#define SRST_P_SARADC 384 +#define SRST_P_TSADC 385 +#define SRST_TSADC 386 +#define SRST_P_TIMER 387 +#define SRST_TIMER0 388 +#define SRST_TIMER1 389 +#define SRST_TIMER2 390 +#define SRST_TIMER3 391 +#define SRST_TIMER4 392 +#define SRST_TIMER5 393 +#define SRST_P_UART1 394 +#define SRST_S_UART1 395 + +/* cru_softrst_con25 */ +#define SRST_P_UART2 400 +#define SRST_S_UART2 401 +#define SRST_P_UART3 402 +#define SRST_S_UART3 403 +#define SRST_P_UART4 404 +#define SRST_S_UART4 405 +#define SRST_P_UART5 406 +#define SRST_S_UART5 407 +#define SRST_P_UART6 408 +#define SRST_S_UART6 409 +#define SRST_P_UART7 410 +#define SRST_S_UART7 411 +#define SRST_P_UART8 412 +#define SRST_S_UART8 413 +#define SRST_P_UART9 414 +#define SRST_S_UART9 415 + +/* cru_softrst_con26 */ +#define SRST_P_GRF 416 +#define SRST_P_GRF_VCCIO12 417 +#define SRST_P_GRF_VCCIO34 418 +#define SRST_P_GRF_VCCIO567 419 +#define SRST_P_SCR 420 +#define SRST_P_WDT_NS 421 +#define SRST_T_WDT_NS 422 +#define SRST_P_DFT2APB 423 +#define SRST_A_MCU 426 +#define SRST_P_INTMUX 427 +#define SRST_P_MAILBOX 428 + +/* cru_softrst_con27 */ +#define SRST_A_TOP_HIGH_NIU 432 +#define SRST_A_TOP_LOW_NIU 433 +#define SRST_H_TOP_NIU 434 +#define SRST_P_TOP_NIU 435 +#define SRST_P_TOP_CRU 438 +#define SRST_P_DDRPHY 439 +#define SRST_DDRPHY 440 +#define SRST_P_MIPICSIPHY 442 +#define SRST_P_MIPIDSIPHY0 443 +#define SRST_P_MIPIDSIPHY1 444 +#define SRST_P_PCIE30PHY 445 +#define SRST_PCIE30PHY 446 +#define SRST_P_PCIE30PHY_GRF 447 + +/* cru_softrst_con28 */ +#define SRST_P_APB2ASB_LEFT 448 +#define SRST_P_APB2ASB_BOTTOM 449 +#define SRST_P_ASB2APB_LEFT 450 +#define SRST_P_ASB2APB_BOTTOM 451 +#define SRST_P_PIPEPHY0 452 +#define SRST_PIPEPHY0 453 +#define SRST_P_PIPEPHY1 454 +#define SRST_PIPEPHY1 455 +#define SRST_P_PIPEPHY2 456 +#define SRST_PIPEPHY2 457 +#define SRST_P_USB2PHY0_GRF 458 +#define SRST_P_USB2PHY1_GRF 459 +#define SRST_P_CPU_BOOST 460 +#define SRST_CPU_BOOST 461 +#define SRST_P_OTPPHY 462 +#define SRST_OTPPHY 463 + +/* cru_softrst_con29 */ +#define SRST_USB2PHY0_POR 464 +#define SRST_USB2PHY0_USB3OTG0 465 +#define SRST_USB2PHY0_USB3OTG1 466 +#define SRST_USB2PHY1_POR 467 +#define SRST_USB2PHY1_USB2HOST0 468 +#define SRST_USB2PHY1_USB2HOST1 469 +#define SRST_P_EDPPHY_GRF 470 +#define SRST_TSADCPHY 471 +#define SRST_GMAC0_DELAYLINE 472 +#define SRST_GMAC1_DELAYLINE 473 +#define SRST_OTPC_ARB 474 +#define SRST_P_PIPEPHY0_GRF 475 +#define SRST_P_PIPEPHY1_GRF 476 +#define SRST_P_PIPEPHY2_GRF 477 + +#endif From 4a262feba3a52d9ecc98ab04dcf61e84d48d651b Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 2 Jun 2021 11:39:24 +0800 Subject: [PATCH 104/250] rockchip: rk3568: add clock driver Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/cru_rk3568.h | 504 +++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3568.c | 2959 +++++++++++++++++ 3 files changed, 3464 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h create mode 100644 drivers/clk/rockchip/clk_rk3568.c diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h new file mode 100644 index 00000000000..6c59033f03a --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _ASM_ARCH_CRU_RK3568_H +#define _ASM_ARCH_CRU_RK3568_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (816 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (1000 * MHz) +#define PPLL_HZ (100 * MHz) + +/* RK3568 pll id */ +enum rk3568_pll_id { + APLL, + DPLL, + CPLL, + GPLL, + NPLL, + VPLL, + PPLL, + HPLL, + PLL_COUNT, +}; + +struct rk3568_clk_info { + unsigned long id; + char *name; + bool is_cru; +}; + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3568_pmuclk_priv { + struct rk3568_pmucru *pmucru; + ulong ppll_hz; + ulong hpll_hz; +}; + +struct rk3568_clk_priv { + struct rk3568_cru *cru; + struct rk3568_grf *grf; + ulong ppll_hz; + ulong hpll_hz; + ulong gpll_hz; + ulong cpll_hz; + ulong npll_hz; + ulong vpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rk3568_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct rk3568_pmucru { + struct rk3568_pll pll[2];/* Address Offset: 0x0000 */ + unsigned int reserved0[16];/* Address Offset: 0x0040 */ + unsigned int mode_con00;/* Address Offset: 0x0080 */ + unsigned int reserved1[31];/* Address Offset: 0x0084 */ + unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */ + unsigned int reserved2[22];/* Address Offset: 0x0128 */ + unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */ + unsigned int reserved3[29];/* Address Offset: 0x018C */ + unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */ +}; + +check_member(rk3568_pmucru, mode_con00, 0x80); +check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200); + +struct rk3568_cru { + struct rk3568_pll pll[6]; + unsigned int mode_con00;/* Address Offset: 0x00C0 */ + unsigned int misc_con[3];/* Address Offset: 0x00C4 */ + unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */ + unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */ + unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */ + unsigned int glb_rst_con;/* Address Offset: 0x00DC */ + unsigned int glb_rst_st;/* Address Offset: 0x00E0 */ + unsigned int reserved0[7];/* Address Offset: 0x00E4 */ + unsigned int clksel_con[85]; /* Address Offset: 0x0100 */ + unsigned int reserved1[43];/* Address Offset: 0x0254 */ + unsigned int clkgate_con[36];/* Address Offset: 0x0300 */ + unsigned int reserved2[28]; /* Address Offset: 0x0390 */ + unsigned int softrst_con[30];/* Address Offset: 0x0400 */ + unsigned int reserved3[2];/* Address Offset: 0x0478 */ + unsigned int ssgtbl[32];/* Address Offset: 0x0480 */ + unsigned int reserved4[32];/* Address Offset: 0x0500 */ + unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */ + unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */ + unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */ + unsigned int emmc_con[2];/* Address Offset: 0x0598 */ +}; + +check_member(rk3568_cru, mode_con00, 0xc0); +check_member(rk3568_cru, softrst_con[0], 0x400); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RK3568_PMU_MODE 0x80 +#define RK3568_PMU_PLL_CON(x) ((x) * 0x4) +#define RK3568_PLL_CON(x) ((x) * 0x4) +#define RK3568_MODE_CON 0xc0 + +enum { + /* CRU_PMU_CLK_SEL0_CON */ + RTC32K_SEL_SHIFT = 6, + RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, + RTC32K_SEL_PMUPVTM = 0, + RTC32K_SEL_OSC1_32K, + RTC32K_SEL_OSC0_DIV32K, + + /* CRU_PMU_CLK_SEL1_CON */ + RTC32K_FRAC_NUMERATOR_SHIFT = 16, + RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, + RTC32K_FRAC_DENOMINATOR_SHIFT = 0, + RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_PMU_CLK_SEL2_CON */ + PCLK_PDPMU_SEL_SHIFT = 15, + PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT, + PCLK_PDPMU_SEL_PPLL = 0, + PCLK_PDPMU_SEL_GPLL, + PCLK_PDPMU_DIV_SHIFT = 0, + PCLK_PDPMU_DIV_MASK = 0x1f, + + /* CRU_PMU_CLK_SEL3_CON */ + CLK_I2C0_DIV_SHIFT = 0, + CLK_I2C0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL6_CON */ + CLK_PWM0_SEL_SHIFT = 7, + CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, + CLK_PWM0_SEL_XIN24M = 0, + CLK_PWM0_SEL_PPLL, + CLK_PWM0_DIV_SHIFT = 0, + CLK_PWM0_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL0_CON */ + CLK_CORE_PRE_SEL_SHIFT = 7, + CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT, + CLK_CORE_PRE_SEL_SRC = 0, + CLK_CORE_PRE_SEL_APLL, + + /* CRU_CLK_SEL2_CON */ + SCLK_CORE_PRE_SEL_SHIFT = 15, + SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT, + SCLK_CORE_PRE_SEL_SRC = 0, + SCLK_CORE_PRE_SEL_NPLL, + SCLK_CORE_SRC_SEL_SHIFT = 8, + SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT, + SCLK_CORE_SRC_SEL_APLL = 0, + SCLK_CORE_SRC_SEL_GPLL, + SCLK_CORE_SRC_SEL_NPLL, + SCLK_CORE_SRC_DIV_SHIFT = 0, + SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL3_CON */ + GICCLK_CORE_DIV_SHIFT = 8, + GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT, + ATCLK_CORE_DIV_SHIFT = 0, + ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT, + + /* CRU_CLK_SEL4_CON */ + PERIPHCLK_CORE_PRE_DIV_SHIFT = 8, + PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT, + PCLK_CORE_PRE_DIV_SHIFT = 0, + PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT, + + /* CRU_CLK_SEL5_CON */ + ACLK_CORE_NIU2BUS_SEL_SHIFT = 14, + ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT, + ACLK_CORE_NDFT_DIV_SHIFT = 8, + ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT, + + /* CRU_CLK_SEL10_CON */ + HCLK_PERIMID_SEL_SHIFT = 6, + HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT, + HCLK_PERIMID_SEL_150M = 0, + HCLK_PERIMID_SEL_100M, + HCLK_PERIMID_SEL_75M, + HCLK_PERIMID_SEL_24M, + ACLK_PERIMID_SEL_SHIFT = 4, + ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT, + ACLK_PERIMID_SEL_300M = 0, + ACLK_PERIMID_SEL_200M, + ACLK_PERIMID_SEL_100M, + ACLK_PERIMID_SEL_24M, + + /* CRU_CLK_SEL27_CON */ + CLK_CRYPTO_PKA_SEL_SHIFT = 6, + CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT, + CLK_CRYPTO_PKA_SEL_300M = 0, + CLK_CRYPTO_PKA_SEL_200M, + CLK_CRYPTO_PKA_SEL_100M, + CLK_CRYPTO_CORE_SEL_SHIFT = 4, + CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT, + CLK_CRYPTO_CORE_SEL_200M = 0, + CLK_CRYPTO_CORE_SEL_150M, + CLK_CRYPTO_CORE_SEL_100M, + HCLK_SECURE_FLASH_SEL_SHIFT = 2, + HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT, + HCLK_SECURE_FLASH_SEL_150M = 0, + HCLK_SECURE_FLASH_SEL_100M, + HCLK_SECURE_FLASH_SEL_75M, + HCLK_SECURE_FLASH_SEL_24M, + ACLK_SECURE_FLASH_SEL_SHIFT = 0, + ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT, + ACLK_SECURE_FLASH_SEL_200M = 0, + ACLK_SECURE_FLASH_SEL_150M, + ACLK_SECURE_FLASH_SEL_100M, + ACLK_SECURE_FLASH_SEL_24M, + + /* CRU_CLK_SEL28_CON */ + CCLK_EMMC_SEL_SHIFT = 12, + CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT, + CCLK_EMMC_SEL_24M = 0, + CCLK_EMMC_SEL_200M, + CCLK_EMMC_SEL_150M, + CCLK_EMMC_SEL_100M, + CCLK_EMMC_SEL_50M, + CCLK_EMMC_SEL_375K, + BCLK_EMMC_SEL_SHIFT = 8, + BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_200M = 0, + BCLK_EMMC_SEL_150M, + BCLK_EMMC_SEL_125M, + SCLK_SFC_SEL_SHIFT = 4, + SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT, + SCLK_SFC_SEL_24M = 0, + SCLK_SFC_SEL_50M, + SCLK_SFC_SEL_75M, + SCLK_SFC_SEL_100M, + SCLK_SFC_SEL_125M, + SCLK_SFC_SEL_150M, + NCLK_NANDC_SEL_SHIFT = 0, + NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT, + NCLK_NANDC_SEL_200M = 0, + NCLK_NANDC_SEL_150M, + NCLK_NANDC_SEL_100M, + NCLK_NANDC_SEL_24M, + + /* CRU_CLK_SEL30_CON */ + CLK_SDMMC1_SEL_SHIFT = 12, + CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT, + CLK_SDMMC0_SEL_SHIFT = 8, + CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT, + CLK_SDMMC_SEL_24M = 0, + CLK_SDMMC_SEL_400M, + CLK_SDMMC_SEL_300M, + CLK_SDMMC_SEL_100M, + CLK_SDMMC_SEL_50M, + CLK_SDMMC_SEL_750K, + + /* CRU_CLK_SEL31_CON */ + CLK_MAC0_OUT_SEL_SHIFT = 14, + CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT, + CLK_MAC0_OUT_SEL_125M = 0, + CLK_MAC0_OUT_SEL_50M, + CLK_MAC0_OUT_SEL_25M, + CLK_MAC0_OUT_SEL_24M, + CLK_GMAC0_PTP_REF_SEL_SHIFT = 12, + CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT, + CLK_GMAC0_PTP_REF_SEL_62_5M = 0, + CLK_GMAC0_PTP_REF_SEL_100M, + CLK_GMAC0_PTP_REF_SEL_50M, + CLK_GMAC0_PTP_REF_SEL_24M, + CLK_MAC0_2TOP_SEL_SHIFT = 8, + CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT, + CLK_MAC0_2TOP_SEL_125M = 0, + CLK_MAC0_2TOP_SEL_50M, + CLK_MAC0_2TOP_SEL_25M, + CLK_MAC0_2TOP_SEL_PPLL, + RGMII0_CLK_SEL_SHIFT = 4, + RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT, + RGMII0_CLK_SEL_125M = 0, + RGMII0_CLK_SEL_125M_1, + RGMII0_CLK_SEL_2_5M, + RGMII0_CLK_SEL_25M, + RMII0_CLK_SEL_SHIFT = 3, + RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT, + RMII0_CLK_SEL_2_5M = 0, + RMII0_CLK_SEL_25M, + RMII0_EXTCLK_SEL_SHIFT = 2, + RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT, + RMII0_EXTCLK_SEL_MAC0_TOP = 0, + RMII0_EXTCLK_SEL_IO, + RMII0_MODE_SHIFT = 0, + RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT, + RMII0_MODE_SEL_RGMII = 0, + RMII0_MODE_SEL_RMII, + RMII0_MODE_SEL_GMII, + + /* CRU_CLK_SEL32_CON */ + CLK_SDMMC2_SEL_SHIFT = 8, + CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT, + + /* CRU_CLK_SEL38_CON */ + ACLK_VOP_PRE_SEL_SHIFT = 6, + ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT, + ACLK_VOP_PRE_SEL_CPLL = 0, + ACLK_VOP_PRE_SEL_GPLL, + ACLK_VOP_PRE_SEL_HPLL, + ACLK_VOP_PRE_SEL_VPLL, + ACLK_VOP_PRE_DIV_SHIFT = 0, + ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT, + + /* CRU_CLK_SEL39_CON */ + DCLK0_VOP_SEL_SHIFT = 10, + DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT, + DCLK_VOP_SEL_HPLL = 0, + DCLK_VOP_SEL_VPLL, + DCLK_VOP_SEL_GPLL, + DCLK_VOP_SEL_CPLL, + DCLK0_VOP_DIV_SHIFT = 0, + DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT, + + /* CRU_CLK_SEL40_CON */ + DCLK1_VOP_SEL_SHIFT = 10, + DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT, + DCLK1_VOP_DIV_SHIFT = 0, + DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT, + + /* CRU_CLK_SEL41_CON */ + DCLK2_VOP_SEL_SHIFT = 10, + DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT, + DCLK2_VOP_DIV_SHIFT = 0, + DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT, + + /* CRU_CLK_SEL43_CON */ + DCLK_EBC_SEL_SHIFT = 6, + DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT, + DCLK_EBC_SEL_GPLL_400M = 0, + DCLK_EBC_SEL_CPLL_333M, + DCLK_EBC_SEL_GPLL_200M, + + /* CRU_CLK_SEL47_CON */ + ACLK_RKVDEC_SEL_SHIFT = 7, + ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT, + ACLK_RKVDEC_SEL_GPLL = 0, + ACLK_RKVDEC_SEL_CPLL, + ACLK_RKVDEC_DIV_SHIFT = 0, + ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT, + + /* CRU_CLK_SEL49_CON */ + CLK_RKVDEC_CORE_SEL_SHIFT = 14, + CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT, + CLK_RKVDEC_CORE_SEL_GPLL = 0, + CLK_RKVDEC_CORE_SEL_CPLL, + CLK_RKVDEC_CORE_SEL_NPLL, + CLK_RKVDEC_CORE_SEL_VPLL, + CLK_RKVDEC_CORE_DIV_SHIFT = 8, + CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT, + + /* CRU_CLK_SEL50_CON */ + PCLK_BUS_SEL_SHIFT = 4, + PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT, + PCLK_BUS_SEL_100M = 0, + PCLK_BUS_SEL_75M, + PCLK_BUS_SEL_50M, + PCLK_BUS_SEL_24M, + ACLK_BUS_SEL_SHIFT = 0, + ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT, + ACLK_BUS_SEL_200M = 0, + ACLK_BUS_SEL_150M, + ACLK_BUS_SEL_100M, + ACLK_BUS_SEL_24M, + + /* CRU_CLK_SEL51_CON */ + CLK_TSADC_DIV_SHIFT = 8, + CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT, + CLK_TSADC_TSEN_SEL_SHIFT = 4, + CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT, + CLK_TSADC_TSEN_SEL_24M = 0, + CLK_TSADC_TSEN_SEL_100M, + CLK_TSADC_TSEN_SEL_CPLL_100M, + CLK_TSADC_TSEN_DIV_SHIFT = 0, + CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT, + + /* CRU_CLK_SEL52_CON */ + CLK_UART_SEL_SHIFT = 12, + CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, + CLK_UART_SEL_SRC = 0, + CLK_UART_SEL_FRAC, + CLK_UART_SEL_XIN24M, + CLK_UART_SRC_SEL_SHIFT = 8, + CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, + CLK_UART_SRC_SEL_GPLL = 0, + CLK_UART_SRC_SEL_CPLL, + CLK_UART_SRC_SEL_480M, + CLK_UART_SRC_DIV_SHIFT = 0, + CLK_UART_SRC_DIV_MASK = 0x3f << CLK_UART_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL53_CON */ + CLK_UART_FRAC_NUMERATOR_SHIFT = 16, + CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, + CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL71_CON */ + CLK_I2C_SEL_SHIFT = 8, + CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT, + CLK_I2C_SEL_200M = 0, + CLK_I2C_SEL_100M, + CLK_I2C_SEL_24M, + CLK_I2C_SEL_CPLL_100M, + + /* CRU_CLK_SEL72_CON */ + CLK_PWM3_SEL_SHIFT = 12, + CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT, + CLK_PWM2_SEL_SHIFT = 10, + CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, + CLK_PWM_SEL_100M = 0, + CLK_PWM_SEL_24M, + CLK_PWM_SEL_CPLL_100M, + CLK_SPI3_SEL_SHIFT = 6, + CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, + CLK_SPI2_SEL_SHIFT = 4, + CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 2, + CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, + CLK_SPI0_SEL_SHIFT = 0, + CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, + CLK_SPI_SEL_200M = 0, + CLK_SPI_SEL_24M, + CLK_SPI_SEL_CPLL_100M, + + /* CRU_CLK_SEL73_CON */ + PCLK_TOP_SEL_SHIFT = 12, + PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, + PCLK_TOP_SEL_100M = 0, + PCLK_TOP_SEL_75M, + PCLK_TOP_SEL_50M, + PCLK_TOP_SEL_24M, + HCLK_TOP_SEL_SHIFT = 8, + HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, + HCLK_TOP_SEL_150M = 0, + HCLK_TOP_SEL_100M, + HCLK_TOP_SEL_75M, + HCLK_TOP_SEL_24M, + ACLK_TOP_LOW_SEL_SHIFT = 4, + ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT, + ACLK_TOP_LOW_SEL_400M = 0, + ACLK_TOP_LOW_SEL_300M, + ACLK_TOP_LOW_SEL_200M, + ACLK_TOP_LOW_SEL_24M, + ACLK_TOP_HIGH_SEL_SHIFT = 0, + ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT, + ACLK_TOP_HIGH_SEL_500M = 0, + ACLK_TOP_HIGH_SEL_400M, + ACLK_TOP_HIGH_SEL_300M, + ACLK_TOP_HIGH_SEL_24M, + + /* CRU_CLK_SEL78_CON */ + CPLL_500M_DIV_SHIFT = 8, + CPLL_500M_DIV_MASK = 0x1f << CPLL_500M_DIV_SHIFT, + + /* CRU_CLK_SEL79_CON */ + CPLL_250M_DIV_SHIFT = 8, + CPLL_250M_DIV_MASK = 0x1f << CPLL_250M_DIV_SHIFT, + CPLL_333M_DIV_SHIFT = 0, + CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT, + + /* CRU_CLK_SEL80_CON */ + CPLL_62P5M_DIV_SHIFT = 8, + CPLL_62P5M_DIV_MASK = 0x1f << CPLL_62P5M_DIV_SHIFT, + CPLL_125M_DIV_SHIFT = 0, + CPLL_125M_DIV_MASK = 0x1f << CPLL_125M_DIV_SHIFT, + + /* CRU_CLK_SEL81_CON */ + CPLL_25M_DIV_SHIFT = 8, + CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT, + CPLL_50M_DIV_SHIFT = 0, + CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, + + /* CRU_CLK_SEL82_CON */ + CPLL_100M_DIV_SHIFT = 0, + CPLL_100M_DIV_MASK = 0x1f << CPLL_100M_DIV_SHIFT, +}; +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 4cfcf833092..913f611a0ff 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c new file mode 100644 index 00000000000..553c6c0dafb --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -0,0 +1,2959 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * Author: Elaine Zhang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct rk3568_clk_plat { + struct dtd_rockchip_rk3568_cru dtd; +}; + +struct rk3568_pmuclk_plat { + struct dtd_rockchip_rk3568_pmucru dtd; +}; +#endif + +#define RK3568_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ +{ \ + .rate = _rate##U, \ + .aclk_div = _aclk_div, \ + .pclk_div = _pclk_div, \ +} + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +static struct rockchip_cpu_rate_table rk3568_cpu_rates[] = { + RK3568_CPUCLK_RATE(1416000000, 1, 5), + RK3568_CPUCLK_RATE(1296000000, 1, 5), + RK3568_CPUCLK_RATE(1200000000, 1, 3), + RK3568_CPUCLK_RATE(1104000000, 1, 3), + RK3568_CPUCLK_RATE(1008000000, 1, 3), + RK3568_CPUCLK_RATE(912000000, 1, 3), + RK3568_CPUCLK_RATE(816000000, 1, 3), + RK3568_CPUCLK_RATE(600000000, 1, 1), + RK3568_CPUCLK_RATE(408000000, 1, 1), + { /* sentinel */ }, +}; + +static struct rockchip_pll_rate_table rk3568_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(400000000, 1, 100, 6, 1, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rk3568_pll_clks[] = { + [APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0), + RK3568_MODE_CON, 0, 10, 0, rk3568_pll_rates), + [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8), + RK3568_MODE_CON, 2, 10, 0, NULL), + [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24), + RK3568_MODE_CON, 4, 10, 0, rk3568_pll_rates), + [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16), + RK3568_MODE_CON, 6, 10, 0, rk3568_pll_rates), + [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32), + RK3568_MODE_CON, 10, 10, 0, rk3568_pll_rates), + [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40), + RK3568_MODE_CON, 12, 10, 0, rk3568_pll_rates), + [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0), + RK3568_PMU_MODE, 0, 10, 0, rk3568_pll_rates), + [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16), + RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates), +}; + +#ifndef CONFIG_SPL_BUILD +static ulong +rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv, + ulong pll_id, ulong rate) +{ + struct udevice *pmucru_dev; + struct rk3568_pmuclk_priv *pmu_priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3568_pmucru), + &pmucru_dev); + if (ret) { + printf("%s: could not find pmucru device\n", __func__); + return ret; + } + pmu_priv = dev_get_priv(pmucru_dev); + + rockchip_pll_set_rate(&rk3568_pll_clks[pll_id], + pmu_priv->pmucru, pll_id, rate); + + return 0; +} +#endif + +static ulong rk3568_pmu_pll_get_rate(struct rk3568_clk_priv *priv, + ulong pll_id) +{ + struct udevice *pmucru_dev; + struct rk3568_pmuclk_priv *pmu_priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3568_pmucru), + &pmucru_dev); + if (ret) { + printf("%s: could not find pmucru device\n", __func__); + return ret; + } + pmu_priv = dev_get_priv(pmucru_dev); + + return rockchip_pll_get_rate(&rk3568_pll_clks[pll_id], + pmu_priv->pmucru, pll_id); +} + +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + +static ulong rk3568_rtc32k_get_pmuclk(struct rk3568_pmuclk_priv *priv) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + unsigned long m, n; + u32 fracdiv; + + fracdiv = readl(&pmucru->pmu_clksel_con[1]); + m = fracdiv & RTC32K_FRAC_NUMERATOR_MASK; + m >>= RTC32K_FRAC_NUMERATOR_SHIFT; + n = fracdiv & RTC32K_FRAC_DENOMINATOR_MASK; + n >>= RTC32K_FRAC_DENOMINATOR_SHIFT; + + return OSC_HZ * m / n; +} + +static ulong rk3568_rtc32k_set_pmuclk(struct rk3568_pmuclk_priv *priv, + ulong rate) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + unsigned long m, n, val; + + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); + + rational_best_approximation(rate, OSC_HZ, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + val = m << RTC32K_FRAC_NUMERATOR_SHIFT | n; + writel(val, &pmucru->pmu_clksel_con[1]); + + return rk3568_rtc32k_get_pmuclk(priv); +} + +static ulong rk3568_i2c_get_pmuclk(struct rk3568_pmuclk_priv *priv, + ulong clk_id) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + u32 div, con; + + switch (clk_id) { + case CLK_I2C0: + con = readl(&pmucru->pmu_clksel_con[3]); + div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->ppll_hz, div); +} + +static ulong rk3568_i2c_set_pmuclk(struct rk3568_pmuclk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); + assert(src_clk_div - 1 <= 127); + + switch (clk_id) { + case CLK_I2C0: + rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C0_DIV_MASK, + (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3568_i2c_get_pmuclk(priv, clk_id); +} + +static ulong rk3568_pwm_get_pmuclk(struct rk3568_pmuclk_priv *priv, + ulong clk_id) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + u32 div, sel, con, parent; + + switch (clk_id) { + case CLK_PWM0: + con = readl(&pmucru->pmu_clksel_con[6]); + sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; + div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; + if (sel == CLK_PWM0_SEL_XIN24M) + parent = OSC_HZ; + else + parent = priv->ppll_hz; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3568_pwm_set_pmuclk(struct rk3568_pmuclk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + switch (clk_id) { + case CLK_PWM0: + if (rate == OSC_HZ) { + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK, + (CLK_PWM0_SEL_XIN24M << + CLK_PWM0_SEL_SHIFT) | + 0 << CLK_PWM0_SEL_SHIFT); + } else { + src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_DIV_MASK | CLK_PWM0_DIV_MASK, + (CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) | + (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); + } + break; + default: + return -ENOENT; + } + + return rk3568_pwm_get_pmuclk(priv, clk_id); +} + +static ulong rk3568_pmu_get_pmuclk(struct rk3568_pmuclk_priv *priv) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + u32 div, con, sel, parent; + + con = readl(&pmucru->pmu_clksel_con[2]); + sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT; + div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT; + if (sel) + parent = GPLL_HZ; + else + parent = priv->ppll_hz; + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3568_pmu_set_pmuclk(struct rk3568_pmuclk_priv *priv, + ulong rate) +{ + struct rk3568_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&pmucru->pmu_clksel_con[2], + PCLK_PDPMU_DIV_MASK | PCLK_PDPMU_SEL_MASK, + (PCLK_PDPMU_SEL_PPLL << PCLK_PDPMU_SEL_SHIFT) | + ((src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT)); + + return rk3568_pmu_get_pmuclk(priv); +} + +static ulong rk3568_pmuclk_get_rate(struct clk *clk) +{ + struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->ppll_hz) { + printf("%s ppll=%lu\n", __func__, priv->ppll_hz); + return -ENOENT; + } + + debug("%s %ld\n", __func__, clk->id); + switch (clk->id) { + case PLL_PPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], + priv->pmucru, PPLL); + break; + case PLL_HPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], + priv->pmucru, HPLL); + break; + case CLK_RTC_32K: + case CLK_RTC32K_FRAC: + rate = rk3568_rtc32k_get_pmuclk(priv); + break; + case CLK_I2C0: + rate = rk3568_i2c_get_pmuclk(priv, clk->id); + break; + case CLK_PWM0: + rate = rk3568_pwm_get_pmuclk(priv, clk->id); + break; + case PCLK_PMU: + rate = rk3568_pmu_get_pmuclk(priv); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->ppll_hz) { + printf("%s ppll=%lu\n", __func__, priv->ppll_hz); + return -ENOENT; + } + + debug("%s %ld %ld\n", __func__, clk->id, rate); + switch (clk->id) { + case PLL_PPLL: + ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL], + priv->pmucru, PPLL, rate); + priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], + priv->pmucru, PPLL); + break; + case PLL_HPLL: + ret = rockchip_pll_set_rate(&rk3568_pll_clks[HPLL], + priv->pmucru, HPLL, rate); + priv->hpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], + priv->pmucru, HPLL); + break; + case CLK_RTC_32K: + case CLK_RTC32K_FRAC: + ret = rk3568_rtc32k_set_pmuclk(priv, rate); + break; + case CLK_I2C0: + ret = rk3568_i2c_set_pmuclk(priv, clk->id, rate); + break; + case CLK_PWM0: + ret = rk3568_pwm_set_pmuclk(priv, clk->id, rate); + break; + case PCLK_PMU: + ret = rk3568_pmu_set_pmuclk(priv, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static int rk3568_rtc32k_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_pmucru *pmucru = priv->pmucru; + + if (parent->id == CLK_RTC32K_FRAC) + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); + else + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT); + + return 0; +} + +static int rk3568_pmuclk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case CLK_RTC_32K: + return rk3568_rtc32k_set_parent(clk, parent); + default: + return -ENOENT; + } +} + +static struct clk_ops rk3568_pmuclk_ops = { + .get_rate = rk3568_pmuclk_get_rate, + .set_rate = rk3568_pmuclk_set_rate, + .set_parent = rk3568_pmuclk_set_parent, +}; + +static int rk3568_pmuclk_probe(struct udevice *dev) +{ + struct rk3568_pmuclk_priv *priv = dev_get_priv(dev); + int ret = 0; + + if (priv->ppll_hz != PPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL], + priv->pmucru, + PPLL, PPLL_HZ); + if (!ret) + priv->ppll_hz = PPLL_HZ; + } + + /* Ungate PCIe30phy refclk_m and refclk_n */ + rk_clrsetreg(&priv->pmucru->pmu_clkgate_con[2], 0x3 << 13, 0 << 13); + return 0; +} + +static int rk3568_pmuclk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3568_pmuclk_priv *priv = dev_get_priv(dev); + + priv->pmucru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rk3568_pmuclk_bind(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + int ret = 0; + + ret = offsetof(struct rk3568_pmucru, pmu_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 1); + if (ret) + debug("Warning: pmucru software reset driver bind faile\n"); +#endif + + return 0; +} + +static const struct udevice_id rk3568_pmuclk_ids[] = { + { .compatible = "rockchip,rk3568-pmucru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3568_pmucru) = { + .name = "rockchip_rk3568_pmucru", + .id = UCLASS_CLK, + .of_match = rk3568_pmuclk_ids, + .priv_auto = sizeof(struct rk3568_pmuclk_priv), + .of_to_plat = rk3568_pmuclk_ofdata_to_platdata, + .ops = &rk3568_pmuclk_ops, + .bind = rk3568_pmuclk_bind, + .probe = rk3568_pmuclk_probe, +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .plat_auto = sizeof(struct rk3568_pmuclk_plat), +#endif + +}; + +static int rk3568_armclk_set_clk(struct rk3568_clk_priv *priv, ulong hz) +{ + struct rk3568_cru *cru = priv->cru; + const struct rockchip_cpu_rate_table *rate; + ulong old_rate; + + rate = rockchip_get_cpu_settings(rk3568_cpu_rates, hz); + if (!rate) { + printf("%s unsupported rate\n", __func__); + return -EINVAL; + } + + rk_clrsetreg(&cru->clksel_con[0], + CLK_CORE_PRE_SEL_MASK, + (CLK_CORE_PRE_SEL_SRC << CLK_CORE_PRE_SEL_SHIFT)); + rk_clrsetreg(&cru->clksel_con[2], + SCLK_CORE_PRE_SEL_MASK | + SCLK_CORE_SRC_SEL_MASK | + SCLK_CORE_SRC_DIV_MASK, + (SCLK_CORE_PRE_SEL_SRC << + SCLK_CORE_PRE_SEL_SHIFT) | + (SCLK_CORE_SRC_SEL_APLL << + SCLK_CORE_SRC_SEL_SHIFT) | + (1 << SCLK_CORE_SRC_DIV_SHIFT)); + + /* + * set up dependent divisors for DBG and ACLK clocks. + */ + old_rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], + priv->cru, APLL); + if (old_rate > hz) { + if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL], + priv->cru, APLL, hz)) + return -EINVAL; + rk_clrsetreg(&cru->clksel_con[3], + GICCLK_CORE_DIV_MASK | ATCLK_CORE_DIV_MASK, + rate->pclk_div << GICCLK_CORE_DIV_SHIFT | + rate->pclk_div << ATCLK_CORE_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[4], + PERIPHCLK_CORE_PRE_DIV_MASK | + PCLK_CORE_PRE_DIV_MASK, + rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT | + rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[5], + ACLK_CORE_NDFT_DIV_MASK, + rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT); + } else if (old_rate < hz) { + rk_clrsetreg(&cru->clksel_con[3], + GICCLK_CORE_DIV_MASK | ATCLK_CORE_DIV_MASK, + rate->pclk_div << GICCLK_CORE_DIV_SHIFT | + rate->pclk_div << ATCLK_CORE_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[4], + PERIPHCLK_CORE_PRE_DIV_MASK | + PCLK_CORE_PRE_DIV_MASK, + rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT | + rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[5], + ACLK_CORE_NDFT_DIV_MASK, + rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT); + if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL], + priv->cru, APLL, hz)) + return -EINVAL; + } + + return 0; +} + +static ulong rk3568_cpll_div_get_rate(struct rk3568_clk_priv *priv, + ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + int div, mask, shift, con; + + switch (clk_id) { + case CPLL_500M: + con = 78; + mask = CPLL_500M_DIV_MASK; + shift = CPLL_500M_DIV_SHIFT; + break; + case CPLL_333M: + con = 79; + mask = CPLL_333M_DIV_MASK; + shift = CPLL_333M_DIV_SHIFT; + break; + case CPLL_250M: + con = 79; + mask = CPLL_250M_DIV_MASK; + shift = CPLL_250M_DIV_SHIFT; + break; + case CPLL_125M: + con = 80; + mask = CPLL_125M_DIV_MASK; + shift = CPLL_125M_DIV_SHIFT; + break; + case CPLL_100M: + con = 82; + mask = CPLL_100M_DIV_MASK; + shift = CPLL_100M_DIV_SHIFT; + break; + case CPLL_62P5M: + con = 80; + mask = CPLL_62P5M_DIV_MASK; + shift = CPLL_62P5M_DIV_SHIFT; + break; + case CPLL_50M: + con = 81; + mask = CPLL_50M_DIV_MASK; + shift = CPLL_50M_DIV_SHIFT; + break; + case CPLL_25M: + con = 81; + mask = CPLL_25M_DIV_MASK; + shift = CPLL_25M_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + div = (readl(&cru->clksel_con[con]) & mask) >> shift; + return DIV_TO_RATE(priv->cpll_hz, div); +} + +static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int div, mask, shift, con; + + switch (clk_id) { + case CPLL_500M: + con = 78; + mask = CPLL_500M_DIV_MASK; + shift = CPLL_500M_DIV_SHIFT; + break; + case CPLL_333M: + con = 79; + mask = CPLL_333M_DIV_MASK; + shift = CPLL_333M_DIV_SHIFT; + break; + case CPLL_250M: + con = 79; + mask = CPLL_250M_DIV_MASK; + shift = CPLL_250M_DIV_SHIFT; + break; + case CPLL_125M: + con = 80; + mask = CPLL_125M_DIV_MASK; + shift = CPLL_125M_DIV_SHIFT; + break; + case CPLL_100M: + con = 82; + mask = CPLL_100M_DIV_MASK; + shift = CPLL_100M_DIV_SHIFT; + break; + case CPLL_62P5M: + con = 80; + mask = CPLL_62P5M_DIV_MASK; + shift = CPLL_62P5M_DIV_SHIFT; + break; + case CPLL_50M: + con = 81; + mask = CPLL_50M_DIV_MASK; + shift = CPLL_50M_DIV_SHIFT; + break; + case CPLL_25M: + con = 81; + mask = CPLL_25M_DIV_MASK; + shift = CPLL_25M_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + div = DIV_ROUND_UP(priv->cpll_hz, rate); + assert(div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[con], + mask, (div - 1) << shift); + return rk3568_cpll_div_get_rate(priv, clk_id); +} + +static ulong rk3568_bus_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 con, sel, rate; + + switch (clk_id) { + case ACLK_BUS: + con = readl(&cru->clksel_con[50]); + sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; + if (sel == ACLK_BUS_SEL_200M) + rate = 200 * MHz; + else if (sel == ACLK_BUS_SEL_150M) + rate = 150 * MHz; + else if (sel == ACLK_BUS_SEL_100M) + rate = 100 * MHz; + else + rate = OSC_HZ; + break; + case PCLK_BUS: + case PCLK_WDT_NS: + con = readl(&cru->clksel_con[50]); + sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT; + if (sel == PCLK_BUS_SEL_100M) + rate = 100 * MHz; + else if (sel == PCLK_BUS_SEL_75M) + rate = 75 * MHz; + else if (sel == PCLK_BUS_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3568_bus_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (clk_id) { + case ACLK_BUS: + if (rate == 200 * MHz) + src_clk = ACLK_BUS_SEL_200M; + else if (rate == 150 * MHz) + src_clk = ACLK_BUS_SEL_150M; + else if (rate == 100 * MHz) + src_clk = ACLK_BUS_SEL_100M; + else + src_clk = ACLK_BUS_SEL_24M; + rk_clrsetreg(&cru->clksel_con[50], + ACLK_BUS_SEL_MASK, + src_clk << ACLK_BUS_SEL_SHIFT); + break; + case PCLK_BUS: + case PCLK_WDT_NS: + if (rate == 100 * MHz) + src_clk = PCLK_BUS_SEL_100M; + else if (rate == 75 * MHz) + src_clk = PCLK_BUS_SEL_75M; + else if (rate == 50 * MHz) + src_clk = PCLK_BUS_SEL_50M; + else + src_clk = PCLK_BUS_SEL_24M; + rk_clrsetreg(&cru->clksel_con[50], + PCLK_BUS_SEL_MASK, + src_clk << PCLK_BUS_SEL_SHIFT); + break; + + default: + printf("do not support this bus freq\n"); + return -EINVAL; + } + + return rk3568_bus_get_clk(priv, clk_id); +} + +static ulong rk3568_perimid_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 con, sel, rate; + + switch (clk_id) { + case ACLK_PERIMID: + con = readl(&cru->clksel_con[10]); + sel = (con & ACLK_PERIMID_SEL_MASK) >> ACLK_PERIMID_SEL_SHIFT; + if (sel == ACLK_PERIMID_SEL_300M) + rate = 300 * MHz; + else if (sel == ACLK_PERIMID_SEL_200M) + rate = 200 * MHz; + else if (sel == ACLK_PERIMID_SEL_100M) + rate = 100 * MHz; + else + rate = OSC_HZ; + break; + case HCLK_PERIMID: + con = readl(&cru->clksel_con[10]); + sel = (con & HCLK_PERIMID_SEL_MASK) >> HCLK_PERIMID_SEL_SHIFT; + if (sel == HCLK_PERIMID_SEL_150M) + rate = 150 * MHz; + else if (sel == HCLK_PERIMID_SEL_100M) + rate = 100 * MHz; + else if (sel == HCLK_PERIMID_SEL_75M) + rate = 75 * MHz; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3568_perimid_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (clk_id) { + case ACLK_PERIMID: + if (rate == 300 * MHz) + src_clk = ACLK_PERIMID_SEL_300M; + else if (rate == 200 * MHz) + src_clk = ACLK_PERIMID_SEL_200M; + else if (rate == 100 * MHz) + src_clk = ACLK_PERIMID_SEL_100M; + else + src_clk = ACLK_PERIMID_SEL_24M; + rk_clrsetreg(&cru->clksel_con[10], + ACLK_PERIMID_SEL_MASK, + src_clk << ACLK_PERIMID_SEL_SHIFT); + break; + case HCLK_PERIMID: + if (rate == 150 * MHz) + src_clk = HCLK_PERIMID_SEL_150M; + else if (rate == 100 * MHz) + src_clk = HCLK_PERIMID_SEL_100M; + else if (rate == 75 * MHz) + src_clk = HCLK_PERIMID_SEL_75M; + else + src_clk = HCLK_PERIMID_SEL_24M; + rk_clrsetreg(&cru->clksel_con[10], + HCLK_PERIMID_SEL_MASK, + src_clk << HCLK_PERIMID_SEL_SHIFT); + break; + + default: + printf("do not support this permid freq\n"); + return -EINVAL; + } + + return rk3568_perimid_get_clk(priv, clk_id); +} + +static ulong rk3568_top_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 con, sel, rate; + + switch (clk_id) { + case ACLK_TOP_HIGH: + con = readl(&cru->clksel_con[73]); + sel = (con & ACLK_TOP_HIGH_SEL_MASK) >> ACLK_TOP_HIGH_SEL_SHIFT; + if (sel == ACLK_TOP_HIGH_SEL_500M) + rate = 500 * MHz; + else if (sel == ACLK_TOP_HIGH_SEL_400M) + rate = 400 * MHz; + else if (sel == ACLK_TOP_HIGH_SEL_300M) + rate = 300 * MHz; + else + rate = OSC_HZ; + break; + case ACLK_TOP_LOW: + con = readl(&cru->clksel_con[73]); + sel = (con & ACLK_TOP_LOW_SEL_MASK) >> ACLK_TOP_LOW_SEL_SHIFT; + if (sel == ACLK_TOP_LOW_SEL_400M) + rate = 400 * MHz; + else if (sel == ACLK_TOP_LOW_SEL_300M) + rate = 300 * MHz; + else if (sel == ACLK_TOP_LOW_SEL_200M) + rate = 200 * MHz; + else + rate = OSC_HZ; + break; + case HCLK_TOP: + con = readl(&cru->clksel_con[73]); + sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT; + if (sel == HCLK_TOP_SEL_150M) + rate = 150 * MHz; + else if (sel == HCLK_TOP_SEL_100M) + rate = 100 * MHz; + else if (sel == HCLK_TOP_SEL_75M) + rate = 75 * MHz; + else + rate = OSC_HZ; + break; + case PCLK_TOP: + con = readl(&cru->clksel_con[73]); + sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT; + if (sel == PCLK_TOP_SEL_100M) + rate = 100 * MHz; + else if (sel == PCLK_TOP_SEL_75M) + rate = 75 * MHz; + else if (sel == PCLK_TOP_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3568_top_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (clk_id) { + case ACLK_TOP_HIGH: + if (rate == 500 * MHz) + src_clk = ACLK_TOP_HIGH_SEL_500M; + else if (rate == 400 * MHz) + src_clk = ACLK_TOP_HIGH_SEL_400M; + else if (rate == 300 * MHz) + src_clk = ACLK_TOP_HIGH_SEL_300M; + else + src_clk = ACLK_TOP_HIGH_SEL_24M; + rk_clrsetreg(&cru->clksel_con[73], + ACLK_TOP_HIGH_SEL_MASK, + src_clk << ACLK_TOP_HIGH_SEL_SHIFT); + break; + case ACLK_TOP_LOW: + if (rate == 400 * MHz) + src_clk = ACLK_TOP_LOW_SEL_400M; + else if (rate == 300 * MHz) + src_clk = ACLK_TOP_LOW_SEL_300M; + else if (rate == 200 * MHz) + src_clk = ACLK_TOP_LOW_SEL_200M; + else + src_clk = ACLK_TOP_LOW_SEL_24M; + rk_clrsetreg(&cru->clksel_con[73], + ACLK_TOP_LOW_SEL_MASK, + src_clk << ACLK_TOP_LOW_SEL_SHIFT); + break; + case HCLK_TOP: + if (rate == 150 * MHz) + src_clk = HCLK_TOP_SEL_150M; + else if (rate == 100 * MHz) + src_clk = HCLK_TOP_SEL_100M; + else if (rate == 75 * MHz) + src_clk = HCLK_TOP_SEL_75M; + else + src_clk = HCLK_TOP_SEL_24M; + rk_clrsetreg(&cru->clksel_con[73], + HCLK_TOP_SEL_MASK, + src_clk << HCLK_TOP_SEL_SHIFT); + break; + case PCLK_TOP: + if (rate == 100 * MHz) + src_clk = PCLK_TOP_SEL_100M; + else if (rate == 75 * MHz) + src_clk = PCLK_TOP_SEL_75M; + else if (rate == 50 * MHz) + src_clk = PCLK_TOP_SEL_50M; + else + src_clk = PCLK_TOP_SEL_24M; + rk_clrsetreg(&cru->clksel_con[73], + PCLK_TOP_SEL_MASK, + src_clk << PCLK_TOP_SEL_SHIFT); + break; + + default: + printf("do not support this permid freq\n"); + return -EINVAL; + } + + return rk3568_top_get_clk(priv, clk_id); +} + +static ulong rk3568_i2c_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + ulong rate; + + switch (clk_id) { + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + con = readl(&cru->clksel_con[71]); + sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT; + if (sel == CLK_I2C_SEL_200M) + rate = 200 * MHz; + else if (sel == CLK_I2C_SEL_100M) + rate = 100 * MHz; + else if (sel == CLK_I2C_SEL_CPLL_100M) + rate = 100 * MHz; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3568_i2c_set_clk(struct rk3568_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + if (rate == 200 * MHz) + src_clk = CLK_I2C_SEL_200M; + else if (rate == 100 * MHz) + src_clk = CLK_I2C_SEL_100M; + else + src_clk = CLK_I2C_SEL_24M; + + switch (clk_id) { + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + rk_clrsetreg(&cru->clksel_con[71], CLK_I2C_SEL_MASK, + src_clk << CLK_I2C_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3568_i2c_get_clk(priv, clk_id); +} + +static ulong rk3568_spi_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[72]); + + switch (clk_id) { + case CLK_SPI0: + sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; + break; + case CLK_SPI1: + sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; + break; + case CLK_SPI2: + sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT; + break; + case CLK_SPI3: + sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + switch (sel) { + case CLK_SPI_SEL_200M: + return 200 * MHz; + case CLK_SPI_SEL_24M: + return OSC_HZ; + case CLK_SPI_SEL_CPLL_100M: + return 100 * MHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_spi_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + if (rate == 200 * MHz) + src_clk = CLK_SPI_SEL_200M; + else if (rate == 100 * MHz) + src_clk = CLK_SPI_SEL_CPLL_100M; + else + src_clk = CLK_SPI_SEL_24M; + + switch (clk_id) { + case CLK_SPI0: + rk_clrsetreg(&cru->clksel_con[72], + CLK_SPI0_SEL_MASK, + src_clk << CLK_SPI0_SEL_SHIFT); + break; + case CLK_SPI1: + rk_clrsetreg(&cru->clksel_con[72], + CLK_SPI1_SEL_MASK, + src_clk << CLK_SPI1_SEL_SHIFT); + break; + case CLK_SPI2: + rk_clrsetreg(&cru->clksel_con[72], + CLK_SPI2_SEL_MASK, + src_clk << CLK_SPI2_SEL_SHIFT); + break; + case CLK_SPI3: + rk_clrsetreg(&cru->clksel_con[72], + CLK_SPI3_SEL_MASK, + src_clk << CLK_SPI3_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3568_spi_get_clk(priv, clk_id); +} + +static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[72]); + + switch (clk_id) { + case CLK_PWM1: + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; + break; + case CLK_PWM2: + sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; + break; + case CLK_PWM3: + sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + switch (sel) { + case CLK_PWM_SEL_100M: + return 100 * MHz; + case CLK_PWM_SEL_24M: + return OSC_HZ; + case CLK_PWM_SEL_CPLL_100M: + return 100 * MHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_pwm_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + if (rate == 100 * MHz) + src_clk = CLK_PWM_SEL_100M; + else + src_clk = CLK_PWM_SEL_24M; + + switch (clk_id) { + case CLK_PWM1: + rk_clrsetreg(&cru->clksel_con[72], + CLK_PWM1_SEL_MASK, + src_clk << CLK_PWM1_SEL_SHIFT); + break; + case CLK_PWM2: + rk_clrsetreg(&cru->clksel_con[72], + CLK_PWM2_SEL_MASK, + src_clk << CLK_PWM2_SEL_SHIFT); + break; + case CLK_PWM3: + rk_clrsetreg(&cru->clksel_con[72], + CLK_PWM3_SEL_MASK, + src_clk << CLK_PWM3_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3568_pwm_get_clk(priv, clk_id); +} + +static ulong rk3568_adc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 div, sel, con, prate; + + switch (clk_id) { + case CLK_SARADC: + return OSC_HZ; + case CLK_TSADC_TSEN: + con = readl(&cru->clksel_con[51]); + div = (con & CLK_TSADC_TSEN_DIV_MASK) >> + CLK_TSADC_TSEN_DIV_SHIFT; + sel = (con & CLK_TSADC_TSEN_SEL_MASK) >> + CLK_TSADC_TSEN_SEL_SHIFT; + if (sel == CLK_TSADC_TSEN_SEL_24M) + prate = OSC_HZ; + else + prate = 100 * MHz; + return DIV_TO_RATE(prate, div); + case CLK_TSADC: + con = readl(&cru->clksel_con[51]); + div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT; + prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN); + return DIV_TO_RATE(prate, div); + default: + return -ENOENT; + } +} + +static ulong rk3568_adc_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk_div; + ulong prate = 0; + + switch (clk_id) { + case CLK_SARADC: + return OSC_HZ; + case CLK_TSADC_TSEN: + if (!(OSC_HZ % rate)) { + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); + assert(src_clk_div - 1 <= 7); + rk_clrsetreg(&cru->clksel_con[51], + CLK_TSADC_TSEN_SEL_MASK | + CLK_TSADC_TSEN_DIV_MASK, + (CLK_TSADC_TSEN_SEL_24M << + CLK_TSADC_TSEN_SEL_SHIFT) | + (src_clk_div - 1) << + CLK_TSADC_TSEN_DIV_SHIFT); + } else { + src_clk_div = DIV_ROUND_UP(100 * MHz, rate); + assert(src_clk_div - 1 <= 7); + rk_clrsetreg(&cru->clksel_con[51], + CLK_TSADC_TSEN_SEL_MASK | + CLK_TSADC_TSEN_DIV_MASK, + (CLK_TSADC_TSEN_SEL_100M << + CLK_TSADC_TSEN_SEL_SHIFT) | + (src_clk_div - 1) << + CLK_TSADC_TSEN_DIV_SHIFT); + } + break; + case CLK_TSADC: + prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN); + src_clk_div = DIV_ROUND_UP(prate, rate); + assert(src_clk_div - 1 <= 128); + rk_clrsetreg(&cru->clksel_con[51], + CLK_TSADC_DIV_MASK, + (src_clk_div - 1) << CLK_TSADC_DIV_SHIFT); + break; + default: + return -ENOENT; + } + return rk3568_adc_get_clk(priv, clk_id); +} + +static ulong rk3568_crypto_get_rate(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + switch (clk_id) { + case ACLK_SECURE_FLASH: + case ACLK_CRYPTO_NS: + con = readl(&cru->clksel_con[27]); + sel = (con & ACLK_SECURE_FLASH_SEL_MASK) >> + ACLK_SECURE_FLASH_SEL_SHIFT; + if (sel == ACLK_SECURE_FLASH_SEL_200M) + return 200 * MHz; + else if (sel == ACLK_SECURE_FLASH_SEL_150M) + return 150 * MHz; + else if (sel == ACLK_SECURE_FLASH_SEL_100M) + return 100 * MHz; + else + return 24 * MHz; + case HCLK_SECURE_FLASH: + case HCLK_CRYPTO_NS: + case CLK_CRYPTO_NS_RNG: + con = readl(&cru->clksel_con[27]); + sel = (con & HCLK_SECURE_FLASH_SEL_MASK) >> + HCLK_SECURE_FLASH_SEL_SHIFT; + if (sel == HCLK_SECURE_FLASH_SEL_150M) + return 150 * MHz; + else if (sel == HCLK_SECURE_FLASH_SEL_100M) + return 100 * MHz; + else if (sel == HCLK_SECURE_FLASH_SEL_75M) + return 75 * MHz; + else + return 24 * MHz; + case CLK_CRYPTO_NS_CORE: + con = readl(&cru->clksel_con[27]); + sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >> + CLK_CRYPTO_CORE_SEL_SHIFT; + if (sel == CLK_CRYPTO_CORE_SEL_200M) + return 200 * MHz; + else if (sel == CLK_CRYPTO_CORE_SEL_150M) + return 150 * MHz; + else + return 100 * MHz; + case CLK_CRYPTO_NS_PKA: + con = readl(&cru->clksel_con[27]); + sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >> + CLK_CRYPTO_PKA_SEL_SHIFT; + if (sel == CLK_CRYPTO_PKA_SEL_300M) + return 300 * MHz; + else if (sel == CLK_CRYPTO_PKA_SEL_200M) + return 200 * MHz; + else + return 100 * MHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_crypto_set_rate(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + u32 src_clk, mask, shift; + + switch (clk_id) { + case ACLK_SECURE_FLASH: + case ACLK_CRYPTO_NS: + mask = ACLK_SECURE_FLASH_SEL_MASK; + shift = ACLK_SECURE_FLASH_SEL_SHIFT; + if (rate == 200 * MHz) + src_clk = ACLK_SECURE_FLASH_SEL_200M; + else if (rate == 150 * MHz) + src_clk = ACLK_SECURE_FLASH_SEL_150M; + else if (rate == 100 * MHz) + src_clk = ACLK_SECURE_FLASH_SEL_100M; + else + src_clk = ACLK_SECURE_FLASH_SEL_24M; + break; + case HCLK_SECURE_FLASH: + case HCLK_CRYPTO_NS: + case CLK_CRYPTO_NS_RNG: + mask = HCLK_SECURE_FLASH_SEL_MASK; + shift = HCLK_SECURE_FLASH_SEL_SHIFT; + if (rate == 150 * MHz) + src_clk = HCLK_SECURE_FLASH_SEL_150M; + else if (rate == 100 * MHz) + src_clk = HCLK_SECURE_FLASH_SEL_100M; + else if (rate == 75 * MHz) + src_clk = HCLK_SECURE_FLASH_SEL_75M; + else + src_clk = HCLK_SECURE_FLASH_SEL_24M; + break; + case CLK_CRYPTO_NS_CORE: + mask = CLK_CRYPTO_CORE_SEL_MASK; + shift = CLK_CRYPTO_CORE_SEL_SHIFT; + if (rate == 200 * MHz) + src_clk = CLK_CRYPTO_CORE_SEL_200M; + else if (rate == 150 * MHz) + src_clk = CLK_CRYPTO_CORE_SEL_150M; + else + src_clk = CLK_CRYPTO_CORE_SEL_100M; + break; + case CLK_CRYPTO_NS_PKA: + mask = CLK_CRYPTO_PKA_SEL_MASK; + shift = CLK_CRYPTO_PKA_SEL_SHIFT; + if (rate == 300 * MHz) + src_clk = CLK_CRYPTO_PKA_SEL_300M; + else if (rate == 200 * MHz) + src_clk = CLK_CRYPTO_PKA_SEL_200M; + else + src_clk = CLK_CRYPTO_PKA_SEL_100M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[27], mask, src_clk << shift); + + return rk3568_crypto_get_rate(priv, clk_id); +} + +static ulong rk3568_sdmmc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + switch (clk_id) { + case HCLK_SDMMC0: + case CLK_SDMMC0: + con = readl(&cru->clksel_con[30]); + sel = (con & CLK_SDMMC0_SEL_MASK) >> CLK_SDMMC0_SEL_SHIFT; + break; + case CLK_SDMMC1: + con = readl(&cru->clksel_con[30]); + sel = (con & CLK_SDMMC1_SEL_MASK) >> CLK_SDMMC1_SEL_SHIFT; + break; + case CLK_SDMMC2: + con = readl(&cru->clksel_con[32]); + sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT; + break; + default: + return -ENOENT; + } + + switch (sel) { + case CLK_SDMMC_SEL_24M: + return OSC_HZ; + case CLK_SDMMC_SEL_400M: + return 400 * MHz; + case CLK_SDMMC_SEL_300M: + return 300 * MHz; + case CLK_SDMMC_SEL_100M: + return 100 * MHz; + case CLK_SDMMC_SEL_50M: + return 50 * MHz; + case CLK_SDMMC_SEL_750K: + return 750 * KHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case OSC_HZ: + src_clk = CLK_SDMMC_SEL_24M; + break; + case 400 * MHz: + src_clk = CLK_SDMMC_SEL_400M; + break; + case 300 * MHz: + src_clk = CLK_SDMMC_SEL_300M; + break; + case 100 * MHz: + src_clk = CLK_SDMMC_SEL_100M; + break; + case 52 * MHz: + case 50 * MHz: + src_clk = CLK_SDMMC_SEL_50M; + break; + case 750 * KHz: + case 400 * KHz: + src_clk = CLK_SDMMC_SEL_750K; + break; + default: + return -ENOENT; + } + + switch (clk_id) { + case HCLK_SDMMC0: + case CLK_SDMMC0: + rk_clrsetreg(&cru->clksel_con[30], + CLK_SDMMC0_SEL_MASK, + src_clk << CLK_SDMMC0_SEL_SHIFT); + break; + case CLK_SDMMC1: + rk_clrsetreg(&cru->clksel_con[30], + CLK_SDMMC1_SEL_MASK, + src_clk << CLK_SDMMC1_SEL_SHIFT); + break; + case CLK_SDMMC2: + rk_clrsetreg(&cru->clksel_con[32], + CLK_SDMMC2_SEL_MASK, + src_clk << CLK_SDMMC2_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3568_sdmmc_get_clk(priv, clk_id); +} + +static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[28]); + sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT; + switch (sel) { + case SCLK_SFC_SEL_24M: + return OSC_HZ; + case SCLK_SFC_SEL_50M: + return 50 * MHz; + case SCLK_SFC_SEL_75M: + return 75 * MHz; + case SCLK_SFC_SEL_100M: + return 100 * MHz; + case SCLK_SFC_SEL_125M: + return 125 * MHz; + case SCLK_SFC_SEL_150M: + return 150 * KHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case OSC_HZ: + src_clk = SCLK_SFC_SEL_24M; + break; + case 50 * MHz: + src_clk = SCLK_SFC_SEL_50M; + break; + case 75 * MHz: + src_clk = SCLK_SFC_SEL_75M; + break; + case 100 * MHz: + src_clk = SCLK_SFC_SEL_100M; + break; + case 125 * MHz: + src_clk = SCLK_SFC_SEL_125M; + break; + case 150 * KHz: + src_clk = SCLK_SFC_SEL_150M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[28], + SCLK_SFC_SEL_MASK, + src_clk << SCLK_SFC_SEL_SHIFT); + + return rk3568_sfc_get_clk(priv); +} + +static ulong rk3568_nand_get_clk(struct rk3568_clk_priv *priv) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[28]); + sel = (con & NCLK_NANDC_SEL_MASK) >> NCLK_NANDC_SEL_SHIFT; + switch (sel) { + case NCLK_NANDC_SEL_200M: + return 200 * MHz; + case NCLK_NANDC_SEL_150M: + return 150 * MHz; + case NCLK_NANDC_SEL_100M: + return 100 * MHz; + case NCLK_NANDC_SEL_24M: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3568_nand_set_clk(struct rk3568_clk_priv *priv, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case OSC_HZ: + src_clk = NCLK_NANDC_SEL_24M; + break; + case 100 * MHz: + src_clk = NCLK_NANDC_SEL_100M; + break; + case 150 * MHz: + src_clk = NCLK_NANDC_SEL_150M; + break; + case 200 * MHz: + src_clk = NCLK_NANDC_SEL_200M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[28], + NCLK_NANDC_SEL_MASK, + src_clk << NCLK_NANDC_SEL_SHIFT); + + return rk3568_nand_get_clk(priv); +} + +static ulong rk3568_emmc_get_clk(struct rk3568_clk_priv *priv) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[28]); + sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT; + switch (sel) { + case CCLK_EMMC_SEL_200M: + return 200 * MHz; + case CCLK_EMMC_SEL_150M: + return 150 * MHz; + case CCLK_EMMC_SEL_100M: + return 100 * MHz; + case CCLK_EMMC_SEL_50M: + return 50 * MHz; + case CCLK_EMMC_SEL_375K: + return 375 * KHz; + case CCLK_EMMC_SEL_24M: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case OSC_HZ: + src_clk = CCLK_EMMC_SEL_24M; + break; + case 52 * MHz: + case 50 * MHz: + src_clk = CCLK_EMMC_SEL_50M; + break; + case 100 * MHz: + src_clk = CCLK_EMMC_SEL_100M; + break; + case 150 * MHz: + src_clk = CCLK_EMMC_SEL_150M; + break; + case 200 * MHz: + src_clk = CCLK_EMMC_SEL_200M; + break; + case 400 * KHz: + case 375 * KHz: + src_clk = CCLK_EMMC_SEL_375K; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[28], + CCLK_EMMC_SEL_MASK, + src_clk << CCLK_EMMC_SEL_SHIFT); + + return rk3568_emmc_get_clk(priv); +} + +static ulong rk3568_emmc_get_bclk(struct rk3568_clk_priv *priv) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[28]); + sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT; + switch (sel) { + case BCLK_EMMC_SEL_200M: + return 200 * MHz; + case BCLK_EMMC_SEL_150M: + return 150 * MHz; + case BCLK_EMMC_SEL_125M: + return 125 * MHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case 200 * MHz: + src_clk = BCLK_EMMC_SEL_200M; + break; + case 150 * MHz: + src_clk = BCLK_EMMC_SEL_150M; + break; + case 125 * MHz: + src_clk = BCLK_EMMC_SEL_125M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[28], + BCLK_EMMC_SEL_MASK, + src_clk << BCLK_EMMC_SEL_SHIFT); + + return rk3568_emmc_get_bclk(priv); +} + +#ifndef CONFIG_SPL_BUILD +static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv) +{ + struct rk3568_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[38]); + div = (con & ACLK_VOP_PRE_DIV_MASK) >> ACLK_VOP_PRE_DIV_SHIFT; + sel = (con & ACLK_VOP_PRE_SEL_MASK) >> ACLK_VOP_PRE_SEL_SHIFT; + if (sel == ACLK_VOP_PRE_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_VOP_PRE_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == ACLK_VOP_PRE_SEL_VPLL) + parent = priv->vpll_hz; + else + parent = priv->hpll_hz; + + return DIV_TO_RATE(parent, div); +} + +static ulong rk3568_aclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk_div, src_clk_mux; + + if ((priv->cpll_hz % rate) == 0) { + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + src_clk_mux = ACLK_VOP_PRE_SEL_CPLL; + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + src_clk_mux = ACLK_VOP_PRE_SEL_GPLL; + } + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[38], + ACLK_VOP_PRE_SEL_MASK | ACLK_VOP_PRE_DIV_MASK, + src_clk_mux << ACLK_VOP_PRE_SEL_SHIFT | + (src_clk_div - 1) << ACLK_VOP_PRE_DIV_SHIFT); + + return rk3568_aclk_vop_get_clk(priv); +} + +static ulong rk3568_dclk_vop_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 conid, div, sel, con, parent; + + switch (clk_id) { + case DCLK_VOP0: + conid = 39; + break; + case DCLK_VOP1: + conid = 40; + break; + case DCLK_VOP2: + conid = 41; + break; + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[conid]); + div = (con & DCLK0_VOP_DIV_MASK) >> DCLK0_VOP_DIV_SHIFT; + sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT; + if (sel == DCLK_VOP_SEL_HPLL) + parent = rk3568_pmu_pll_get_rate(priv, HPLL); + else if (sel == DCLK_VOP_SEL_VPLL) + parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], + priv->cru, VPLL); + else if (sel == DCLK_VOP_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_VOP_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +#define RK3568_VOP_PLL_LIMIT_FREQ 600000000 + +static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + ulong pll_rate, now, best_rate = 0; + u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; + + switch (clk_id) { + case DCLK_VOP0: + conid = 39; + break; + case DCLK_VOP1: + conid = 40; + break; + case DCLK_VOP2: + conid = 41; + break; + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[conid]); + sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT; + + if (sel == DCLK_VOP_SEL_HPLL) { + div = 1; + rk_clrsetreg(&cru->clksel_con[conid], + DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK, + (DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT) | + ((div - 1) << DCLK0_VOP_DIV_SHIFT)); + rk3568_pmu_pll_set_rate(priv, HPLL, div * rate); + } else if (sel == DCLK_VOP_SEL_VPLL) { + div = DIV_ROUND_UP(RK3568_VOP_PLL_LIMIT_FREQ, rate); + rk_clrsetreg(&cru->clksel_con[conid], + DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK, + (DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT) | + ((div - 1) << DCLK0_VOP_DIV_SHIFT)); + rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], + priv->cru, VPLL, div * rate); + } else { + for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { + switch (i) { + case DCLK_VOP_SEL_GPLL: + pll_rate = priv->gpll_hz; + break; + case DCLK_VOP_SEL_CPLL: + pll_rate = priv->cpll_hz; + break; + default: + printf("do not support this vop pll sel\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(pll_rate, rate); + if (div > 255) + continue; + now = pll_rate / div; + if (abs(rate - now) < abs(rate - best_rate)) { + best_rate = now; + best_div = div; + best_sel = i; + } + debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n", + pll_rate, best_rate, best_div, best_sel); + } + + if (best_rate) { + rk_clrsetreg(&cru->clksel_con[conid], + DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK, + best_sel << DCLK0_VOP_SEL_SHIFT | + (best_div - 1) << DCLK0_VOP_DIV_SHIFT); + } else { + printf("do not support this vop freq %lu\n", rate); + return -EINVAL; + } + } + return rk3568_dclk_vop_get_clk(priv, clk_id); +} + +static ulong rk3568_gmac_src_get_clk(struct rk3568_clk_priv *priv, + ulong mac_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[31 + mac_id * 2]); + sel = (con & CLK_MAC0_2TOP_SEL_MASK) >> CLK_MAC0_2TOP_SEL_SHIFT; + + switch (sel) { + case CLK_MAC0_2TOP_SEL_125M: + return 125 * MHz; + case CLK_MAC0_2TOP_SEL_50M: + return 50 * MHz; + case CLK_MAC0_2TOP_SEL_25M: + return 25 * MHz; + case CLK_MAC0_2TOP_SEL_PPLL: + return rk3568_pmu_pll_get_rate(priv, HPLL); + default: + return -ENOENT; + } +} + +static ulong rk3568_gmac_src_set_clk(struct rk3568_clk_priv *priv, + ulong mac_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case 125 * MHz: + src_clk = CLK_MAC0_2TOP_SEL_125M; + break; + case 50 * MHz: + src_clk = CLK_MAC0_2TOP_SEL_50M; + break; + case 25 * MHz: + src_clk = CLK_MAC0_2TOP_SEL_25M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2], + CLK_MAC0_2TOP_SEL_MASK, + src_clk << CLK_MAC0_2TOP_SEL_SHIFT); + + return rk3568_gmac_src_get_clk(priv, mac_id); +} + +static ulong rk3568_gmac_out_get_clk(struct rk3568_clk_priv *priv, + ulong mac_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[31 + mac_id * 2]); + sel = (con & CLK_MAC0_OUT_SEL_MASK) >> CLK_MAC0_OUT_SEL_SHIFT; + + switch (sel) { + case CLK_MAC0_OUT_SEL_125M: + return 125 * MHz; + case CLK_MAC0_OUT_SEL_50M: + return 50 * MHz; + case CLK_MAC0_OUT_SEL_25M: + return 25 * MHz; + case CLK_MAC0_OUT_SEL_24M: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3568_gmac_out_set_clk(struct rk3568_clk_priv *priv, + ulong mac_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case 125 * MHz: + src_clk = CLK_MAC0_OUT_SEL_125M; + break; + case 50 * MHz: + src_clk = CLK_MAC0_OUT_SEL_50M; + break; + case 25 * MHz: + src_clk = CLK_MAC0_OUT_SEL_25M; + break; + case 24 * MHz: + src_clk = CLK_MAC0_OUT_SEL_24M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2], + CLK_MAC0_OUT_SEL_MASK, + src_clk << CLK_MAC0_OUT_SEL_SHIFT); + + return rk3568_gmac_out_get_clk(priv, mac_id); +} + +static ulong rk3568_gmac_ptp_ref_get_clk(struct rk3568_clk_priv *priv, + ulong mac_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 sel, con; + + con = readl(&cru->clksel_con[31 + mac_id * 2]); + sel = (con & CLK_GMAC0_PTP_REF_SEL_MASK) >> CLK_GMAC0_PTP_REF_SEL_SHIFT; + + switch (sel) { + case CLK_GMAC0_PTP_REF_SEL_62_5M: + return 62500 * KHz; + case CLK_GMAC0_PTP_REF_SEL_100M: + return 100 * MHz; + case CLK_GMAC0_PTP_REF_SEL_50M: + return 50 * MHz; + case CLK_GMAC0_PTP_REF_SEL_24M: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3568_gmac_ptp_ref_set_clk(struct rk3568_clk_priv *priv, + ulong mac_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk; + + switch (rate) { + case 62500 * KHz: + src_clk = CLK_GMAC0_PTP_REF_SEL_62_5M; + break; + case 100 * MHz: + src_clk = CLK_GMAC0_PTP_REF_SEL_100M; + break; + case 50 * MHz: + src_clk = CLK_GMAC0_PTP_REF_SEL_50M; + break; + case 24 * MHz: + src_clk = CLK_GMAC0_PTP_REF_SEL_24M; + break; + default: + return -ENOENT; + } + + rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2], + CLK_GMAC0_PTP_REF_SEL_MASK, + src_clk << CLK_GMAC0_PTP_REF_SEL_SHIFT); + + return rk3568_gmac_ptp_ref_get_clk(priv, mac_id); +} + +static ulong rk3568_gmac_tx_rx_set_clk(struct rk3568_clk_priv *priv, + ulong mac_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + u32 con, sel, div_sel; + + con = readl(&cru->clksel_con[31 + mac_id * 2]); + sel = (con & RMII0_MODE_MASK) >> RMII0_MODE_SHIFT; + + if (sel == RMII0_MODE_SEL_RGMII) { + if (rate == 2500000) + div_sel = RGMII0_CLK_SEL_2_5M; + else if (rate == 25000000) + div_sel = RGMII0_CLK_SEL_25M; + else + div_sel = RGMII0_CLK_SEL_125M; + rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2], + RGMII0_CLK_SEL_MASK, + div_sel << RGMII0_CLK_SEL_SHIFT); + } else if (sel == RMII0_MODE_SEL_RMII) { + if (rate == 2500000) + div_sel = RMII0_CLK_SEL_2_5M; + else + div_sel = RMII0_CLK_SEL_25M; + rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2], + RMII0_CLK_SEL_MASK, + div_sel << RMII0_CLK_SEL_SHIFT); + } + + return 0; +} + +static ulong rk3568_ebc_get_clk(struct rk3568_clk_priv *priv) +{ + struct rk3568_cru *cru = priv->cru; + u32 con, div, p_rate; + + con = readl(&cru->clksel_con[79]); + div = (con & CPLL_333M_DIV_MASK) >> CPLL_333M_DIV_SHIFT; + p_rate = DIV_TO_RATE(priv->cpll_hz, div); + + con = readl(&cru->clksel_con[43]); + div = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; + switch (div) { + case DCLK_EBC_SEL_GPLL_400M: + return 400 * MHz; + case DCLK_EBC_SEL_CPLL_333M: + return p_rate; + case DCLK_EBC_SEL_GPLL_200M: + return 200 * MHz; + default: + return -ENOENT; + } +} + +static ulong rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[79], + CPLL_333M_DIV_MASK, + (src_clk_div - 1) << CPLL_333M_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[43], + DCLK_EBC_SEL_MASK, + DCLK_EBC_SEL_CPLL_333M << DCLK_EBC_SEL_SHIFT); + + return rk3568_ebc_get_clk(priv); +} + +static ulong rk3568_rkvdec_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 con, div, src, p_rate; + + switch (clk_id) { + case ACLK_RKVDEC_PRE: + case ACLK_RKVDEC: + con = readl(&cru->clksel_con[47]); + src = (con & ACLK_RKVDEC_SEL_MASK) >> ACLK_RKVDEC_SEL_SHIFT; + div = (con & ACLK_RKVDEC_DIV_MASK) >> ACLK_RKVDEC_DIV_SHIFT; + if (src == ACLK_RKVDEC_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = priv->gpll_hz; + return DIV_TO_RATE(p_rate, div); + case CLK_RKVDEC_CORE: + con = readl(&cru->clksel_con[49]); + src = (con & CLK_RKVDEC_CORE_SEL_MASK) + >> CLK_RKVDEC_CORE_SEL_SHIFT; + div = (con & CLK_RKVDEC_CORE_DIV_MASK) + >> CLK_RKVDEC_CORE_DIV_SHIFT; + if (src == CLK_RKVDEC_CORE_SEL_CPLL) + p_rate = priv->cpll_hz; + else if (src == CLK_RKVDEC_CORE_SEL_NPLL) + p_rate = priv->npll_hz; + else if (src == CLK_RKVDEC_CORE_SEL_VPLL) + p_rate = priv->vpll_hz; + else + p_rate = priv->gpll_hz; + return DIV_TO_RATE(p_rate, div); + default: + return -ENOENT; + } +} + +static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + int src_clk_div, src, p_rate; + + switch (clk_id) { + case ACLK_RKVDEC_PRE: + case ACLK_RKVDEC: + src = (readl(&cru->clksel_con[47]) & ACLK_RKVDEC_SEL_MASK) + >> ACLK_RKVDEC_SEL_SHIFT; + if (src == ACLK_RKVDEC_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = priv->gpll_hz; + src_clk_div = DIV_ROUND_UP(p_rate, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[47], + ACLK_RKVDEC_SEL_MASK | + ACLK_RKVDEC_DIV_MASK, + (src << ACLK_RKVDEC_SEL_SHIFT) | + (src_clk_div - 1) << ACLK_RKVDEC_DIV_SHIFT); + break; + case CLK_RKVDEC_CORE: + src = (readl(&cru->clksel_con[49]) & CLK_RKVDEC_CORE_SEL_MASK) + >> CLK_RKVDEC_CORE_SEL_SHIFT; + if (src == CLK_RKVDEC_CORE_SEL_CPLL) + p_rate = priv->cpll_hz; + else if (src == CLK_RKVDEC_CORE_SEL_NPLL) + p_rate = priv->npll_hz; + else if (src == CLK_RKVDEC_CORE_SEL_VPLL) + p_rate = priv->vpll_hz; + else + p_rate = priv->gpll_hz; + src_clk_div = DIV_ROUND_UP(p_rate, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[49], + CLK_RKVDEC_CORE_SEL_MASK | + CLK_RKVDEC_CORE_DIV_MASK, + (src << CLK_RKVDEC_CORE_SEL_SHIFT) | + (src_clk_div - 1) << CLK_RKVDEC_CORE_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3568_rkvdec_get_clk(priv, clk_id); +} + +static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id) +{ + struct rk3568_cru *cru = priv->cru; + u32 reg, con, fracdiv, div, src, p_src, p_rate; + unsigned long m, n; + + switch (clk_id) { + case SCLK_UART1: + reg = 52; + break; + case SCLK_UART2: + reg = 54; + break; + case SCLK_UART3: + reg = 56; + break; + case SCLK_UART4: + reg = 58; + break; + case SCLK_UART5: + reg = 60; + break; + case SCLK_UART6: + reg = 62; + break; + case SCLK_UART7: + reg = 64; + break; + case SCLK_UART8: + reg = 66; + break; + case SCLK_UART9: + reg = 68; + break; + default: + return -ENOENT; + } + con = readl(&cru->clksel_con[reg]); + src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT; + div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT; + p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT; + if (p_src == CLK_UART_SRC_SEL_GPLL) + p_rate = priv->gpll_hz; + else if (p_src == CLK_UART_SRC_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = 480000000; + if (src == CLK_UART_SEL_SRC) { + return DIV_TO_RATE(p_rate, div); + } else if (src == CLK_UART_SEL_FRAC) { + fracdiv = readl(&cru->clksel_con[reg + 1]); + n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK; + n >>= CLK_UART_FRAC_NUMERATOR_SHIFT; + m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK; + m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT; + return DIV_TO_RATE(p_rate, div) * n / m; + } else { + return OSC_HZ; + } +} + +static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rk3568_cru *cru = priv->cru; + u32 reg, clk_src, uart_src, div; + unsigned long m = 0, n = 0, val; + + if (priv->gpll_hz % rate == 0) { + clk_src = CLK_UART_SRC_SEL_GPLL; + uart_src = CLK_UART_SEL_SRC; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } else if (priv->cpll_hz % rate == 0) { + clk_src = CLK_UART_SRC_SEL_CPLL; + uart_src = CLK_UART_SEL_SRC; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } else if (rate == OSC_HZ) { + clk_src = CLK_UART_SRC_SEL_GPLL; + uart_src = CLK_UART_SEL_XIN24M; + div = 2; + } else { + clk_src = CLK_UART_SRC_SEL_GPLL; + uart_src = CLK_UART_SEL_FRAC; + div = 2; + rational_best_approximation(rate, priv->gpll_hz / div, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + } + + switch (clk_id) { + case SCLK_UART1: + reg = 52; + break; + case SCLK_UART2: + reg = 54; + break; + case SCLK_UART3: + reg = 56; + break; + case SCLK_UART4: + reg = 58; + break; + case SCLK_UART5: + reg = 60; + break; + case SCLK_UART6: + reg = 62; + break; + case SCLK_UART7: + reg = 64; + break; + case SCLK_UART8: + reg = 66; + break; + case SCLK_UART9: + reg = 68; + break; + default: + return -ENOENT; + } + rk_clrsetreg(&cru->clksel_con[reg], + CLK_UART_SEL_MASK | CLK_UART_SRC_SEL_MASK | + CLK_UART_SRC_DIV_MASK, + (clk_src << CLK_UART_SRC_SEL_SHIFT) | + (uart_src << CLK_UART_SEL_SHIFT) | + ((div - 1) << CLK_UART_SRC_DIV_SHIFT)); + if (m && n) { + val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n; + writel(val, &cru->clksel_con[reg + 1]); + } + + return rk3568_uart_get_rate(priv, clk_id); +} +#endif + +static ulong rk3568_clk_get_rate(struct clk *clk) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru, + APLL); + break; + case PLL_CPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, + CPLL); + break; + case PLL_GPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru, + GPLL); + break; + case PLL_NPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru, + NPLL); + break; + case PLL_VPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru, + VPLL); + break; + case PLL_DPLL: + rate = rockchip_pll_get_rate(&rk3568_pll_clks[DPLL], priv->cru, + DPLL); + break; + case ACLK_BUS: + case PCLK_BUS: + case PCLK_WDT_NS: + rate = rk3568_bus_get_clk(priv, clk->id); + break; + case ACLK_PERIMID: + case HCLK_PERIMID: + rate = rk3568_perimid_get_clk(priv, clk->id); + break; + case ACLK_TOP_HIGH: + case ACLK_TOP_LOW: + case HCLK_TOP: + case PCLK_TOP: + rate = rk3568_top_get_clk(priv, clk->id); + break; + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + rate = rk3568_i2c_get_clk(priv, clk->id); + break; + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + rate = rk3568_spi_get_clk(priv, clk->id); + break; + case CLK_PWM1: + case CLK_PWM2: + case CLK_PWM3: + rate = rk3568_pwm_get_clk(priv, clk->id); + break; + case CLK_SARADC: + case CLK_TSADC_TSEN: + case CLK_TSADC: + rate = rk3568_adc_get_clk(priv, clk->id); + break; + case HCLK_SDMMC0: + case CLK_SDMMC0: + case CLK_SDMMC1: + case CLK_SDMMC2: + rate = rk3568_sdmmc_get_clk(priv, clk->id); + break; + case SCLK_SFC: + rate = rk3568_sfc_get_clk(priv); + break; + case NCLK_NANDC: + rate = rk3568_nand_get_clk(priv); + break; + case CCLK_EMMC: + rate = rk3568_emmc_get_clk(priv); + break; + case BCLK_EMMC: + rate = rk3568_emmc_get_bclk(priv); + break; +#ifndef CONFIG_SPL_BUILD + case ACLK_VOP: + rate = rk3568_aclk_vop_get_clk(priv); + break; + case DCLK_VOP0: + case DCLK_VOP1: + case DCLK_VOP2: + rate = rk3568_dclk_vop_get_clk(priv, clk->id); + break; + case SCLK_GMAC0: + case CLK_MAC0_2TOP: + case CLK_MAC0_REFOUT: + rate = rk3568_gmac_src_get_clk(priv, 0); + break; + case CLK_MAC0_OUT: + rate = rk3568_gmac_out_get_clk(priv, 0); + break; + case CLK_GMAC0_PTP_REF: + rate = rk3568_gmac_ptp_ref_get_clk(priv, 0); + break; + case SCLK_GMAC1: + case CLK_MAC1_2TOP: + case CLK_MAC1_REFOUT: + rate = rk3568_gmac_src_get_clk(priv, 1); + break; + case CLK_MAC1_OUT: + rate = rk3568_gmac_out_get_clk(priv, 1); + break; + case CLK_GMAC1_PTP_REF: + rate = rk3568_gmac_ptp_ref_get_clk(priv, 1); + break; + case DCLK_EBC: + rate = rk3568_ebc_get_clk(priv); + break; + case ACLK_RKVDEC_PRE: + case ACLK_RKVDEC: + case CLK_RKVDEC_CORE: + rate = rk3568_rkvdec_get_clk(priv, clk->id); + break; + case TCLK_WDT_NS: + rate = OSC_HZ; + break; + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + case SCLK_UART8: + case SCLK_UART9: + rate = rk3568_uart_get_rate(priv, clk->id); + break; +#endif + case ACLK_SECURE_FLASH: + case ACLK_CRYPTO_NS: + case HCLK_SECURE_FLASH: + case HCLK_CRYPTO_NS: + case CLK_CRYPTO_NS_RNG: + case CLK_CRYPTO_NS_CORE: + case CLK_CRYPTO_NS_PKA: + rate = rk3568_crypto_get_rate(priv, clk->id); + break; + case CPLL_500M: + case CPLL_333M: + case CPLL_250M: + case CPLL_125M: + case CPLL_100M: + case CPLL_62P5M: + case CPLL_50M: + case CPLL_25M: + rate = rk3568_cpll_div_get_rate(priv, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +}; + +static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + if (priv->armclk_hz) + rk3568_armclk_set_clk(priv, rate); + priv->armclk_hz = rate; + break; + case PLL_CPLL: + ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, + CPLL, rate); + priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], + priv->cru, CPLL); + break; + case PLL_GPLL: + ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru, + GPLL, rate); + priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], + priv->cru, GPLL); + break; + case PLL_NPLL: + ret = rockchip_pll_set_rate(&rk3568_pll_clks[NPLL], priv->cru, + NPLL, rate); + break; + case PLL_VPLL: + ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru, + VPLL, rate); + priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], + priv->cru, + VPLL); + break; + case ACLK_BUS: + case PCLK_BUS: + case PCLK_WDT_NS: + ret = rk3568_bus_set_clk(priv, clk->id, rate); + break; + case ACLK_PERIMID: + case HCLK_PERIMID: + ret = rk3568_perimid_set_clk(priv, clk->id, rate); + break; + case ACLK_TOP_HIGH: + case ACLK_TOP_LOW: + case HCLK_TOP: + case PCLK_TOP: + ret = rk3568_top_set_clk(priv, clk->id, rate); + break; + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + ret = rk3568_i2c_set_clk(priv, clk->id, rate); + break; + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + ret = rk3568_spi_set_clk(priv, clk->id, rate); + break; + case CLK_PWM1: + case CLK_PWM2: + case CLK_PWM3: + ret = rk3568_pwm_set_clk(priv, clk->id, rate); + break; + case CLK_SARADC: + case CLK_TSADC_TSEN: + case CLK_TSADC: + ret = rk3568_adc_set_clk(priv, clk->id, rate); + break; + case HCLK_SDMMC0: + case CLK_SDMMC0: + case CLK_SDMMC1: + case CLK_SDMMC2: + ret = rk3568_sdmmc_set_clk(priv, clk->id, rate); + break; + case SCLK_SFC: + ret = rk3568_sfc_set_clk(priv, rate); + break; + case NCLK_NANDC: + ret = rk3568_nand_set_clk(priv, rate); + break; + case CCLK_EMMC: + ret = rk3568_emmc_set_clk(priv, rate); + break; + case BCLK_EMMC: + ret = rk3568_emmc_set_bclk(priv, rate); + break; +#ifndef CONFIG_SPL_BUILD + case ACLK_VOP: + ret = rk3568_aclk_vop_set_clk(priv, rate); + break; + case DCLK_VOP0: + case DCLK_VOP1: + case DCLK_VOP2: + ret = rk3568_dclk_vop_set_clk(priv, clk->id, rate); + break; + case SCLK_GMAC0: + case CLK_MAC0_2TOP: + case CLK_MAC0_REFOUT: + ret = rk3568_gmac_src_set_clk(priv, 0, rate); + break; + case CLK_MAC0_OUT: + ret = rk3568_gmac_out_set_clk(priv, 0, rate); + break; + case SCLK_GMAC0_RX_TX: + ret = rk3568_gmac_tx_rx_set_clk(priv, 0, rate); + break; + case CLK_GMAC0_PTP_REF: + ret = rk3568_gmac_ptp_ref_set_clk(priv, 0, rate); + break; + case SCLK_GMAC1: + case CLK_MAC1_2TOP: + case CLK_MAC1_REFOUT: + ret = rk3568_gmac_src_set_clk(priv, 1, rate); + break; + case CLK_MAC1_OUT: + ret = rk3568_gmac_out_set_clk(priv, 1, rate); + break; + case SCLK_GMAC1_RX_TX: + ret = rk3568_gmac_tx_rx_set_clk(priv, 1, rate); + break; + case CLK_GMAC1_PTP_REF: + ret = rk3568_gmac_ptp_ref_set_clk(priv, 1, rate); + break; + case DCLK_EBC: + ret = rk3568_ebc_set_clk(priv, rate); + break; + case ACLK_RKVDEC_PRE: + case ACLK_RKVDEC: + case CLK_RKVDEC_CORE: + ret = rk3568_rkvdec_set_clk(priv, clk->id, rate); + break; + case TCLK_WDT_NS: + ret = OSC_HZ; + break; + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + case SCLK_UART8: + case SCLK_UART9: + ret = rk3568_uart_set_rate(priv, clk->id, rate); + break; +#endif + case ACLK_SECURE_FLASH: + case ACLK_CRYPTO_NS: + case HCLK_SECURE_FLASH: + case HCLK_CRYPTO_NS: + case CLK_CRYPTO_NS_RNG: + case CLK_CRYPTO_NS_CORE: + case CLK_CRYPTO_NS_PKA: + ret = rk3568_crypto_set_rate(priv, clk->id, rate); + break; + case CPLL_500M: + case CPLL_333M: + case CPLL_250M: + case CPLL_125M: + case CPLL_100M: + case CPLL_62P5M: + case CPLL_50M: + case CPLL_25M: + ret = rk3568_cpll_div_set_rate(priv, clk->id, rate); + break; + default: + return -ENOENT; + } + + return ret; +}; + +#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA)) +static int rk3568_gmac0_src_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_cru *cru = priv->cru; + + if (parent->id == CLK_MAC0_2TOP) + rk_clrsetreg(&cru->clksel_con[31], + RMII0_EXTCLK_SEL_MASK, + RMII0_EXTCLK_SEL_MAC0_TOP << + RMII0_EXTCLK_SEL_SHIFT); + else + rk_clrsetreg(&cru->clksel_con[31], + RMII0_EXTCLK_SEL_MASK, + RMII0_EXTCLK_SEL_IO << RMII0_EXTCLK_SEL_SHIFT); + return 0; +} + +static int rk3568_gmac1_src_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_cru *cru = priv->cru; + + if (parent->id == CLK_MAC1_2TOP) + rk_clrsetreg(&cru->clksel_con[33], + RMII0_EXTCLK_SEL_MASK, + RMII0_EXTCLK_SEL_MAC0_TOP << + RMII0_EXTCLK_SEL_SHIFT); + else + rk_clrsetreg(&cru->clksel_con[33], + RMII0_EXTCLK_SEL_MASK, + RMII0_EXTCLK_SEL_IO << RMII0_EXTCLK_SEL_SHIFT); + return 0; +} + +static int rk3568_gmac0_tx_rx_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_cru *cru = priv->cru; + + if (parent->id == SCLK_GMAC0_RGMII_SPEED) + rk_clrsetreg(&cru->clksel_con[31], + RMII0_MODE_MASK, + RMII0_MODE_SEL_RGMII << RMII0_MODE_SHIFT); + else if (parent->id == SCLK_GMAC0_RMII_SPEED) + rk_clrsetreg(&cru->clksel_con[31], + RMII0_MODE_MASK, + RMII0_MODE_SEL_RMII << RMII0_MODE_SHIFT); + else + rk_clrsetreg(&cru->clksel_con[31], + RMII0_MODE_MASK, + RMII0_MODE_SEL_GMII << RMII0_MODE_SHIFT); + + return 0; +} + +static int rk3568_gmac1_tx_rx_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_cru *cru = priv->cru; + + if (parent->id == SCLK_GMAC1_RGMII_SPEED) + rk_clrsetreg(&cru->clksel_con[33], + RMII0_MODE_MASK, + RMII0_MODE_SEL_RGMII << RMII0_MODE_SHIFT); + else if (parent->id == SCLK_GMAC1_RMII_SPEED) + rk_clrsetreg(&cru->clksel_con[33], + RMII0_MODE_MASK, + RMII0_MODE_SEL_RMII << RMII0_MODE_SHIFT); + else + rk_clrsetreg(&cru->clksel_con[33], + RMII0_MODE_MASK, + RMII0_MODE_SEL_GMII << RMII0_MODE_SHIFT); + + return 0; +} + +static int rk3568_dclk_vop_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_cru *cru = priv->cru; + u32 con_id; + + switch (clk->id) { + case DCLK_VOP0: + con_id = 39; + break; + case DCLK_VOP1: + con_id = 40; + break; + case DCLK_VOP2: + con_id = 41; + break; + default: + return -EINVAL; + } + if (parent->id == PLL_VPLL) { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT); + } + + return 0; +} + +static int rk3568_rkvdec_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3568_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3568_cru *cru = priv->cru; + u32 con_id, mask, shift; + + switch (clk->id) { + case ACLK_RKVDEC_PRE: + con_id = 47; + mask = ACLK_RKVDEC_SEL_MASK; + shift = ACLK_RKVDEC_SEL_SHIFT; + break; + case CLK_RKVDEC_CORE: + con_id = 49; + mask = CLK_RKVDEC_CORE_SEL_MASK; + shift = CLK_RKVDEC_CORE_SEL_SHIFT; + break; + default: + return -EINVAL; + } + if (parent->id == PLL_CPLL) { + rk_clrsetreg(&cru->clksel_con[con_id], mask, + ACLK_RKVDEC_SEL_CPLL << shift); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], mask, + ACLK_RKVDEC_SEL_GPLL << shift); + } + + return 0; +} + +static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case SCLK_GMAC0: + return rk3568_gmac0_src_set_parent(clk, parent); + case SCLK_GMAC1: + return rk3568_gmac1_src_set_parent(clk, parent); + case SCLK_GMAC0_RX_TX: + return rk3568_gmac0_tx_rx_set_parent(clk, parent); + case SCLK_GMAC1_RX_TX: + return rk3568_gmac1_tx_rx_set_parent(clk, parent); + case DCLK_VOP0: + case DCLK_VOP1: + case DCLK_VOP2: + return rk3568_dclk_vop_set_parent(clk, parent); + case ACLK_RKVDEC_PRE: + case CLK_RKVDEC_CORE: + return rk3568_rkvdec_set_parent(clk, parent); + default: + return -ENOENT; + } + + return 0; +} +#endif + +static struct clk_ops rk3568_clk_ops = { + .get_rate = rk3568_clk_get_rate, + .set_rate = rk3568_clk_set_rate, +#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA)) + .set_parent = rk3568_clk_set_parent, +#endif +}; + +static void rk3568_clk_init(struct rk3568_clk_priv *priv) +{ + int ret; + + priv->sync_kernel = false; + if (!priv->armclk_enter_hz) { + priv->armclk_enter_hz = + rockchip_pll_get_rate(&rk3568_pll_clks[APLL], + priv->cru, APLL); + priv->armclk_init_hz = priv->armclk_enter_hz; + } + + if (priv->armclk_init_hz != APLL_HZ) { + ret = rk3568_armclk_set_clk(priv, APLL_HZ); + if (!ret) + priv->armclk_init_hz = APLL_HZ; + } + if (priv->cpll_hz != CPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, + CPLL, CPLL_HZ); + if (!ret) + priv->cpll_hz = CPLL_HZ; + } + if (priv->gpll_hz != GPLL_HZ) { + ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru, + GPLL, GPLL_HZ); + if (!ret) + priv->gpll_hz = GPLL_HZ; + } + +#ifdef CONFIG_SPL_BUILD + ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000); + if (ret < 0) + printf("Fail to set the ACLK_BUS clock.\n"); +#endif + + priv->ppll_hz = rk3568_pmu_pll_get_rate(priv, PPLL); + priv->hpll_hz = rk3568_pmu_pll_get_rate(priv, HPLL); +} + +static int rk3568_clk_probe(struct udevice *dev) +{ + struct rk3568_clk_priv *priv = dev_get_priv(dev); + int ret; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + + rk3568_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + debug("%s clk_set_defaults failed %d\n", __func__, ret); + else + priv->sync_kernel = true; + + return 0; +} + +static int rk3568_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3568_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rk3568_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3568_cru, + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rk3568_cru, + glb_srsr_snd); + } + +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + ret = offsetof(struct rk3568_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 30); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + + return 0; +} + +static const struct udevice_id rk3568_clk_ids[] = { + { .compatible = "rockchip,rk3568-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3568_cru) = { + .name = "rockchip_rk3568_cru", + .id = UCLASS_CLK, + .of_match = rk3568_clk_ids, + .priv_auto = sizeof(struct rk3568_clk_priv), + .of_to_plat = rk3568_clk_ofdata_to_platdata, + .ops = &rk3568_clk_ops, + .bind = rk3568_clk_bind, + .probe = rk3568_clk_probe, +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .plat_auto = sizeof(struct rk3568_clk_plat), +#endif +}; From c52c362e6481e88c47ef5902fd5fa673b5e43aaa Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Wed, 26 May 2021 17:34:17 +0800 Subject: [PATCH 105/250] rk3399_common: setup fdtoverlay_addr_r value fdtoverlay (pxe_utils) require define fdtoverlay_addr_r env variable for example sunxi-common.h meson64.h already have it. Signed-off-by: Artem Lapkin Reviewed-by: Kever Yang --- include/configs/rk3399_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index b37ed5cce0a..6d710da901e 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -51,6 +51,7 @@ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x01f00000\0" \ + "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02080000\0" \ "ramdisk_addr_r=0x06000000\0" \ "kernel_comp_addr_r=0x08000000\0" \ From a4a9ce1660ddf48b1aaf251fefda02b97171d149 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 2 Jun 2021 15:58:22 +0800 Subject: [PATCH 106/250] arm: dts: Sync rockchip-pinconf.dtsi from kernel Sync from linux kernel: https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen Reviewed-by: Kever Yang --- arch/arm/dts/rockchip-pinconf.dtsi | 344 +++++++++++++++++++++++++++++ 1 file changed, 344 insertions(+) create mode 100644 arch/arm/dts/rockchip-pinconf.dtsi diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi new file mode 100644 index 00000000000..5c645437b50 --- /dev/null +++ b/arch/arm/dts/rockchip-pinconf.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; From 636ffbd25c88778417c9fa44223d226d0c0f132c Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 2 Jun 2021 15:58:23 +0800 Subject: [PATCH 107/250] arm: dts: rockchip: Add dts for rk3568 evb Add dts for rk3568 evb, sync from the linux kernel upstream list [0]. [0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 + arch/arm/dts/rk3568-evb-u-boot.dtsi | 23 + arch/arm/dts/rk3568-evb.dts | 79 + arch/arm/dts/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++++++++++++ arch/arm/dts/rk3568-u-boot.dtsi | 37 + arch/arm/dts/rk3568.dtsi | 779 +++++++ 6 files changed, 4032 insertions(+) create mode 100644 arch/arm/dts/rk3568-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-evb.dts create mode 100644 arch/arm/dts/rk3568-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261da..9918e466339 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -146,6 +146,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-rockpro64.dtb \ rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-evb.dtb + dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb-u-boot.dtsi new file mode 100644 index 00000000000..b03cbeaedf9 --- /dev/null +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include "rk3568-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; + }; +}; + +&sdmmc0 { + status = "okay"; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-spl; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts new file mode 100644 index 00000000000..69786557093 --- /dev/null +++ b/arch/arm/dts/rk3568-evb.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi new file mode 100644 index 00000000000..a588ca95ace --- /dev/null +++ b/arch/arm/dts/rk3568-pinctrl.dtsi @@ -0,0 +1,3111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi new file mode 100644 index 00000000000..1570f13fc77 --- /dev/null +++ b/arch/arm/dts/rk3568-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + dmc: dmc { + compatible = "rockchip,rk3568-dmc"; + u-boot,dm-pre-reloc; + status = "okay"; + }; +}; + +&cru { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmucru { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&grf { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi new file mode 100644 index 00000000000..12a071e6790 --- /dev/null +++ b/arch/arm/dts/rk3568.dtsi @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3568"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; + }; + + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-0 = <&clk32k_out0>; + pinctrl-names = "default"; + #clock-cells = <0>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0x80000>; /* GICR */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + mbi-alias = <0x0 0xfd100000>; + mbi-ranges = <296 24>; + msi-controller; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + interrupts = ; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-0 = <&uart0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm0: pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70000 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70010 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70020 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70030 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@fe600000 { + compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; + reg = <0x0 0xfe600000 0x0 0x100>; + interrupts = ; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-0 = <&uart1m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-0 = <&uart3m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-0 = <&uart4m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-0 = <&uart5m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-0 = <&uart8m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm4: pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@fe6e0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@fe700000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@fe700010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@fe700020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@fe700030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" From 2d46775287e3e421e5c1369ddc04626ccf52c23d Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 2 Jun 2021 15:58:24 +0800 Subject: [PATCH 108/250] rockchip: rk3568: Add sdram driver Add the driver for rk3568 u-boot to get sdram capacity. Signed-off-by: Joseph Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_rk3568.c | 56 +++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 drivers/ram/rockchip/sdram_rk3568.c diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index c3ec89ada4c..ca1c289b884 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -12,4 +12,5 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c new file mode 100644 index 00000000000..0ac4b54eef3 --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3568.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct dram_info { + struct ram_info info; + struct rk3568_pmugrf *pmugrf; +}; + +static int rk3568_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2); + + return 0; +} + +static int rk3568_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3568_dmc_ops = { + .get_info = rk3568_dmc_get_info, +}; + +static const struct udevice_id rk3568_dmc_ids[] = { + { .compatible = "rockchip,rk3568-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3568) = { + .name = "rockchip_rk3568_dmc", + .id = UCLASS_RAM, + .of_match = rk3568_dmc_ids, + .ops = &rk3568_dmc_ops, + .probe = rk3568_dmc_probe, + .priv_auto = sizeof(struct dram_info), +}; From 2a950e3ba5063a6c23bdcde2d5224ffb9abb5a93 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 2 Jun 2021 15:58:25 +0800 Subject: [PATCH 109/250] rockchip: Add rk3568 architecture core RK3568 is a high-performance and low power quad-core application processor designed for personal mobile internet device and AIoT equipments. Signed-off-by: Joseph Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rk3568/boot0.h | 11 + arch/arm/include/asm/arch-rk3568/gpio.h | 11 + .../include/asm/arch-rockchip/grf_rk3568.h | 369 ++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 17 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3568/Kconfig | 20 + arch/arm/mach-rockchip/rk3568/Makefile | 9 + arch/arm/mach-rockchip/rk3568/clk_rk3568.c | 53 +++ arch/arm/mach-rockchip/rk3568/rk3568.c | 85 ++++ arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 24 ++ include/configs/rk3568_common.h | 43 ++ 11 files changed, 643 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3568/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3568/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3568.h create mode 100644 arch/arm/mach-rockchip/rk3568/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3568/Makefile create mode 100644 arch/arm/mach-rockchip/rk3568/clk_rk3568.c create mode 100644 arch/arm/mach-rockchip/rk3568/rk3568.c create mode 100644 arch/arm/mach-rockchip/rk3568/syscon_rk3568.c create mode 100644 include/configs/rk3568_common.h diff --git a/arch/arm/include/asm/arch-rk3568/boot0.h b/arch/arm/include/asm/arch-rk3568/boot0.h new file mode 100644 index 00000000000..dea2b20252d --- /dev/null +++ b/arch/arm/include/asm/arch-rk3568/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3568/gpio.h b/arch/arm/include/asm/arch-rk3568/gpio.h new file mode 100644 index 00000000000..b48c0a5cf84 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3568/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3568.h b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h new file mode 100644 index 00000000000..d4e9b56292e --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h @@ -0,0 +1,369 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __SOC_ROCKCHIP_RK3568_GRF_H__ +#define __SOC_ROCKCHIP_RK3568_GRF_H__ + +struct rk3568_grf { + unsigned int gpio1a_iomux_l; + unsigned int gpio1a_iomux_h; + unsigned int gpio1b_iomux_l; + unsigned int gpio1b_iomux_h; + unsigned int gpio1c_iomux_l; + unsigned int gpio1c_iomux_h; + unsigned int gpio1d_iomux_l; + unsigned int gpio1d_iomux_h; + unsigned int gpio2a_iomux_l; + unsigned int gpio2a_iomux_h; + unsigned int gpio2b_iomux_l; + unsigned int gpio2b_iomux_h; + unsigned int gpio2c_iomux_l; + unsigned int gpio2c_iomux_h; + unsigned int gpio2d_iomux_l; + unsigned int gpio2d_iomux_h; + unsigned int gpio3a_iomux_l; + unsigned int gpio3a_iomux_h; + unsigned int gpio3b_iomux_l; + unsigned int gpio3b_iomux_h; + unsigned int gpio3c_iomux_l; + unsigned int gpio3c_iomux_h; + unsigned int gpio3d_iomux_l; + unsigned int gpio3d_iomux_h; + unsigned int gpio4a_iomux_l; + unsigned int gpio4a_iomux_h; + unsigned int gpio4b_iomux_l; + unsigned int gpio4b_iomux_h; + unsigned int gpio4c_iomux_l; + unsigned int gpio4c_iomux_h; + unsigned int gpio4d_iomux_l; + unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1]; + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int gpio2d_p; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int gpio3c_p; + unsigned int gpio3d_p; + unsigned int gpio4a_p; + unsigned int gpio4b_p; + unsigned int gpio4c_p; + unsigned int gpio4d_p; + unsigned int gpio1a_ie; + unsigned int gpio1b_ie; + unsigned int gpio1c_ie; + unsigned int gpio1d_ie; + unsigned int gpio2a_ie; + unsigned int gpio2b_ie; + unsigned int gpio2c_ie; + unsigned int gpio2d_ie; + unsigned int gpio3a_ie; + unsigned int gpio3b_ie; + unsigned int gpio3c_ie; + unsigned int gpio3d_ie; + unsigned int gpio4a_ie; + unsigned int gpio4b_ie; + unsigned int gpio4c_ie; + unsigned int gpio4d_ie; + unsigned int gpio1a_opd; + unsigned int gpio1b_opd; + unsigned int gpio1c_opd; + unsigned int gpio1d_opd; + unsigned int gpio2a_opd; + unsigned int gpio2b_opd; + unsigned int gpio2c_opd; + unsigned int gpio2d_opd; + unsigned int gpio3a_opd; + unsigned int gpio3b_opd; + unsigned int gpio3c_opd; + unsigned int gpio3d_opd; + unsigned int gpio4a_opd; + unsigned int gpio4b_opd; + unsigned int gpio4c_opd; + unsigned int gpio4d_opd; + unsigned int gpio1a_sus; + unsigned int gpio1b_sus; + unsigned int gpio1c_sus; + unsigned int gpio1d_sus; + unsigned int gpio2a_sus; + unsigned int gpio2b_sus; + unsigned int gpio2c_sus; + unsigned int gpio2d_sus; + unsigned int gpio3a_sus; + unsigned int gpio3b_sus; + unsigned int gpio3c_sus; + unsigned int gpio3d_sus; + unsigned int gpio4a_sus; + unsigned int gpio4b_sus; + unsigned int gpio4c_sus; + unsigned int gpio4d_sus; + unsigned int gpio1a_sl; + unsigned int gpio1b_sl; + unsigned int gpio1c_sl; + unsigned int gpio1d_sl; + unsigned int gpio2a_sl; + unsigned int gpio2b_sl; + unsigned int gpio2c_sl; + unsigned int gpio2d_sl; + unsigned int gpio3a_sl; + unsigned int gpio3b_sl; + unsigned int gpio3c_sl; + unsigned int gpio3d_sl; + unsigned int gpio4a_sl; + unsigned int gpio4b_sl; + unsigned int gpio4c_sl; + unsigned int gpio4d_sl; + unsigned int reserved1[(0x0200 - 0x01bc) / 4 - 1]; + unsigned int gpio1a_ds_0; + unsigned int gpio1a_ds_1; + unsigned int gpio1a_ds_2; + unsigned int gpio1a_ds_3; + unsigned int gpio1b_ds_0; + unsigned int gpio1b_ds_1; + unsigned int gpio1b_ds_2; + unsigned int gpio1b_ds_3; + unsigned int gpio1c_ds_0; + unsigned int gpio1c_ds_1; + unsigned int gpio1c_ds_2; + unsigned int gpio1c_ds_3; + unsigned int gpio1d_ds_0; + unsigned int gpio1d_ds_1; + unsigned int gpio1d_ds_2; + unsigned int gpio1d_ds_3; + unsigned int gpio2a_ds_0; + unsigned int gpio2a_ds_1; + unsigned int gpio2a_ds_2; + unsigned int gpio2a_ds_3; + unsigned int gpio2b_ds_0; + unsigned int gpio2b_ds_1; + unsigned int gpio2b_ds_2; + unsigned int gpio2b_ds_3; + unsigned int gpio2c_ds_0; + unsigned int gpio2c_ds_1; + unsigned int gpio2c_ds_2; + unsigned int gpio2c_ds_3; + unsigned int gpio2d_ds_0; + unsigned int gpio2d_ds_1; + unsigned int gpio2d_ds_2; + unsigned int gpio2d_ds_3; + unsigned int gpio3a_ds_0; + unsigned int gpio3a_ds_1; + unsigned int gpio3a_ds_2; + unsigned int gpio3a_ds_3; + unsigned int gpio3b_ds_0; + unsigned int gpio3b_ds_1; + unsigned int gpio3b_ds_2; + unsigned int gpio3b_ds_3; + unsigned int gpio3c_ds_0; + unsigned int gpio3c_ds_1; + unsigned int gpio3c_ds_2; + unsigned int gpio3c_ds_3; + unsigned int gpio3d_ds_0; + unsigned int gpio3d_ds_1; + unsigned int gpio3d_ds_2; + unsigned int gpio3d_ds_3; + unsigned int gpio4a_ds_0; + unsigned int gpio4a_ds_1; + unsigned int gpio4a_ds_2; + unsigned int gpio4a_ds_3; + unsigned int gpio4b_ds_0; + unsigned int gpio4b_ds_1; + unsigned int gpio4b_ds_2; + unsigned int gpio4b_ds_3; + unsigned int gpio4c_ds_0; + unsigned int gpio4c_ds_1; + unsigned int gpio4c_ds_2; + unsigned int gpio4c_ds_3; + unsigned int gpio4d_ds_0; + unsigned int gpio4d_ds_1; + unsigned int gpio4d_ds_2; + unsigned int gpio4d_ds_3; + unsigned int iofunc_sel0; + unsigned int iofunc_sel1; + unsigned int iofunc_sel2; + unsigned int iofunc_sel3; + unsigned int iofunc_sel4; + unsigned int iofunc_sel5; + unsigned int reserved2[(0x0340 - 0x0314) / 4 - 1]; + unsigned int vi_con0; + unsigned int vi_con1; + unsigned int vi_status0; + unsigned int reserved3[(0x0360 - 0x0348) / 4 - 1]; + unsigned int vo_con0; + unsigned int vo_con1; + unsigned int vo_con2; + unsigned int vo_con3; + unsigned int reserved4[(0x0380 - 0x036c) / 4 - 1]; + unsigned int mac0_con0; + unsigned int mac0_con1; + unsigned int mac1_con0; + unsigned int mac1_con1; + unsigned int reserved5[(0x03a0 - 0x038c) / 4 - 1]; + unsigned int biu_con0; + unsigned int biu_con1; + unsigned int biu_con2; + unsigned int reserved6[(0x03c0 - 0x03a8) / 4 - 1]; + unsigned int gic_con0; + unsigned int gic_con1; + unsigned int gic_con2; + unsigned int reserved7[(0x03f0 - 0x03c8) / 4 - 1]; + unsigned int gpu_con0; + unsigned int gpu_con1; + unsigned int reserved8[(0x0400 - 0x03f4) / 4 - 1]; + unsigned int cpu_con0; + unsigned int reserved9[(0x0420 - 0x0400) / 4 - 1]; + unsigned int cpu_status0; + unsigned int reserved10[(0x0500 - 0x0420) / 4 - 1]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_con3; + unsigned int reserved11[(0x0514 - 0x050c) / 4 - 1]; + unsigned int soc_con5; + unsigned int soc_con6; + unsigned int reserved12[(0x0580 - 0x0518) / 4 - 1]; + unsigned int soc_status0; + unsigned int reserved13[(0x05c0 - 0x0580) / 4 - 1]; + unsigned int ram_con; + unsigned int core_ram_con; + unsigned int reserved14[(0x0600 - 0x05c4) / 4 - 1]; + unsigned int tsadc_con; + unsigned int reserved15[(0x0610 - 0x0600) / 4 - 1]; + unsigned int saradc_con; + unsigned int reserved16[(0x0700 - 0x0610) / 4 - 1]; + unsigned int gpupvtpll_con0; + unsigned int gpupvtpll_con1; + unsigned int gpupvtpll_con2; + unsigned int gpupvtpll_con3; + unsigned int reserved17[(0x0740 - 0x070c) / 4 - 1]; + unsigned int npupvtpll_con0; + unsigned int npupvtpll_con1; + unsigned int npupvtpll_con2; + unsigned int npupvtpll_con3; + unsigned int reserved18[(0x0800 - 0x074c) / 4 - 1]; + unsigned int chip_id; + unsigned int reserved19[(0x0840 - 0x0800) / 4 - 1]; + unsigned int gpio1c5_ds; + unsigned int gpio2a2_ds; + unsigned int gpio2b0_ds; + unsigned int gpio3a0_ds; + unsigned int gpio3a6_ds; + unsigned int gpio4a0_ds; + unsigned int reserved20[(0x0900 - 0x0854) / 4 - 1]; + unsigned int dmac0_con0; + unsigned int dmac0_con1; + unsigned int dmac0_con2; + unsigned int dmac0_con3; + unsigned int dmac0_con4; + unsigned int dmac0_con5; + unsigned int dmac0_con6; + unsigned int dmac0_con7; + unsigned int dmac0_con8; + unsigned int dmac0_con9; + unsigned int reserved21[(0x0940 - 0x0924) / 4 - 1]; + unsigned int dmac1_con0; + unsigned int dmac1_con1; + unsigned int dmac1_con2; + unsigned int dmac1_con3; + unsigned int dmac1_con4; + unsigned int dmac1_con5; + unsigned int dmac1_con6; + unsigned int dmac1_con7; + unsigned int dmac1_con8; + unsigned int dmac1_con9; +}; + +check_member(rk3568_grf, dmac1_con9, 0x0964); + +struct rk3568_pmugrf { + unsigned int pmu_gpio0a_iomux_l; + unsigned int pmu_gpio0a_iomux_h; + unsigned int pmu_gpio0b_iomux_l; + unsigned int pmu_gpio0b_iomux_h; + unsigned int pmu_gpio0c_iomux_l; + unsigned int pmu_gpio0c_iomux_h; + unsigned int pmu_gpio0d_iomux_l; + unsigned int reserved0[(0x0020 - 0x0018) / 4 - 1]; + unsigned int pmu_gpio0a_p; + unsigned int pmu_gpio0b_p; + unsigned int pmu_gpio0c_p; + unsigned int pmu_gpio0d_p; + unsigned int pmu_gpio0a_ie; + unsigned int pmu_gpio0b_ie; + unsigned int pmu_gpio0c_ie; + unsigned int pmu_gpio0d_ie; + unsigned int pmu_gpio0a_opd; + unsigned int pmu_gpio0b_opd; + unsigned int pmu_gpio0c_opd; + unsigned int pmu_gpio0d_opd; + unsigned int pmu_gpio0a_sus; + unsigned int pmu_gpio0b_sus; + unsigned int pmu_gpio0c_sus; + unsigned int pmu_gpio0d_sus; + unsigned int pmu_gpio0a_sl; + unsigned int pmu_gpio0b_sl; + unsigned int pmu_gpio0c_sl; + unsigned int pmu_gpio0d_sl; + unsigned int pmu_gpio0a_ds_0; + unsigned int pmu_gpio0a_ds_1; + unsigned int pmu_gpio0a_ds_2; + unsigned int pmu_gpio0a_ds_3; + unsigned int pmu_gpio0b_ds_0; + unsigned int pmu_gpio0b_ds_1; + unsigned int pmu_gpio0b_ds_2; + unsigned int pmu_gpio0b_ds_3; + unsigned int pmu_gpio0c_ds_0; + unsigned int pmu_gpio0c_ds_1; + unsigned int pmu_gpio0c_ds_2; + unsigned int pmu_gpio0c_ds_3; + unsigned int pmu_gpio0d_ds_0; + unsigned int pmu_gpio0d_ds_1; + unsigned int pmu_gpio0d_ds_2; + unsigned int pmu_gpio0d_ds_3; + unsigned int reserved1[(0x0100 - 0x00ac) / 4 - 1]; + unsigned int pmu_soc_con0; + unsigned int pmu_soc_con1; + unsigned int pmu_soc_con2; + unsigned int pmu_soc_con3; + unsigned int pmu_soc_con4; + unsigned int pmu_soc_con5; + unsigned int reserved2[(0x0124 - 0x0114) / 4 - 1]; + unsigned int pmu_io_vsel0; + unsigned int pmu_io_vsel1; + unsigned int pmu_io_vsel2; + unsigned int reserved3[(0x0180 - 0x012c) / 4 - 1]; + unsigned int pmu_dll_con0; + unsigned int reserved4[(0x0200 - 0x0180) / 4 - 1]; + unsigned int pmu_os_reg0; + unsigned int pmu_os_reg1; + unsigned int pmu_os_reg2; + unsigned int pmu_os_reg3; + unsigned int pmu_os_reg4; + unsigned int pmu_os_reg5; + unsigned int pmu_os_reg6; + unsigned int pmu_os_reg7; + unsigned int pmu_os_reg8; + unsigned int pmu_os_reg9; + unsigned int pmu_os_reg10; + unsigned int pmu_os_reg11; + unsigned int pmu_reset_function_status; + unsigned int pmu_reset_function_clr; + unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1]; + unsigned int pmu_sig_detect_con; + unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1]; + unsigned int pmu_sig_detect_status; + unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1]; + unsigned int pmu_sig_detect_status_clear; + unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1]; + unsigned int pmu_sdmmc_det_counter; +}; + +check_member(rk3568_pmugrf, pmu_sdmmc_det_counter, 0x03b0); + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 407bf3fbeae..4a2d35aee22 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -257,6 +257,23 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3568 + bool "Support Rockchip RK3568" + select ARM64 + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + imply ROCKCHIP_COMMON_BOARD + help + The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, + including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, + two video interfaces supporting HDMI and eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 121f23a563e..00aef0ecee6 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ # Clear out SPL objects, in case this is a TPL build diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig new file mode 100644 index 00000000000..201c63c2a9c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -0,0 +1,20 @@ +if ROCKCHIP_RK3568 + +config TARGET_EVB_RK3568 + bool "RK3568 evaluation board" + select BOARD_LATE_INIT + help + RK3568 EVB is a evaluation board for Rockchp RK3568. + +config ROCKCHIP_BOOT_MODE_REG + default 0xfdc20200 + +config SYS_SOC + default "rk3568" + +config SYS_MALLOC_F_LEN + default 0x2000 + +source "board/rockchip/evb_rk3568/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3568/Makefile b/arch/arm/mach-rockchip/rk3568/Makefile new file mode 100644 index 00000000000..28c1f4ee5c9 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2021 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk_rk3568.o +obj-y += rk3568.o +obj-y += syscon_rk3568.o diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c new file mode 100644 index 00000000000..8917edcbd30 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3568_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3568_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} + +static int rockchip_get_pmucruclk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3568_pmucru), devp); +} + +void *rockchip_get_pmucru(void) +{ + struct rk3568_pmuclk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_pmucruclk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->pmucru; +} diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c new file mode 100644 index 00000000000..973b4f9dcbd --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PMUGRF_BASE 0xfdc20000 +#define GRF_BASE 0xfdc60000 + +/* PMU_GRF_GPIO0D_IOMUX_L */ +enum { + GPIO0D1_SHIFT = 4, + GPIO0D1_MASK = GENMASK(6, 4), + GPIO0D1_GPIO = 0, + GPIO0D1_UART2_TXM0, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = GENMASK(2, 0), + GPIO0D0_GPIO = 0, + GPIO0D0_UART2_RXM0, +}; + +/* GRF_IOFUNC_SEL3 */ +enum { + UART2_IO_SEL_SHIFT = 10, + UART2_IO_SEL_MASK = GENMASK(11, 10), + UART2_IO_SEL_M0 = 0, +}; + +static struct mm_region rk3568_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xf0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x300000000, + .phys = 0x300000000, + .size = 0x0c0c00000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3568_mem_map; + +void board_debug_uart_init(void) +{ + static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE; + static struct rk3568_grf * const grf = (void *)GRF_BASE; + + /* UART2 M0 */ + rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK, + UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT); + + /* Switch iomux */ + rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l, + GPIO0D1_MASK | GPIO0D0_MASK, + GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT | + GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT); +} + +int arch_cpu_init(void) +{ + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c new file mode 100644 index 00000000000..20adfd11690 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include + +static const struct udevice_id rk3568_syscon_ids[] = { + { .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3568) = { + .name = "rk3568_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3568_syscon_ids, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h new file mode 100644 index 00000000000..b6568917ea8 --- /dev/null +++ b/include/configs/rk3568_common.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3568_COMMON_H +#define __CONFIG_RK3568_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 + +#define CONFIG_IRAM_BASE 0xfdcc0000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 +#define CONFIG_SYS_LOAD_ADDR 0x00c00800 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xf0000000 + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00c00000\0" \ + "pxefile_addr_r=0x00e00000\0" \ + "fdt_addr_r=0x0a100000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x0a200000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV +#endif + +#endif From 695693b2d0cb1b2b2a3755c34de1420000021a9c Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 2 Jun 2021 16:13:46 +0800 Subject: [PATCH 110/250] board: rockchip: Add rk3568 evb support Add support for rk3568 evaluation board. Signed-off-by: Joseph Chen Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + board/rockchip/evb_rk3568/Kconfig | 15 +++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 6 +++++ board/rockchip/evb_rk3568/Makefile | 7 ++++++ board/rockchip/evb_rk3568/evb_rk3568.c | 4 +++ configs/evb-rk3568_defconfig | 35 ++++++++++++++++++++++++++ include/configs/evb_rk3568.h | 17 +++++++++++++ 7 files changed, 85 insertions(+) create mode 100644 board/rockchip/evb_rk3568/Kconfig create mode 100644 board/rockchip/evb_rk3568/MAINTAINERS create mode 100644 board/rockchip/evb_rk3568/Makefile create mode 100644 board/rockchip/evb_rk3568/evb_rk3568.c create mode 100644 configs/evb-rk3568_defconfig create mode 100644 include/configs/evb_rk3568.h diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4a2d35aee22..35bdef29fe6 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -403,5 +403,6 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" endif diff --git a/board/rockchip/evb_rk3568/Kconfig b/board/rockchip/evb_rk3568/Kconfig new file mode 100644 index 00000000000..f3d3a7e1112 --- /dev/null +++ b/board/rockchip/evb_rk3568/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3568 + +config SYS_BOARD + default "evb_rk3568" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3568" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS new file mode 100644 index 00000000000..b6ea498d2b3 --- /dev/null +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3568 +M: Joseph Chen +S: Maintained +F: board/rockchip/evb_rk3568 +F: include/configs/evb_rk3568.h +F: configs/evb-rk3568_defconfig diff --git a/board/rockchip/evb_rk3568/Makefile b/board/rockchip/evb_rk3568/Makefile new file mode 100644 index 00000000000..cbda95fe94d --- /dev/null +++ b/board/rockchip/evb_rk3568/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2021 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3568.o diff --git a/board/rockchip/evb_rk3568/evb_rk3568.c b/board/rockchip/evb_rk3568/evb_rk3568.c new file mode 100644 index 00000000000..c2fdf95d9a1 --- /dev/null +++ b/board/rockchip/evb_rk3568/evb_rk3568.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig new file mode 100644 index 00000000000..03511d790e0 --- /dev/null +++ b/configs/evb-rk3568_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00a00000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ROCKCHIP_RK3568=y +CONFIG_TARGET_EVB_RK3568=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/evb_rk3568.h b/include/configs/evb_rk3568.h new file mode 100644 index 00000000000..2b255a11da2 --- /dev/null +++ b/include/configs/evb_rk3568.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3568_H +#define __EVB_RK3568_H + +#include + +#define CONFIG_SUPPORT_EMMC_RPMB + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif From a122d3a6a097e93f3d84378dc3d26801b73e1995 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Sat, 5 Jun 2021 14:38:41 +0000 Subject: [PATCH 111/250] pci: pcie_dw_rockchip: Fixed the below compilation error Use the generic error number instead of specific error number. Changes fix the below error. drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read': drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 70 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write': drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 90 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ Cc: Patrick Wildt Cc: Neil Armstrong Cc: Kever Yang Reviewed-by: Neil Armstrong Reviewed-by: Patrick Wildt Signed-off-by: Anand Moon Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index bc22af4230c..3ac2434b69d 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { *val = 0; - return PCIBIOS_UNSUPPORTED; + return -EOPNOTSUPP; } if (size == 4) { @@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val) static int rk_pcie_write(void __iomem *addr, int size, u32 val) { if ((uintptr_t)addr & (size - 1)) - return PCIBIOS_UNSUPPORTED; + return -EOPNOTSUPP; if (size == 4) writel(val, addr); From 290686f79a3c0bc3adaca941f665efe301fadea0 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Sat, 5 Jun 2021 14:38:42 +0000 Subject: [PATCH 112/250] pci: pcie_dw_rockchip: Drop the unused variable warning Drop the unused variable warning below. drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable 'val' [-Wunused-variable] 161 | u32 val; | ^~~ Cc: Patrick Wildt Cc: Neil Armstrong Cc: Kever Yang Reviewed-by: Neil Armstrong Reviewed-by: Patrick Wildt Signed-off-by: Anand Moon Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 3ac2434b69d..4e448c0a3df 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, */ static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) { - u32 val; - dw_pcie_dbi_write_enable(&pci->dw, true); clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, From 88647f078dbae9a43a37af37454f2b9f535a16dd Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Sat, 5 Jun 2021 14:38:43 +0000 Subject: [PATCH 113/250] pci: pcie_dw_rockchip: Replace msleep occurences by udelay Replace msleep occurences by udelay. drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit declaration of function 'msleep' [-Wimplicit-function-declaration] Cc: Patrick Wildt Cc: Neil Armstrong Cc: Kever Yang Signed-off-by: Anand Moon Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 4e448c0a3df..9322e735b9c 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -61,7 +61,7 @@ struct rk_pcie { #define PCIE_CLIENT_DBF_EN 0xffff0003 /* Parameters for the waiting for #perst signal */ -#define PERST_WAIT_MS 1000 +#define MACRO_US 1000 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { @@ -249,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) * some wired devices need much more, such as 600ms. * Add a enough delay to cover all cases. */ - msleep(PERST_WAIT_MS); + udelay(MACRO_US * 1000); dm_gpio_set_value(&priv->rst_gpio, 1); } @@ -271,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n", rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); rk_pcie_debug_dump(priv); - msleep(1000); + udelay(MACRO_US * 1000); } dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev)); /* Link maybe in Gen switch recovery but we need to wait more 1s */ - msleep(1000); + udelay(MACRO_US * 1000); return -EIO; } @@ -296,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) } } - msleep(1000); + udelay(MACRO_US * 1000); ret = generic_phy_init(&priv->phy); if (ret) { From ad0e919492b0957ffde813c7e03ac20355a1240c Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Mon, 7 Jun 2021 11:45:04 +0800 Subject: [PATCH 114/250] ARM64: rockchip: evb_rk3399: add usb ohci definations Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard) Add missed USB OHCI configuration USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Human Interface (1.5 Mb/s, 100mA) Dell KB216 Wired Keyboard Signed-off-by: Artem Lapkin Reviewed-by: Kever Yang --- include/configs/evb_rk3399.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index b7e850370b3..492b7b4df12 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -15,4 +15,7 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif From 7da079d54d1d39ecfc571701e8deff4e692eb893 Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Mon, 7 Jun 2021 11:45:05 +0800 Subject: [PATCH 115/250] configs: rockchip: rk3399: Khadas Edge add USB OHCI Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard) Add missed USB OHCI configuration USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Human Interface (1.5 Mb/s, 100mA) Dell KB216 Wired Keyboard Signed-off-by: Artem Lapkin Reviewed-by: Kever Yang --- configs/khadas-edge-captain-rk3399_defconfig | 2 ++ configs/khadas-edge-rk3399_defconfig | 2 ++ configs/khadas-edge-v-rk3399_defconfig | 2 ++ 3 files changed, 6 insertions(+) diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 63074a4eed7..ce6b492b3de 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -50,6 +50,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index cf5a6da3842..e52963e86f2 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -49,6 +49,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 197a6f66772..5f61df85daf 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -50,6 +50,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y From b12dc5d6fa766b26f567a1f569d4a7effef3b49f Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Mon, 7 Jun 2021 16:40:29 +0800 Subject: [PATCH 116/250] mtd: nand: NFC drivers for RK3308, RK2928 and others This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using 8-bit NAND interface on the ARM based RK3308 platform. Support Rockchip SoCs and NFC versions: - PX30 and RK3326(NFCv900). ECC: 16/40/60/70 bits/1KB. CLOCK: ahb and nfc. - RK3308 and RV1108(NFCv800). ECC: 16 bits/1KB. CLOCK: ahb and nfc. - RK3036 and RK3128(NFCv622). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb and nfc. - RK3066, RK3188 and RK2928(NFCv600). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb. Supported features: - Read full page data by DMA. - Support HW ECC(one step is 1KB). - Support 2 - 32K page size. - Support 8 CS(depend on SoCs) Limitations: - No support for the ecc step size is 512. - Untested on some SoCs. - No support for subpages. - No support for the builtin randomizer. - The original bad block mask is not supported. It is recommended to use the BBT(bad block table). Signed-off-by: Yifeng Zhao Reviewed-by: Kever Yang --- drivers/mtd/nand/raw/Kconfig | 16 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/rockchip_nfc.c | 1253 +++++++++++++++++++++++++++ 3 files changed, 1270 insertions(+) create mode 100644 drivers/mtd/nand/raw/rockchip_nfc.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ed151ee0a5c..a901ce55111 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -333,6 +333,22 @@ config CORTINA_NAND The controller supports a maximum 8k page size and supports a maximum 40-bit error correction per sector of 1024 bytes. +config ROCKCHIP_NAND + bool "Support for NAND controller on Rockchip SoCs" + depends on ARCH_ROCKCHIP + select SYS_NAND_SELF_INIT + select DM_MTD + imply CMD_NAND + help + Enables support for NAND Flash chips on Rockchip SoCs platform. + This controller is found on Rockchip SoCs. + There are four different versions of NAND FLASH Controllers, + including: + NFC v600: RK2928, RK3066, RK3188 + NFC v622: RK3036, RK3128 + NFC v800: RK3308, RV1108 + NFC v900: PX30, RK3326 + comment "Generic NAND options" config SYS_NAND_BLOCK_SIZE diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index f3f0e15a157..a5ed2c536f5 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o +obj-$(CONFIG_ROCKCHIP_NAND) += rockchip_nfc.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c new file mode 100644 index 00000000000..21776f3b14c --- /dev/null +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -0,0 +1,1253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip NAND Flash controller driver. + * Copyright (C) 2021 Rockchip Inc. + * Author: Yifeng Zhao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * NFC Page Data Layout: + * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + + * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + + * ...... + * NAND Page Data Layout: + * 1024 * n data + m Bytes oob + * Original Bad Block Mask Location: + * First byte of oob(spare). + * nand_chip->oob_poi data layout: + * 4Bytes sys data + .... + 4Bytes sys data + ECC data. + */ + +/* NAND controller register definition */ +#define NFC_READ (0) +#define NFC_WRITE (1) + +#define NFC_FMCTL (0x00) +#define FMCTL_CE_SEL_M 0xFF +#define FMCTL_CE_SEL(x) (1 << (x)) +#define FMCTL_WP BIT(8) +#define FMCTL_RDY BIT(9) + +#define NFC_FMWAIT (0x04) +#define FLCTL_RST BIT(0) +#define FLCTL_WR (1) /* 0: read, 1: write */ +#define FLCTL_XFER_ST BIT(2) +#define FLCTL_XFER_EN BIT(3) +#define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */ +#define FLCTL_XFER_READY BIT(20) +#define FLCTL_XFER_SECTOR (22) +#define FLCTL_TOG_FIX BIT(29) + +#define BCHCTL_BANK_M (7 << 5) +#define BCHCTL_BANK (5) + +#define DMA_ST BIT(0) +#define DMA_WR (1) /* 0: write, 1: read */ +#define DMA_EN BIT(2) +#define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */ +#define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */ +#define DMA_INC_NUM (9) /* 1 - 16 */ + +#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\ + (((x) >> (e).high) & (e).high_mask) << (e).low_bn) +#define INT_DMA BIT(0) +#define NFC_BANK (0x800) +#define NFC_BANK_STEP (0x100) +#define BANK_DATA (0x00) +#define BANK_ADDR (0x04) +#define BANK_CMD (0x08) +#define NFC_SRAM0 (0x1000) +#define NFC_SRAM1 (0x1400) +#define NFC_SRAM_SIZE (0x400) +#define NFC_TIMEOUT_MS (500) +#define NFC_MAX_OOB_PER_STEP 128 +#define NFC_MIN_OOB_PER_STEP 64 +#define MAX_DATA_SIZE 0xFFFC +#define MAX_ADDRESS_CYC 6 +#define NFC_ECC_MAX_MODES 4 +#define NFC_RB_DELAY_US 50 +#define NFC_MAX_PAGE_SIZE (16 * 1024) +#define NFC_MAX_OOB_SIZE (16 * 128) +#define NFC_MAX_NSELS (8) /* Some Socs only have 1 or 2 CSs. */ +#define NFC_SYS_DATA_SIZE (4) /* 4 bytes sys data in oob pre 1024 data.*/ +#define RK_DEFAULT_CLOCK_RATE (150 * 1000 * 1000) /* 150 Mhz */ +#define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs)) + +enum nfc_type { + NFC_V6, + NFC_V8, + NFC_V9, +}; + +/** + * struct rk_ecc_cnt_status: represent a ecc status data. + * @err_flag_bit: error flag bit index at register. + * @low: ECC count low bit index at register. + * @low_mask: mask bit. + * @low_bn: ECC count low bit number. + * @high: ECC count high bit index at register. + * @high_mask: mask bit + */ +struct ecc_cnt_status { + u8 err_flag_bit; + u8 low; + u8 low_mask; + u8 low_bn; + u8 high; + u8 high_mask; +}; + +/** + * @type: NFC version + * @ecc_strengths: ECC strengths + * @ecc_cfgs: ECC config values + * @flctl_off: FLCTL register offset + * @bchctl_off: BCHCTL register offset + * @dma_data_buf_off: DMA_DATA_BUF register offset + * @dma_oob_buf_off: DMA_OOB_BUF register offset + * @dma_cfg_off: DMA_CFG register offset + * @dma_st_off: DMA_ST register offset + * @bch_st_off: BCG_ST register offset + * @randmz_off: RANDMZ register offset + * @int_en_off: interrupt enable register offset + * @int_clr_off: interrupt clean register offset + * @int_st_off: interrupt status register offset + * @oob0_off: oob0 register offset + * @oob1_off: oob1 register offset + * @ecc0: represent ECC0 status data + * @ecc1: represent ECC1 status data + */ +struct nfc_cfg { + enum nfc_type type; + u8 ecc_strengths[NFC_ECC_MAX_MODES]; + u32 ecc_cfgs[NFC_ECC_MAX_MODES]; + u32 flctl_off; + u32 bchctl_off; + u32 dma_cfg_off; + u32 dma_data_buf_off; + u32 dma_oob_buf_off; + u32 dma_st_off; + u32 bch_st_off; + u32 randmz_off; + u32 int_en_off; + u32 int_clr_off; + u32 int_st_off; + u32 oob0_off; + u32 oob1_off; + struct ecc_cnt_status ecc0; + struct ecc_cnt_status ecc1; +}; + +struct rk_nfc_nand_chip { + struct nand_chip chip; + + u16 boot_blks; + u16 metadata_size; + u32 boot_ecc; + u32 timing; + + u8 nsels; + u8 sels[0]; + /* Nothing after this field. */ +}; + +struct rk_nfc { + struct nand_hw_control controller; + const struct nfc_cfg *cfg; + struct udevice *dev; + + struct clk *nfc_clk; + struct clk *ahb_clk; + void __iomem *regs; + + int selected_bank; + u32 band_offset; + u32 cur_ecc; + u32 cur_timing; + + u8 *page_buf; + u32 *oob_buf; + + unsigned long assigned_cs; +}; + +static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip) +{ + return container_of(chip, struct rk_nfc_nand_chip, chip); +} + +static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i) +{ + return (u8 *)p + i * chip->ecc.size; +} + +static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i) +{ + u8 *poi; + + poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE; + + return poi; +} + +static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i) +{ + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + u8 *poi; + + poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i; + + return poi; +} + +static inline int rk_nfc_data_len(struct nand_chip *chip) +{ + return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE; +} + +static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + + return nfc->page_buf + i * rk_nfc_data_len(chip); +} + +static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + + return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size; +} + +static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + u32 reg, i; + + for (i = 0; i < NFC_ECC_MAX_MODES; i++) { + if (strength == nfc->cfg->ecc_strengths[i]) { + reg = nfc->cfg->ecc_cfgs[i]; + break; + } + } + + if (i >= NFC_ECC_MAX_MODES) + return -EINVAL; + + writel(reg, nfc->regs + nfc->cfg->bchctl_off); + + /* Save chip ECC setting */ + nfc->cur_ecc = strength; + + return 0; +} + +static void rk_nfc_select_chip(struct mtd_info *mtd, int cs) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + u32 val; + + if (cs < 0) { + nfc->selected_bank = -1; + /* Deselect the currently selected target. */ + val = readl(nfc->regs + NFC_FMCTL); + val &= ~FMCTL_CE_SEL_M; + writel(val, nfc->regs + NFC_FMCTL); + return; + } + + nfc->selected_bank = rknand->sels[cs]; + nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP; + + val = readl(nfc->regs + NFC_FMCTL); + val &= ~FMCTL_CE_SEL_M; + val |= FMCTL_CE_SEL(nfc->selected_bank); + + writel(val, nfc->regs + NFC_FMCTL); + + /* + * Compare current chip timing with selected chip timing and + * change if needed. + */ + if (nfc->cur_timing != rknand->timing) { + writel(rknand->timing, nfc->regs + NFC_FMWAIT); + nfc->cur_timing = rknand->timing; + } + + /* + * Compare current chip ECC setting with selected chip ECC setting and + * change if needed. + */ + if (nfc->cur_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, ecc->strength); +} + +static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc) +{ + u32 timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000; + u32 time_start; + + time_start = get_timer(0); + do { + if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY) + return 0; + } while (get_timer(time_start) < timeout); + + dev_err(nfc->dev, "wait for io ready timedout\n"); + return -ETIMEDOUT; +} + +static void rk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + void __iomem *bank_base; + int i = 0; + + bank_base = nfc->regs + nfc->band_offset + BANK_DATA; + + for (i = 0; i < len; i++) + buf[i] = readl(bank_base); +} + +static void rk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + void __iomem *bank_base; + int i = 0; + + bank_base = nfc->regs + nfc->band_offset + BANK_DATA; + + for (i = 0; i < len; i++) + writel(buf[i], bank_base); +} + +static void rk_nfc_cmd(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + void __iomem *bank_base; + + bank_base = nfc->regs + nfc->band_offset; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_ALE) + bank_base += BANK_ADDR; + else if (ctrl & NAND_CLE) + bank_base += BANK_CMD; + chip->IO_ADDR_W = bank_base; + } + + if (dat != NAND_CMD_NONE) + writel(dat & 0xFF, chip->IO_ADDR_W); +} + +static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + rk_nfc_read_buf(mtd, &ret, 1); + + return ret; +} + +static int rockchip_nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + + if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY) + return 1; + + return 0; +} + +static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB, + dma_addr_t dma_data, dma_addr_t dma_oob) +{ + u32 dma_reg, fl_reg, bch_reg; + + dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) | + (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM); + + fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT | + (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX; + + if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) { + bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off); + bch_reg = (bch_reg & (~BCHCTL_BANK_M)) | + (nfc->selected_bank << BCHCTL_BANK); + writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off); + } + + writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off); + writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off); + writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off); + writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); + fl_reg |= FLCTL_XFER_ST; + writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); +} + +static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc) +{ + unsigned long timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000; + void __iomem *ptr = nfc->regs + nfc->cfg->flctl_off; + u32 time_start; + + time_start = get_timer(0); + + do { + if (readl(ptr) & FLCTL_XFER_READY) + return 0; + } while (get_timer(time_start) < timeout); + + dev_err(nfc->dev, "wait for io ready timedout\n"); + return -ETIMEDOUT; +} + +static int rk_nfc_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, + const u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int i, pages_per_blk; + + pages_per_blk = mtd->erasesize / mtd->writesize; + if ((page < (pages_per_blk * rknand->boot_blks)) && + rknand->boot_ecc != ecc->strength) { + /* + * There's currently no method to notify the MTD framework that + * a different ECC strength is in use for the boot blocks. + */ + return -EIO; + } + + if (!buf) + memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize); + + for (i = 0; i < ecc->steps; i++) { + /* Copy data to the NFC buffer. */ + if (buf) + memcpy(rk_nfc_data_ptr(chip, i), + rk_nfc_buf_to_data_ptr(chip, buf, i), + ecc->size); + /* + * The first four bytes of OOB are reserved for the + * boot ROM. In some debugging cases, such as with a + * read, erase and write back test these 4 bytes stored + * in OOB also need to be written back. + * + * The function nand_block_bad detects bad blocks like: + * + * bad = chip->oob_poi[chip->badblockpos]; + * + * chip->badblockpos == 0 for a large page NAND Flash, + * so chip->oob_poi[0] is the bad block mask (BBM). + * + * The OOB data layout on the NFC is: + * + * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... + * + * or + * + * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... + * + * The code here just swaps the first 4 bytes with the last + * 4 bytes without losing any data. + * + * The chip->oob_poi data layout: + * + * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 + * + * The rk_nfc_ooblayout_free() function already has reserved + * these 4 bytes with: + * + * oob_region->offset = NFC_SYS_DATA_SIZE + 2; + */ + if (!i) + memcpy(rk_nfc_oob_ptr(chip, i), + rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), + NFC_SYS_DATA_SIZE); + else + memcpy(rk_nfc_oob_ptr(chip, i), + rk_nfc_buf_to_oob_ptr(chip, i - 1), + NFC_SYS_DATA_SIZE); + /* Copy ECC data to the NFC buffer. */ + memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, + rk_nfc_buf_to_oob_ecc_ptr(chip, i), + ecc->bytes); + } + + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + rk_nfc_write_buf(mtd, buf, mtd->writesize + mtd->oobsize); + return nand_prog_page_end_op(chip); +} + +static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, + const u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : + NFC_MIN_OOB_PER_STEP; + int pages_per_blk = mtd->erasesize / mtd->writesize; + int ret = 0, i, boot_rom_mode = 0; + dma_addr_t dma_data, dma_oob; + u32 reg; + u8 *oob; + + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + + if (buf) + memcpy(nfc->page_buf, buf, mtd->writesize); + else + memset(nfc->page_buf, 0xFF, mtd->writesize); + + /* + * The first blocks (4, 8 or 16 depending on the device) are used + * by the boot ROM and the first 32 bits of OOB need to link to + * the next page address in the same block. We can't directly copy + * OOB data from the MTD framework, because this page address + * conflicts for example with the bad block marker (BBM), + * so we shift all OOB data including the BBM with 4 byte positions. + * As a consequence the OOB size available to the MTD framework is + * also reduced with 4 bytes. + * + * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... + * + * If a NAND is not a boot medium or the page is not a boot block, + * the first 4 bytes are left untouched by writing 0xFF to them. + * + * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... + * + * Configure the ECC algorithm supported by the boot ROM. + */ + if (page < (pages_per_blk * rknand->boot_blks)) { + boot_rom_mode = 1; + if (rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); + } + + for (i = 0; i < ecc->steps; i++) { + if (!i) { + reg = 0xFFFFFFFF; + } else { + oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + reg = oob[0] | oob[1] << 8 | oob[2] << 16 | + oob[3] << 24; + } + + if (!i && boot_rom_mode) + reg = (page & (pages_per_blk - 1)) * 4; + + if (nfc->cfg->type == NFC_V9) + nfc->oob_buf[i] = reg; + else + nfc->oob_buf[i * (oob_step / 4)] = reg; + } + + dma_data = dma_map_single((void *)nfc->page_buf, + mtd->writesize, DMA_TO_DEVICE); + dma_oob = dma_map_single(nfc->oob_buf, + ecc->steps * oob_step, + DMA_TO_DEVICE); + + rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data, + dma_oob); + ret = rk_nfc_wait_for_xfer_done(nfc); + + dma_unmap_single(dma_data, mtd->writesize, + DMA_TO_DEVICE); + dma_unmap_single(dma_oob, ecc->steps * oob_step, + DMA_TO_DEVICE); + + if (boot_rom_mode && rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, ecc->strength); + + if (ret) { + dev_err(nfc->dev, "write: wait transfer done timeout.\n"); + return -ETIMEDOUT; + } + + return nand_prog_page_end_op(chip); +} + +static int rk_nfc_write_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + return rk_nfc_write_page_hwecc(mtd, chip, NULL, 1, page); +} + +static int rk_nfc_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, + u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int i, pages_per_blk; + + pages_per_blk = mtd->erasesize / mtd->writesize; + if ((page < (pages_per_blk * rknand->boot_blks)) && + nfc->selected_bank == 0 && + rknand->boot_ecc != ecc->strength) { + /* + * There's currently no method to notify the MTD framework that + * a different ECC strength is in use for the boot blocks. + */ + return -EIO; + } + + nand_read_page_op(chip, page, 0, NULL, 0); + rk_nfc_read_buf(mtd, nfc->page_buf, mtd->writesize + mtd->oobsize); + for (i = 0; i < ecc->steps; i++) { + /* + * The first four bytes of OOB are reserved for the + * boot ROM. In some debugging cases, such as with a read, + * erase and write back test, these 4 bytes also must be + * saved somewhere, otherwise this information will be + * lost during a write back. + */ + if (!i) + memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), + rk_nfc_oob_ptr(chip, i), + NFC_SYS_DATA_SIZE); + else + memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1), + rk_nfc_oob_ptr(chip, i), + NFC_SYS_DATA_SIZE); + + /* Copy ECC data from the NFC buffer. */ + memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i), + rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, + ecc->bytes); + + /* Copy data from the NFC buffer. */ + if (buf) + memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i), + rk_nfc_data_ptr(chip, i), + ecc->size); + } + + return 0; +} + +static int rk_nfc_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, + u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : + NFC_MIN_OOB_PER_STEP; + int pages_per_blk = mtd->erasesize / mtd->writesize; + dma_addr_t dma_data, dma_oob; + int ret = 0, i, cnt, boot_rom_mode = 0; + int max_bitflips = 0, bch_st, ecc_fail = 0; + u8 *oob; + u32 tmp; + + nand_read_page_op(chip, page, 0, NULL, 0); + + dma_data = dma_map_single(nfc->page_buf, + mtd->writesize, + DMA_FROM_DEVICE); + dma_oob = dma_map_single(nfc->oob_buf, + ecc->steps * oob_step, + DMA_FROM_DEVICE); + + /* + * The first blocks (4, 8 or 16 depending on the device) + * are used by the boot ROM. + * Configure the ECC algorithm supported by the boot ROM. + */ + if (page < (pages_per_blk * rknand->boot_blks) && + nfc->selected_bank == 0) { + boot_rom_mode = 1; + if (rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); + } + + rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data, + dma_oob); + ret = rk_nfc_wait_for_xfer_done(nfc); + + dma_unmap_single(dma_data, mtd->writesize, + DMA_FROM_DEVICE); + dma_unmap_single(dma_oob, ecc->steps * oob_step, + DMA_FROM_DEVICE); + + if (ret) { + ret = -ETIMEDOUT; + dev_err(nfc->dev, "read: wait transfer done timeout.\n"); + goto timeout_err; + } + + for (i = 1; i < ecc->steps; i++) { + oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + if (nfc->cfg->type == NFC_V9) + tmp = nfc->oob_buf[i]; + else + tmp = nfc->oob_buf[i * (oob_step / 4)]; + *oob++ = (u8)tmp; + *oob++ = (u8)(tmp >> 8); + *oob++ = (u8)(tmp >> 16); + *oob++ = (u8)(tmp >> 24); + } + + for (i = 0; i < (ecc->steps / 2); i++) { + bch_st = readl_relaxed(nfc->regs + + nfc->cfg->bch_st_off + i * 4); + if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) || + bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) { + mtd->ecc_stats.failed++; + ecc_fail = 1; + } else { + cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0); + mtd->ecc_stats.corrected += cnt; + max_bitflips = max_t(u32, max_bitflips, cnt); + + cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1); + mtd->ecc_stats.corrected += cnt; + max_bitflips = max_t(u32, max_bitflips, cnt); + } + } + + if (buf) + memcpy(buf, nfc->page_buf, mtd->writesize); + +timeout_err: + if (boot_rom_mode && rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, ecc->strength); + + if (ret) + return ret; + + if (ecc_fail) { + dev_err(nfc->dev, "read page: %x ecc error!\n", page); + return 0; + } + + return max_bitflips; +} + +static int rk_nfc_read_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + return rk_nfc_read_page_hwecc(mtd, chip, NULL, 1, page); +} + +static inline void rk_nfc_hw_init(struct rk_nfc *nfc) +{ + /* Disable flash wp. */ + writel(FMCTL_WP, nfc->regs + NFC_FMCTL); + /* Config default timing 40ns at 150 Mhz NFC clock. */ + writel(0x1081, nfc->regs + NFC_FMWAIT); + nfc->cur_timing = 0x1081; + /* Disable randomizer and DMA. */ + writel(0, nfc->regs + nfc->cfg->randmz_off); + writel(0, nfc->regs + nfc->cfg->dma_cfg_off); + writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off); +} + +static int rk_nfc_enable_clks(struct udevice *dev, struct rk_nfc *nfc) +{ + int ret; + + if (!IS_ERR(nfc->nfc_clk)) { + ret = clk_prepare_enable(nfc->nfc_clk); + if (ret) + dev_err(dev, "failed to enable NFC clk\n"); + } + + ret = clk_prepare_enable(nfc->ahb_clk); + if (ret) { + dev_err(dev, "failed to enable ahb clk\n"); + if (!IS_ERR(nfc->nfc_clk)) + clk_disable_unprepare(nfc->nfc_clk); + } + + return 0; +} + +static void rk_nfc_disable_clks(struct rk_nfc *nfc) +{ + if (!IS_ERR(nfc->nfc_clk)) + clk_disable_unprepare(nfc->nfc_clk); + clk_disable_unprepare(nfc->ahb_clk); +} + +static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oob_region) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + + if (section) + return -ERANGE; + + /* + * The beginning of the OOB area stores the reserved data for the NFC, + * the size of the reserved data is NFC_SYS_DATA_SIZE bytes. + */ + oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; + oob_region->offset = NFC_SYS_DATA_SIZE + 2; + + return 0; +} + +static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oob_region) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + + if (section) + return -ERANGE; + + oob_region->length = mtd->oobsize - rknand->metadata_size; + oob_region->offset = rknand->metadata_size; + + return 0; +} + +static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = { + .rfree = rk_nfc_ooblayout_free, + .ecc = rk_nfc_ooblayout_ecc, +}; + +static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip) +{ + const u8 *strengths = nfc->cfg->ecc_strengths; + struct mtd_info *mtd = nand_to_mtd(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + u8 max_strength, nfc_max_strength; + int i; + + nfc_max_strength = nfc->cfg->ecc_strengths[0]; + /* If optional dt settings not present. */ + if (!ecc->size || !ecc->strength || + ecc->strength > nfc_max_strength) { + chip->ecc.size = 1024; + ecc->steps = mtd->writesize / ecc->size; + + /* + * HW ECC always requests the number of ECC bytes per 1024 byte + * blocks. The first 4 OOB bytes are reserved for sys data. + */ + max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 / + fls(8 * 1024); + if (max_strength > nfc_max_strength) + max_strength = nfc_max_strength; + + for (i = 0; i < 4; i++) { + if (max_strength >= strengths[i]) + break; + } + + if (i >= 4) { + dev_err(nfc->dev, "unsupported ECC strength\n"); + return -EOPNOTSUPP; + } + + ecc->strength = strengths[i]; + } + ecc->steps = mtd->writesize / ecc->size; + ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8); + + return 0; +} + +static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) +{ + struct rk_nfc_nand_chip *rknand; + struct udevice *dev = nfc->dev; + struct nand_ecc_ctrl *ecc; + struct nand_chip *chip; + struct mtd_info *mtd; + u32 cs[NFC_MAX_NSELS]; + int nsels, i, ret; + u32 tmp; + + if (!ofnode_get_property(node, "reg", &nsels)) + return -ENODEV; + nsels /= sizeof(u32); + if (!nsels || nsels > NFC_MAX_NSELS) { + dev_err(dev, "invalid reg property size %d\n", nsels); + return -EINVAL; + } + + rknand = kzalloc(sizeof(*rknand) + nsels * sizeof(u8), GFP_KERNEL); + if (!rknand) + return -ENOMEM; + + rknand->nsels = nsels; + rknand->timing = nfc->cur_timing; + + ret = ofnode_read_u32_array(node, "reg", cs, nsels); + if (ret < 0) { + dev_err(dev, "Could not retrieve reg property\n"); + return -EINVAL; + } + + for (i = 0; i < nsels; i++) { + if (cs[i] >= NFC_MAX_NSELS) { + dev_err(dev, "invalid CS: %u\n", cs[i]); + return -EINVAL; + } + + if (test_and_set_bit(cs[i], &nfc->assigned_cs)) { + dev_err(dev, "CS %u already assigned\n", cs[i]); + return -EINVAL; + } + + rknand->sels[i] = cs[i]; + } + + chip = &rknand->chip; + ecc = &chip->ecc; + ecc->mode = NAND_ECC_HW_SYNDROME; + + ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp); + ecc->strength = ret ? 0 : tmp; + + ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp); + ecc->size = ret ? 0 : tmp; + + mtd = nand_to_mtd(chip); + mtd->owner = THIS_MODULE; + mtd->dev->parent = dev; + + nand_set_controller_data(chip, nfc); + + chip->chip_delay = NFC_RB_DELAY_US; + chip->select_chip = rk_nfc_select_chip; + chip->cmd_ctrl = rk_nfc_cmd; + chip->read_buf = rk_nfc_read_buf; + chip->write_buf = rk_nfc_write_buf; + chip->read_byte = rockchip_nand_read_byte; + chip->dev_ready = rockchip_nand_dev_ready; + chip->controller = &nfc->controller; + + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; + + mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops); + rk_nfc_hw_init(nfc); + ret = nand_scan_ident(mtd, nsels, NULL); + if (ret) + return ret; + + ret = rk_nfc_ecc_init(nfc, chip); + if (ret) { + dev_err(dev, "rk_nfc_ecc_init failed: %d\n", ret); + return ret; + } + + ret = ofnode_read_u32(node, "rockchip,boot-blks", &tmp); + rknand->boot_blks = ret ? 0 : tmp; + + ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp); + rknand->boot_ecc = ret ? ecc->strength : tmp; + + rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps; + + if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) { + dev_err(dev, + "driver needs at least %d bytes of meta data\n", + NFC_SYS_DATA_SIZE + 2); + return -EIO; + } + + if (!nfc->page_buf) { + nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL); + if (!nfc->page_buf) + return -ENOMEM; + } + + if (!nfc->oob_buf) { + nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL); + if (!nfc->oob_buf) { + kfree(nfc->page_buf); + nfc->page_buf = NULL; + return -ENOMEM; + } + } + + ecc->read_page = rk_nfc_read_page_hwecc; + ecc->read_page_raw = rk_nfc_read_page_raw; + ecc->read_oob = rk_nfc_read_oob; + ecc->write_page = rk_nfc_write_page_hwecc; + ecc->write_page_raw = rk_nfc_write_page_raw; + ecc->write_oob = rk_nfc_write_oob; + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(dev, "nand_scan_tail failed: %d\n", ret); + return ret; + } + + return nand_register(devnum, mtd); +} + +static int rk_nfc_nand_chips_init(struct udevice *dev, struct rk_nfc *nfc) +{ + int ret, i = 0; + ofnode child; + + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + ret = rk_nfc_nand_chip_init(child, nfc, i++); + if (ret) + return ret; + } + + return 0; +} + +static struct nfc_cfg nfc_v6_cfg = { + .type = NFC_V6, + .ecc_strengths = {60, 40, 24, 16}, + .ecc_cfgs = { + 0x00040011, 0x00040001, 0x00000011, 0x00000001, + }, + .flctl_off = 0x08, + .bchctl_off = 0x0C, + .dma_cfg_off = 0x10, + .dma_data_buf_off = 0x14, + .dma_oob_buf_off = 0x18, + .dma_st_off = 0x1C, + .bch_st_off = 0x20, + .randmz_off = 0x150, + .int_en_off = 0x16C, + .int_clr_off = 0x170, + .int_st_off = 0x174, + .oob0_off = 0x200, + .oob1_off = 0x230, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x1F, + .low_bn = 5, + .high = 27, + .high_mask = 0x1, + }, + .ecc1 = { + .err_flag_bit = 15, + .low = 16, + .low_mask = 0x1F, + .low_bn = 5, + .high = 29, + .high_mask = 0x1, + }, +}; + +static struct nfc_cfg nfc_v8_cfg = { + .type = NFC_V8, + .ecc_strengths = {16, 16, 16, 16}, + .ecc_cfgs = { + 0x00000001, 0x00000001, 0x00000001, 0x00000001, + }, + .flctl_off = 0x08, + .bchctl_off = 0x0C, + .dma_cfg_off = 0x10, + .dma_data_buf_off = 0x14, + .dma_oob_buf_off = 0x18, + .dma_st_off = 0x1C, + .bch_st_off = 0x20, + .randmz_off = 0x150, + .int_en_off = 0x16C, + .int_clr_off = 0x170, + .int_st_off = 0x174, + .oob0_off = 0x200, + .oob1_off = 0x230, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x1F, + .low_bn = 5, + .high = 27, + .high_mask = 0x1, + }, + .ecc1 = { + .err_flag_bit = 15, + .low = 16, + .low_mask = 0x1F, + .low_bn = 5, + .high = 29, + .high_mask = 0x1, + }, +}; + +static struct nfc_cfg nfc_v9_cfg = { + .type = NFC_V9, + .ecc_strengths = {70, 60, 40, 16}, + .ecc_cfgs = { + 0x00000001, 0x06000001, 0x04000001, 0x02000001, + }, + .flctl_off = 0x10, + .bchctl_off = 0x20, + .dma_cfg_off = 0x30, + .dma_data_buf_off = 0x34, + .dma_oob_buf_off = 0x38, + .dma_st_off = 0x3C, + .bch_st_off = 0x150, + .randmz_off = 0x208, + .int_en_off = 0x120, + .int_clr_off = 0x124, + .int_st_off = 0x128, + .oob0_off = 0x200, + .oob1_off = 0x204, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x7F, + .low_bn = 7, + .high = 0, + .high_mask = 0x0, + }, + .ecc1 = { + .err_flag_bit = 18, + .low = 19, + .low_mask = 0x7F, + .low_bn = 7, + .high = 0, + .high_mask = 0x0, + }, +}; + +static const struct udevice_id rk_nfc_id_table[] = { + { + .compatible = "rockchip,px30-nfc", + .data = (unsigned long)&nfc_v9_cfg + }, + { + .compatible = "rockchip,rk2928-nfc", + .data = (unsigned long)&nfc_v6_cfg + }, + { + .compatible = "rockchip,rv1108-nfc", + .data = (unsigned long)&nfc_v8_cfg + }, + { + .compatible = "rockchip,rk3308-nfc", + .data = (unsigned long)&nfc_v8_cfg + }, + { /* sentinel */ } +}; + +static int rk_nfc_probe(struct udevice *dev) +{ + struct rk_nfc *nfc = dev_get_priv(dev); + int ret = 0; + + nfc->cfg = (void *)dev_get_driver_data(dev); + nfc->dev = dev; + + nfc->regs = (void *)dev_read_addr(dev); + if (IS_ERR(nfc->regs)) { + ret = PTR_ERR(nfc->regs); + goto release_nfc; + } + + nfc->nfc_clk = devm_clk_get(dev, "nfc"); + if (IS_ERR(nfc->nfc_clk)) { + dev_dbg(dev, "no NFC clk\n"); + /* Some earlier models, such as rk3066, have no NFC clk. */ + } + + nfc->ahb_clk = devm_clk_get(dev, "ahb"); + if (IS_ERR(nfc->ahb_clk)) { + dev_err(dev, "no ahb clk\n"); + ret = PTR_ERR(nfc->ahb_clk); + goto release_nfc; + } + + ret = rk_nfc_enable_clks(dev, nfc); + if (ret) + goto release_nfc; + + spin_lock_init(&nfc->controller.lock); + init_waitqueue_head(&nfc->controller.wq); + + rk_nfc_hw_init(nfc); + + ret = rk_nfc_nand_chips_init(dev, nfc); + if (ret) { + dev_err(dev, "failed to init NAND chips\n"); + goto clk_disable; + } + return 0; + +clk_disable: + rk_nfc_disable_clks(nfc); +release_nfc: + return ret; +} + +U_BOOT_DRIVER(rockchip_nfc) = { + .name = "rockchip_nfc", + .id = UCLASS_MTD, + .of_match = rk_nfc_id_table, + .probe = rk_nfc_probe, + .priv_auto = sizeof(struct rk_nfc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(rockchip_nfc), + &dev); + if (ret && ret != -ENODEV) + log_err("Failed to initialize ROCKCHIP NAND controller. (error %d)\n", + ret); +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + struct mtd_info *mtd; + size_t length = size; + + mtd = get_nand_dev_by_index(0); + return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst); +} + +void nand_deselect(void) {} From 88f7ca03b4a2dca45c33ae360c99f6dbe3fe394d Mon Sep 17 00:00:00 2001 From: Daniil Stas Date: Sun, 23 May 2021 22:24:49 +0000 Subject: [PATCH 117/250] spi: stm32_qspi: Fix short data write operation TCF flag only means that all data was sent to FIFO. To check if the data was sent out of FIFO we should also wait for the BUSY flag to be cleared. Otherwise there is a race condition which can lead to inability to write short (one byte long) data. Signed-off-by: Daniil Stas Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/spi/stm32_qspi.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 4acc9047b9e..8f4aabc3d16 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -148,23 +148,24 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv, const struct spi_mem_op *op) { u32 sr; - int ret; + int ret = 0; - if (!op->data.nbytes) - return _stm32_qspi_wait_for_not_busy(priv); - - ret = readl_poll_timeout(&priv->regs->sr, sr, - sr & STM32_QSPI_SR_TCF, - STM32_QSPI_CMD_TIMEOUT_US); - if (ret) { - log_err("cmd timeout (stat:%#x)\n", sr); - } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { - log_err("transfer error (stat:%#x)\n", sr); - ret = -EIO; + if (op->data.nbytes) { + ret = readl_poll_timeout(&priv->regs->sr, sr, + sr & STM32_QSPI_SR_TCF, + STM32_QSPI_CMD_TIMEOUT_US); + if (ret) { + log_err("cmd timeout (stat:%#x)\n", sr); + } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { + log_err("transfer error (stat:%#x)\n", sr); + ret = -EIO; + } + /* clear flags */ + writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr); } - /* clear flags */ - writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr); + if (!ret) + ret = _stm32_qspi_wait_for_not_busy(priv); return ret; } From 2dc41fccf347e8acba980d7bad1507cfadf11476 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 4 Mar 2021 17:47:56 +0100 Subject: [PATCH 118/250] dfu: dfu_mtd: set max_buf_size to erasesize also for NOR devices For NOR devices the logical DFU buffer size is the sector_size, as it is done in dfu_sf.c or in spi/sf_mtd.c (sf_mtd_info.erasesize = flash->sector_size) For NAND the DFU size was already limited to erasesize as has_pages = true. So the mtd dfu backend can use this erasesize for all the MTD devices, NOR and NAND with dfu->max_buf_size = mtd->erasesize This difference was initially copied from MTD command, where data is fully available in RAM without size limitation. This patch avoids to have many sector write in dfu_mtd.c at the end of the DFU transfer and avoids issues with USB timeout or WATCHDOG. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/dfu/dfu_mtd.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index ec40b8f6bba..894b5708753 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -254,7 +254,6 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) { char *st; struct mtd_info *mtd; - bool has_pages; int ret, part; mtd = get_mtd_device_nm(devstr); @@ -264,9 +263,7 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) dfu->dev_type = DFU_DEV_MTD; dfu->data.mtd.info = mtd; - - has_pages = mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH; - dfu->max_buf_size = has_pages ? mtd->erasesize : 0; + dfu->max_buf_size = mtd->erasesize; st = strsep(&s, " "); if (!strcmp(st, "raw")) { From 486808e354fc0e1982950817d6d54a601463f82e Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 4 Jun 2021 18:25:55 +0200 Subject: [PATCH 119/250] board: stm32mp1: correct the property name for eth Use the correct name for STMicroelectronics phys config properties, replace '_' by '-': "st,eth_clk_sel" => "st,eth-clk-sel" "st,eth-ref-clk-sel" => st,eth-clk-sel" These property name are aligned with the upstreamed Linux kernel binding: linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml See Linux kernel commit "dt-bindings: net: stmmac: add phys config properties" merged in v5.1-rc1. This patch allow to reuse the kernel device tree directly in U-Boot. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- board/dhelectronics/dh_stm32mp1/board.c | 4 ++-- board/st/stm32mp1/stm32mp1.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index ac1af718d4a..d7c1857c168 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -660,11 +660,11 @@ int board_interface_eth_init(struct udevice *dev, bool eth_ref_clk_sel_reg = false; /* Gigabit Ethernet 125MHz clock selection. */ - eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); /* Ethernet 50Mhz RMII clock selection */ eth_ref_clk_sel_reg = - dev_read_bool(dev, "st,eth_ref_clk_sel"); + dev_read_bool(dev, "st,eth-ref-clk-sel"); syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 261ec15e1b0..18b8870269f 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -733,11 +733,11 @@ int board_interface_eth_init(struct udevice *dev, bool eth_ref_clk_sel_reg = false; /* Gigabit Ethernet 125MHz clock selection. */ - eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); /* Ethernet 50Mhz RMII clock selection */ eth_ref_clk_sel_reg = - dev_read_bool(dev, "st,eth_ref_clk_sel"); + dev_read_bool(dev, "st,eth-ref-clk-sel"); syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); From 5f14e2fe9d70afac8aa6e87319e826c7b9daa489 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:04 +0200 Subject: [PATCH 120/250] stm32mp: stm32prog: remove all the header check for UART download This patch removes the header check for UART download; the check of checksum is not mandatory with even parity and chuck checksum for each 256 received bytes and it is only done for STM32 image (FSBL = TF-A BL2), not for FIT image. This patch solve issue of duplicated 0x100 byte written with FIP header. Fixes: 4fb7b3e10891 ("stm32mp: stm32prog: add FIP header support") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 14 +- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 5 - .../cmd_stm32prog/stm32prog_serial.c | 153 ++---------------- 3 files changed, 23 insertions(+), 149 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 4c4d8a7a69e..84b880261a3 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -369,23 +369,24 @@ static int parse_flash_layout(struct stm32prog_data *data, bool end_of_line, eof; char *p, *start, *last, *col; struct stm32prog_part_t *part; + struct image_header_s header; int part_list_size; int i; data->part_nb = 0; /* check if STM32image is detected */ - stm32prog_header_check((struct raw_header_s *)addr, &data->header); - if (data->header.type == HEADER_STM32IMAGE) { + stm32prog_header_check((struct raw_header_s *)addr, &header); + if (header.type == HEADER_STM32IMAGE) { u32 checksum; addr = addr + BL_HEADER_SIZE; - size = data->header.image_length; + size = header.image_length; - checksum = stm32prog_header_checksum(addr, &data->header); - if (checksum != data->header.image_checksum) { + checksum = stm32prog_header_checksum(addr, &header); + if (checksum != header.image_checksum) { stm32prog_err("Layout: invalid checksum : 0x%x expected 0x%x", - checksum, data->header.image_checksum); + checksum, header.image_checksum); return -EIO; } } @@ -1727,7 +1728,6 @@ void stm32prog_clean(struct stm32prog_data *data) free(data->part_array); free(data->otp_part); free(data->buffer); - free(data->header_data); } /* DFU callback: used after serial and direct DFU USB access */ diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 581b10d0ac9..ad404879a71 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -132,14 +132,9 @@ struct stm32prog_data { u32 *otp_part; u8 pmic_part[PMIC_SIZE]; - /* STM32 header information */ - struct raw_header_s *header_data; - struct image_header_s header; - /* SERIAL information */ u32 cursor; u32 packet_number; - u32 checksum; u8 *buffer; /* size = USART_RAM_BUFFER_SIZE*/ int dfu_seq; u8 read_phase; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 2b92e3b1498..7eca86c11b9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -292,56 +292,6 @@ static void stm32prog_serial_putc(u8 w_byte) } /* Helper function ************************************************/ - -static u8 stm32prog_header(struct stm32prog_data *data) -{ - u8 ret; - u8 boot = 0; - struct dfu_entity *dfu_entity; - u64 size = 0; - - dfu_entity = stm32prog_get_entity(data); - if (!dfu_entity) - return -ENODEV; - - printf("\nSTM32 download write %s\n", dfu_entity->name); - - /* force cleanup to avoid issue with previous read */ - dfu_transaction_cleanup(dfu_entity); - - stm32prog_header_check(data->header_data, &data->header); - - /* no stm32 image header : max size is partition size */ - if (data->header.type != HEADER_STM32IMAGE) { - dfu_entity->get_medium_size(dfu_entity, &size); - data->header.image_length = size; - } - - /**** Flash the header if necessary for boot partition */ - if (data->phase < PHASE_FIRST_USER) - boot = 1; - - /* write header if boot partition */ - if (boot) { - if (ret) { - stm32prog_err("invalid header (error %d)", ret); - } else { - ret = stm32prog_write(data, - (u8 *)data->header_data, - BL_HEADER_SIZE); - } - } else { - if (ret) - printf(" partition without checksum\n"); - ret = 0; - } - - free(data->header_data); - data->header_data = NULL; - - return ret; -} - static u8 stm32prog_start(struct stm32prog_data *data, u32 address) { u8 ret = 0; @@ -388,23 +338,6 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) data->dfu_seq = 0; printf("\n received length = 0x%x\n", data->cursor); - if (data->header.type == HEADER_STM32IMAGE) { - if (data->cursor != - (data->header.image_length + BL_HEADER_SIZE)) { - stm32prog_err("transmission interrupted (length=0x%x expected=0x%x)", - data->cursor, - data->header.image_length + - BL_HEADER_SIZE); - return -EIO; - } - if (data->header.image_checksum != data->checksum) { - stm32prog_err("invalid checksum received (0x%x expected 0x%x)", - data->checksum, - data->header.image_checksum); - return -EIO; - } - printf("\n checksum OK (0x%x)\n", data->checksum); - } /* update DFU with received flashlayout */ if (data->phase == PHASE_FLASHLAYOUT) @@ -627,14 +560,12 @@ static void download_command(struct stm32prog_data *data) u32 counter = 0x0, codesize = 0x0; u8 *ramaddress = 0; u8 rcv_data = 0x0; - struct image_header_s *image_header = &data->header; u32 cursor = data->cursor; long size = 0; u8 operation; u32 packet_number; u32 result = ACK_BYTE; u8 ret; - unsigned int i; bool error; int rcv; @@ -668,13 +599,8 @@ static void download_command(struct stm32prog_data *data) if (packet_number == 0) { /* erase: re-initialize the image_header struct */ data->packet_number = 0; - if (data->header_data) - memset(data->header_data, 0, BL_HEADER_SIZE); - else - data->header_data = calloc(1, BL_HEADER_SIZE); cursor = 0; data->cursor = 0; - data->checksum = 0; /*idx = cursor;*/ } else { data->packet_number++; @@ -746,74 +672,27 @@ static void download_command(struct stm32prog_data *data) goto end; } - /* Update current position in buffer */ - data->cursor += codesize; + switch (operation) { + case PHASE_OTP: + size = codesize; + ret = stm32prog_otp_write(data, cursor, data->buffer, &size); + break; - if (operation == PHASE_OTP) { - size = data->cursor - cursor; - /* no header for OTP */ - if (stm32prog_otp_write(data, cursor, - data->buffer, &size)) - result = ABORT_BYTE; - goto end; + case PHASE_PMIC: + size = codesize; + ret = stm32prog_pmic_write(data, cursor, data->buffer, &size); + break; + + default: + ret = stm32prog_write(data, data->buffer, codesize); + break; } - if (operation == PHASE_PMIC) { - size = data->cursor - cursor; - /* no header for PMIC */ - if (stm32prog_pmic_write(data, cursor, - data->buffer, &size)) - result = ABORT_BYTE; - goto end; - } - - if (cursor < BL_HEADER_SIZE) { - /* size = portion of header in this chunck */ - if (data->cursor >= BL_HEADER_SIZE) - size = BL_HEADER_SIZE - cursor; - else - size = data->cursor - cursor; - memcpy((void *)((u32)(data->header_data) + cursor), - data->buffer, size); - cursor += size; - - if (cursor == BL_HEADER_SIZE) { - /* Check and Write the header */ - if (stm32prog_header(data)) { - result = ABORT_BYTE; - goto end; - } - } else { - goto end; - } - } - - if (data->header.type == HEADER_STM32IMAGE) { - if (data->cursor <= BL_HEADER_SIZE) - goto end; - /* compute checksum on payload */ - for (i = (unsigned long)size; i < codesize; i++) - data->checksum += data->buffer[i]; - - if (data->cursor > - image_header->image_length + BL_HEADER_SIZE) { - log_err("expected size exceeded\n"); - result = ABORT_BYTE; - goto end; - } - - /* write data (payload) */ - ret = stm32prog_write(data, - &data->buffer[size], - codesize - size); - } else { - /* write all */ - ret = stm32prog_write(data, - data->buffer, - codesize); - } if (ret) result = ABORT_BYTE; + else + /* Update current position in buffer */ + data->cursor += codesize; end: stm32prog_serial_result(result); From d4358a648c5a785e708dbf23f0a67290ac22cf70 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:05 +0200 Subject: [PATCH 121/250] stm32mp: stm32prog: add timeout in stm32prog_serial_get_buffer Handle timeout in stm32prog_serial_get_buffer to sent NACK to STM32CubeProgrammer when the buffer is not fully received. This patch avoids to reach the STM32CubeProgrammer timeout and the associated unrecoverable error. Timeout error occurred while waiting for acknowledgment. Error: Write Operation fails at packet number 4165 at address 0x1044FF Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- .../mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 7eca86c11b9..2550ae6a2be 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -60,6 +60,9 @@ const u8 cmd_id[] = { #define NB_CMD sizeof(cmd_id) +/* with 115200 bauds, 20 ms allow to receive the 256 bytes buffer */ +#define TIMEOUT_SERIAL_BUFFER 30 + /* DFU support for serial *********************************************/ static struct dfu_entity *stm32prog_get_entity(struct stm32prog_data *data) { @@ -264,6 +267,7 @@ static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count) { struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); int err; + ulong start = get_timer(0); do { err = ops->getc(down_serial_dev); @@ -273,6 +277,10 @@ static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count) } else if (err == -EAGAIN) { ctrlc(); WATCHDOG_RESET(); + if (get_timer(start) > TIMEOUT_SERIAL_BUFFER) { + err = -ETIMEDOUT; + break; + } } else { break; } @@ -648,7 +656,7 @@ static void download_command(struct stm32prog_data *data) printf("transmission error on packet %d, byte %d\n", packet_number, codesize - counter); /* waiting end of packet before flush & NACK */ - mdelay(30); + mdelay(TIMEOUT_SERIAL_BUFFER); data->packet_number--; result = NACK_BYTE; goto end; @@ -666,7 +674,7 @@ static void download_command(struct stm32prog_data *data) /* wait to be sure that all data are received * in the FIFO before flush */ - mdelay(30); + mdelay(TIMEOUT_SERIAL_BUFFER); data->packet_number--; result = NACK_BYTE; goto end; From d68e53b2798962f7c53a9c11c9bf518b600a03af Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:06 +0200 Subject: [PATCH 122/250] stm32mp: stm32prog: add support of initrd in flashlayout Add the support in command stm32prog of kernel load and start with initrd file, identify by the partition Type "Binary" in the flashlayout.tsv, for example: - 0x01 fsbl Binary none 0x0 tfa.stm32 - 0x03 fip Binary none 0x0 fip.bin P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSystem ram0 0xC4000000 board.dtb P 0x12 initrd Binary ram0 0xC4400000 The file can be a legacy image "uInitrd", generated with mkimage, or a RAW initrd image "initrd.gz". After a DFU detach the bootm command with be executed with the associated address, for example: $> bootm 0xC2000000 0xC4400000: 0xC4000000 When the "Binary" partition type is absent, the 'bootm' command starts the kernel without ramdisk, for example: $> bootm 0xC2000000 - 0xC4000000 With this paths, it is no more mandatory to generate FIT including the kernel, DT and initrd: - 0x01 fsbl Binary none 0x0 tfa.stm32 - 0x03 fip Binary none 0x0 fip.bin P 0x10 fit System ram0 0xC2000000 fit.bin Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- .../cmd_stm32prog/cmd_stm32prog.c | 22 +++++++++++++------ .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 10 ++++++--- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 2 ++ 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index e36501a86b2..e584bb52bd6 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -45,7 +45,6 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, bool reset = false; struct image_header_s header; struct stm32prog_data *data; - u32 uimage, dtb; if (argc < 3 || argc > 5) return CMD_RET_USAGE; @@ -119,21 +118,23 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, goto cleanup; } - uimage = data->uimage; - dtb = data->dtb; - stm32prog_clean(data); free(stm32prog_data); stm32prog_data = NULL; puts("Download done\n"); - if (uimage) { + if (data->uimage) { char boot_addr_start[20]; char dtb_addr[20]; + char initrd_addr[40]; char *bootm_argv[5] = { "bootm", boot_addr_start, "-", dtb_addr, NULL }; + u32 uimage = data->uimage; + u32 dtb = data->dtb; + u32 initrd = data->initrd; + if (!dtb) bootm_argv[3] = env_get("fdtcontroladdr"); else @@ -142,8 +143,15 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, "0x%x", uimage); - printf("Booting kernel at %s - %s...\n\n\n", - boot_addr_start, bootm_argv[3]); + + if (initrd) { + snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%x:0x%x", + initrd, data->initrd_size); + bootm_argv[2] = initrd_addr; + } + + printf("Booting kernel at %s %s %s...\n\n\n", + boot_addr_start, bootm_argv[2], bootm_argv[3]); /* Try bootm for legacy and FIT format image */ if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, 4, bootm_argv); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 84b880261a3..ea69d5dd16b 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1473,7 +1473,7 @@ error: return ret; } -static void stm32prog_end_phase(struct stm32prog_data *data) +static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset) { if (data->phase == PHASE_FLASHLAYOUT) { if (parse_flash_layout(data, STM32_DDR_BASE, 0)) @@ -1489,6 +1489,10 @@ static void stm32prog_end_phase(struct stm32prog_data *data) data->uimage = data->cur_part->addr; if (data->cur_part->part_type == PART_FILESYSTEM) data->dtb = data->cur_part->addr; + if (data->cur_part->part_type == PART_BINARY) { + data->initrd = data->cur_part->addr; + data->initrd_size = offset; + } } if (CONFIG_IS_ENABLED(MMC) && @@ -1747,7 +1751,7 @@ void dfu_flush_callback(struct dfu_entity *dfu) if (dfu->dev_type == DFU_DEV_RAM) { if (dfu->alt == 0 && stm32prog_data->phase == PHASE_FLASHLAYOUT) { - stm32prog_end_phase(stm32prog_data); + stm32prog_end_phase(stm32prog_data, dfu->offset); /* waiting DFU DETACH for reenumeration */ } } @@ -1756,7 +1760,7 @@ void dfu_flush_callback(struct dfu_entity *dfu) return; if (dfu->alt == stm32prog_data->cur_part->alt_id) { - stm32prog_end_phase(stm32prog_data); + stm32prog_end_phase(stm32prog_data, dfu->offset); stm32prog_next_phase(stm32prog_data); } } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index ad404879a71..efb51a3022b 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -142,6 +142,8 @@ struct stm32prog_data { /* bootm information */ u32 uimage; u32 dtb; + u32 initrd; + u32 initrd_size; }; extern struct stm32prog_data *stm32prog_data; From 90ed215dd5d3fb4240fe3149eaf23530b6c37420 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:07 +0200 Subject: [PATCH 123/250] stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATURE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When CONFIG_FIT_SIGNATURE is activated, CONFIG_LEGACY_IMAGE_FORMAT is deactivated and the define IMAGE_FORMAT_LEGACY don't exist with include/image.h: #if defined(CONFIG_LEGACY_IMAGE_FORMAT) #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ #endif This patch adds the needed check on compilation flag CONFIG_LEGACY_IMAGE_FORMAT to avoid the compilation error for command stm32prog: cmd_stm32prog.c:81:8: error: ‘IMAGE_FORMAT_LEGACY’ undeclared (first use in this function); did you mean ‘IMAGE_FORMAT_FIT’? 81 | if (IMAGE_FORMAT_LEGACY == | ^~~~~~~~~~~~~~~~~~~ | IMAGE_FORMAT_FIT Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index e584bb52bd6..f3790f900ff 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -77,10 +77,12 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, if (header.type == HEADER_STM32IMAGE) { size = header.image_length + BL_HEADER_SIZE; +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) /* uImage detected in STM32IMAGE, execute the script */ if (IMAGE_FORMAT_LEGACY == genimg_get_format((void *)(addr + BL_HEADER_SIZE))) return image_source_script(addr + BL_HEADER_SIZE, "script@1"); +#endif } } From be4182bf23a73b29eb07496057f346e07534259c Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:08 +0200 Subject: [PATCH 124/250] stm32mp: stm32prog: handle the next phase after USB re-enumeration Handle the second USB enumeration only when the flashlayout is received and when phase is PHASE_FLASHLAYOUT. This patch removes the call of stm32prog_next_phase as it is already done in stm32prog_dfu_init(). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index bc44d9fc8f9..d4a3f7ea16f 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -207,13 +207,10 @@ bool stm32prog_usb_loop(struct stm32prog_data *data, int dev) if (stm32prog_data->phase == PHASE_FLASHLAYOUT) { ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); - if (ret || stm32prog_data->phase == PHASE_DO_RESET) + if (ret || stm32prog_data->phase != PHASE_FLASHLAYOUT) return ret; /* prepare the second enumeration with the FlashLayout */ - if (stm32prog_data->phase == PHASE_FLASHLAYOUT) - stm32prog_dfu_init(data); - /* found next selected partition */ - stm32prog_next_phase(data); + stm32prog_dfu_init(data); } ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); From b57efb24c9d05c04732f96b1330b2229769114e4 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:09 +0200 Subject: [PATCH 125/250] stm32mp: stm32prog: correctly handle DM_PMIC Correctly handle number of alternate when DM_PMIC is not activated. This patch remove the last UNKNOWN partition in this case. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Acked-by: Jaehoon Chung --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index ea69d5dd16b..ab687c272df 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1150,7 +1150,10 @@ static int dfu_init_entities(struct stm32prog_data *data) struct dfu_entity *dfu; int alt_nb; - alt_nb = 3; /* number of virtual = CMD, OTP, PMIC*/ + alt_nb = 2; /* number of virtual = CMD, OTP*/ + if (CONFIG_IS_ENABLED(DM_PMIC)) + alt_nb++; /* PMIC NVMEM*/ + if (data->part_nb == 0) alt_nb++; /* +1 for FlashLayout */ else From 69446dee3759e09dfaeb99673ad70d1556ed5972 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:10 +0200 Subject: [PATCH 126/250] stm32mp: stm32prog: use get_cpu_dev for GetID command Use get_cpu_dev() in uart getID command and remove the defines DEVICE_ID_BYTE1 and 2 defines. This patch prepare the support for new SOC family. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 2550ae6a2be..7de62668fee 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -19,8 +20,7 @@ /* - configuration part -----------------------------*/ #define USART_BL_VERSION 0x40 /* USART bootloader version V4.0*/ #define UBOOT_BL_VERSION 0x03 /* bootloader version V0.3*/ -#define DEVICE_ID_BYTE1 0x05 /* MSB byte of device ID*/ -#define DEVICE_ID_BYTE2 0x00 /* LSB byte of device ID*/ + #define USART_RAM_BUFFER_SIZE 256 /* Size of USART_RAM_Buf buffer*/ /* - Commands -----------------------------*/ @@ -436,10 +436,12 @@ static void get_version_command(struct stm32prog_data *data) */ static void get_id_command(struct stm32prog_data *data) { + u32 cpu = get_cpu_dev(); + /* Send Device IDCode */ stm32prog_serial_putc(0x1); - stm32prog_serial_putc(DEVICE_ID_BYTE1); - stm32prog_serial_putc(DEVICE_ID_BYTE2); + stm32prog_serial_putc((cpu >> 8) & 0xFF); + stm32prog_serial_putc(cpu & 0xFF); stm32prog_serial_result(ACK_BYTE); } From d4cb4025771e74dbf42c3aa0b6daa734f855928d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:11 +0200 Subject: [PATCH 127/250] stm32mp: stm32prog: change one message level to debug Move the message "Invalid or missing layout file." to debug level as it is a normal behavior and not an error and add the missing '\n'. This patch avoids the strange trace : Boot over usb0! Invalid or missing layout file.DFU alt info setting: done Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index f3790f900ff..feff73c79ef 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -99,7 +99,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, ret = stm32prog_init(data, addr, size); if (ret) - printf("Invalid or missing layout file."); + log_debug("Invalid or missing layout file at 0x%lx.\n", addr); /* prepare DFU for device read/write */ ret = stm32prog_dfu_init(data); From d4710326c814ffbf84eab87dce8f8fd789b0da18 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:12 +0200 Subject: [PATCH 128/250] dfu: add error callback Add error callback in dfu stack to manage some board specific behavior on DFU targets. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/dfu/dfu.c | 12 ++++++++++++ include/dfu.h | 11 +++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 213a20e7bcb..ff1859d9463 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -44,6 +44,14 @@ __weak void dfu_initiated_callback(struct dfu_entity *dfu) { } +/* + * The purpose of the dfu_error_callback() function is to + * provide callback for dfu user + */ +__weak void dfu_error_callback(struct dfu_entity *dfu, const char *msg) +{ +} + /* * The purpose of the dfu_usb_get_reset() function is to * provide information if after USB_DETACH request @@ -342,6 +350,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) printf("%s: Wrong sequence number! [%d] [%d]\n", __func__, dfu->i_blk_seq_num, blk_seq_num); dfu_transaction_cleanup(dfu); + dfu_error_callback(dfu, "Wrong sequence number"); return -1; } @@ -366,6 +375,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) ret = dfu_write_buffer_drain(dfu); if (ret) { dfu_transaction_cleanup(dfu); + dfu_error_callback(dfu, "DFU write error"); return ret; } } @@ -375,6 +385,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) pr_err("Buffer overflow! (0x%p + 0x%x > 0x%p)\n", dfu->i_buf, size, dfu->i_buf_end); dfu_transaction_cleanup(dfu); + dfu_error_callback(dfu, "Buffer overflow"); return -1; } @@ -386,6 +397,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) ret = dfu_write_buffer_drain(dfu); if (ret) { dfu_transaction_cleanup(dfu); + dfu_error_callback(dfu, "DFU write error"); return ret; } } diff --git a/include/dfu.h b/include/dfu.h index afada3959b7..f6868982df7 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -377,6 +377,17 @@ void dfu_initiated_callback(struct dfu_entity *dfu); */ void dfu_flush_callback(struct dfu_entity *dfu); +/** + * dfu_error_callback() - weak callback called at the DFU write error + * + * It is a callback function called by DFU stack after DFU write error. + * This function allows to manage some board specific behavior on DFU targets + * + * @dfu: pointer to the dfu_entity which cause the error + * @msg: the message of the error + */ +void dfu_error_callback(struct dfu_entity *dfu, const char *msg); + int dfu_transaction_initiate(struct dfu_entity *dfu, bool read); void dfu_transaction_cleanup(struct dfu_entity *dfu); From 1f2e3d5599704ea927453ac76a8675b607f32304 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 18 May 2021 15:12:13 +0200 Subject: [PATCH 129/250] stm32mp: stm32prog: handle dfu error Handle DFU stack error in STM32CubeProgrammer protocol. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index ab687c272df..f7c93a1298d 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1783,3 +1783,17 @@ void dfu_initiated_callback(struct dfu_entity *dfu) log_debug("dfu offset = 0x%llx\n", dfu->offset); } } + +void dfu_error_callback(struct dfu_entity *dfu, const char *msg) +{ + struct stm32prog_data *data = stm32prog_data; + + if (!stm32prog_data) + return; + + if (!stm32prog_data->cur_part) + return; + + if (dfu->alt == stm32prog_data->cur_part->alt_id) + stm32prog_err(msg); +} From c262522fd4ed453c079b09eb738ec4cbe4812478 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 27 Apr 2021 10:57:54 +0200 Subject: [PATCH 130/250] clk: cosmetic change in uclass Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index cac0f6a0122..14254212ca7 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -160,7 +160,7 @@ int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) { int i, ret, err, count; - + bulk->count = 0; count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0); From 95eca8612b7ba790dfe5d72ce3269ef3a7cdae84 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 14 Jun 2021 14:12:39 +0530 Subject: [PATCH 131/250] ARM: dts: k3-j7200-common-proc-board-u-boot.dtsi: Fix dtc warnings Fix following dtc warning by explicitly setting up #size-cells and #address-cells when overriding node in -u-boot.dtsi arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): /bus@100000/bus@28380000/mcu-navss/ringacc@2b800000:reg: property has invalid length (80 bytes) (#address-cells == 2, #size-cells == 1) Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 41ce9fcb59b..786cc480506 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -43,6 +43,8 @@ mcu-navss{ u-boot,dm-spl; + #address-cells = <2>; + #size-cells = <2>; ringacc@2b800000 { reg = <0x0 0x2b800000 0x0 0x400000>, From 06abbef27a31a81b254b2093b67d90e04ed273b0 Mon Sep 17 00:00:00 2001 From: zhengxun Date: Tue, 23 Mar 2021 13:16:47 +0000 Subject: [PATCH 132/250] mtd: spi-nor-ids: Add Macronix MX66UW2G345G The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence, add SPI_NOR_OCTAL_READ flag for this flash. Reviewed-by: Jagan Teki [jagan: change order of id flags] Signed-off-by: Jagan Teki Signed-off-by: zhengxun --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2b57797954c..8d2b73b6764 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -167,6 +167,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ From ca8bb0ccb752e38c49fc37e83af4857b04487ebb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 2 Jun 2021 12:40:45 +0200 Subject: [PATCH 133/250] gpio: pca953x: Add missing i2c dependency pca953x also depends on i2c that's why add dependency to Kconfig. Where GPIO is enabled but I2C compilation error pops up. Signed-off-by: Michal Simek Reviewed-by: Heiko Schocher --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d24884739bf..de4dc51d4b4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -396,7 +396,7 @@ config DM_74X164 config DM_PCA953X bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports" - depends on DM_GPIO + depends on DM_GPIO && DM_I2C help Say yes here to provide access to several register-oriented SMBus I/O expanders, made mostly by NXP or TI. Compatible From 01c7714a7bc615d054e2cd8ecb077415dbcf0a51 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Sun, 13 Jun 2021 20:55:53 +0200 Subject: [PATCH 134/250] zynqmp: spl: support DRAM ECC initialization Use the ZDMA channel 0 to initialize the DRAM banks. This avoid spurious ECC errors that can occur when accessing unitialized memory. The feature is enabled by setting the option CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data: SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex) SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex) Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/Kconfig | 35 ++++ arch/arm/mach-zynqmp/Makefile | 1 + arch/arm/mach-zynqmp/ecc_spl_init.c | 163 ++++++++++++++++++ .../mach-zynqmp/include/mach/ecc_spl_init.h | 13 ++ arch/arm/mach-zynqmp/include/mach/hardware.h | 2 + arch/arm/mach-zynqmp/spl.c | 4 + 6 files changed, 218 insertions(+) create mode 100644 arch/arm/mach-zynqmp/ecc_spl_init.c create mode 100644 arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index f1301f6661a..39144d654e3 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -92,6 +92,41 @@ config ZYNQMP_NO_DDR This option configures MMU with no DDR to avoid speculative access to DDR memory where DDR is not present. +config SPL_ZYNQMP_DRAM_ECC_INIT + bool "Initialize DRAM ECC" + depends on SPL + help + This option initializes all memory to 0xdeadbeef. Must be set if your + memory is of ECC type. + +config SPL_ZYNQMP_DRAM_BANK1_BASE + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank1 address" + default 0x00000000 + help + Start address of DRAM ECC bank1 + +config SPL_ZYNQMP_DRAM_BANK1_LEN + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank1 size" + default 0x80000000 + help + Size in bytes of the DRAM ECC bank1 + +config SPL_ZYNQMP_DRAM_BANK2_BASE + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank2 address" + default 0x800000000 + help + Start address of DRAM ECC bank2 + +config SPL_ZYNQMP_DRAM_BANK2_LEN + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank2 size" + default 0x0 + help + Size in bytes of the DRAM ECC bank2. A null size takes no action. + config SYS_MALLOC_F_LEN default 0x600 diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 8a3b0747244..eb6c5112b37 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -7,4 +7,5 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o +obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/arch/arm/mach-zynqmp/ecc_spl_init.c b/arch/arm/mach-zynqmp/ecc_spl_init.c new file mode 100644 index 00000000000..f547d8e3a5b --- /dev/null +++ b/arch/arm/mach-zynqmp/ecc_spl_init.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2015 - 2020 Xilinx, Inc. + * + * Jorge Ramirez-Ortiz + */ + +#include +#include +#include +#include +#include +#include + +#define ZDMA_TRANSFER_MAX_LEN (0x3FFFFFFFU - 7U) +#define ZDMA_CH_STATUS ((ADMA_CH0_BASEADDR) + 0x0000011CU) +#define ZDMA_CH_STATUS_STATE_MASK 0x00000003U +#define ZDMA_CH_STATUS_STATE_DONE 0x00000000U +#define ZDMA_CH_STATUS_STATE_ERR 0x00000003U +#define ZDMA_CH_CTRL0 ((ADMA_CH0_BASEADDR) + 0x00000110U) +#define ZDMA_CH_CTRL0_POINT_TYPE_MASK (u32)0x00000040U +#define ZDMA_CH_CTRL0_POINT_TYPE_NORMAL (u32)0x00000000U +#define ZDMA_CH_CTRL0_MODE_MASK (u32)0x00000030U +#define ZDMA_CH_CTRL0_MODE_WR_ONLY (u32)0x00000010U +#define ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT ((ADMA_CH0_BASEADDR) + 0x00000188U) +#define ZDMA_CH_WR_ONLY_WORD0 ((ADMA_CH0_BASEADDR) + 0x00000148U) +#define ZDMA_CH_WR_ONLY_WORD1 ((ADMA_CH0_BASEADDR) + 0x0000014CU) +#define ZDMA_CH_WR_ONLY_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000150U) +#define ZDMA_CH_WR_ONLY_WORD3 ((ADMA_CH0_BASEADDR) + 0x00000154U) +#define ZDMA_CH_DST_DSCR_WORD0 ((ADMA_CH0_BASEADDR) + 0x00000138U) +#define ZDMA_CH_DST_DSCR_WORD0_LSB_MASK 0xFFFFFFFFU +#define ZDMA_CH_DST_DSCR_WORD1 ((ADMA_CH0_BASEADDR) + 0x0000013CU) +#define ZDMA_CH_DST_DSCR_WORD1_MSB_MASK 0x0001FFFFU +#define ZDMA_CH_SRC_DSCR_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000130U) +#define ZDMA_CH_DST_DSCR_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000140U) +#define ZDMA_CH_CTRL2 ((ADMA_CH0_BASEADDR) + 0x00000200U) +#define ZDMA_CH_CTRL2_EN_MASK 0x00000001U +#define ZDMA_CH_ISR ((ADMA_CH0_BASEADDR) + 0x00000100U) +#define ZDMA_CH_ISR_DMA_DONE_MASK 0x00000400U +#define ECC_INIT_VAL_WORD 0xDEADBEEFU + +#define ZDMA_IDLE_TIMEOUT_USEC 1000000 +#define ZDMA_DONE_TIMEOUT_USEC 5000000 + +static void ecc_zdma_restore(void) +{ + /* Restore reset values for the DMA registers used */ + writel(ZDMA_CH_CTRL0, 0x00000080U); + writel(ZDMA_CH_WR_ONLY_WORD0, 0x00000000U); + writel(ZDMA_CH_WR_ONLY_WORD1, 0x00000000U); + writel(ZDMA_CH_WR_ONLY_WORD2, 0x00000000U); + writel(ZDMA_CH_WR_ONLY_WORD3, 0x00000000U); + writel(ZDMA_CH_DST_DSCR_WORD0, 0x00000000U); + writel(ZDMA_CH_DST_DSCR_WORD1, 0x00000000U); + writel(ZDMA_CH_SRC_DSCR_WORD2, 0x00000000U); + writel(ZDMA_CH_DST_DSCR_WORD2, 0x00000000U); + writel(ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT, 0x00000000U); +} + +static void ecc_dram_bank_init(u64 addr, u64 len) +{ + bool retry = true; + u32 timeout; + u64 bytes; + u32 size; + u64 src; + u32 reg; + + if (!len) + return; +retry: + bytes = len; + src = addr; + ecc_zdma_restore(); + while (bytes > 0) { + size = bytes > ZDMA_TRANSFER_MAX_LEN ? + ZDMA_TRANSFER_MAX_LEN : (u32)bytes; + + /* Wait until the DMA is in idle state */ + timeout = ZDMA_IDLE_TIMEOUT_USEC; + do { + udelay(1); + reg = readl(ZDMA_CH_STATUS); + reg &= ZDMA_CH_STATUS_STATE_MASK; + if (!timeout--) { + puts("error, ECC DMA failed to idle\n"); + goto done; + } + + } while ((reg != ZDMA_CH_STATUS_STATE_DONE) && + (reg != ZDMA_CH_STATUS_STATE_ERR)); + + /* Enable Simple (Write Only) Mode */ + reg = readl(ZDMA_CH_CTRL0); + reg &= (ZDMA_CH_CTRL0_POINT_TYPE_MASK | + ZDMA_CH_CTRL0_MODE_MASK); + reg |= (ZDMA_CH_CTRL0_POINT_TYPE_NORMAL | + ZDMA_CH_CTRL0_MODE_WR_ONLY); + writel(reg, ZDMA_CH_CTRL0); + + /* Fill in the data to be written */ + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD0); + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD1); + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD2); + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD3); + + /* Write Destination Address */ + writel((u32)(src & ZDMA_CH_DST_DSCR_WORD0_LSB_MASK), + ZDMA_CH_DST_DSCR_WORD0); + writel((u32)((src >> 32) & ZDMA_CH_DST_DSCR_WORD1_MSB_MASK), + ZDMA_CH_DST_DSCR_WORD1); + + /* Size to be Transferred. Recommended to set both src and dest sizes */ + writel(size, ZDMA_CH_SRC_DSCR_WORD2); + writel(size, ZDMA_CH_DST_DSCR_WORD2); + + /* DMA Enable */ + reg = readl(ZDMA_CH_CTRL2); + reg |= ZDMA_CH_CTRL2_EN_MASK; + writel(reg, ZDMA_CH_CTRL2); + + /* Check the status of the transfer by polling on DMA Done */ + timeout = ZDMA_DONE_TIMEOUT_USEC; + do { + udelay(1); + reg = readl(ZDMA_CH_ISR); + reg &= ZDMA_CH_ISR_DMA_DONE_MASK; + if (!timeout--) { + puts("error, ECC DMA timeout\n"); + goto done; + } + } while (reg != ZDMA_CH_ISR_DMA_DONE_MASK); + + /* Clear DMA status */ + reg = readl(ZDMA_CH_ISR); + reg |= ZDMA_CH_ISR_DMA_DONE_MASK; + writel(ZDMA_CH_ISR_DMA_DONE_MASK, ZDMA_CH_ISR); + + /* Read the channel status for errors */ + reg = readl(ZDMA_CH_STATUS); + if (reg == ZDMA_CH_STATUS_STATE_ERR) { + if (retry) { + retry = false; + goto retry; + } + puts("error, ECC DMA error\n"); + break; + } + + bytes -= size; + src += size; + } +done: + ecc_zdma_restore(); +} + +void zynqmp_ecc_init(void) +{ + ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK1_BASE, + CONFIG_SPL_ZYNQMP_DRAM_BANK1_LEN); + ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK2_BASE, + CONFIG_SPL_ZYNQMP_DRAM_BANK2_LEN); +} diff --git a/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h b/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h new file mode 100644 index 00000000000..b4b6fcf53bc --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2015 - 2020 Xilinx, Inc. + * + * Jorge Ramirez-Ortiz + */ + +#ifndef __ARCH_ZYNQMP_ECC_INIT_H +#define __ARCH_ZYNQMP_ECC_INIT_H + +void zynqmp_ecc_init(void); + +#endif diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index a798aa0eb99..37764990707 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -24,6 +24,8 @@ + 0x00000114) #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210 +#define ADMA_CH0_BASEADDR 0xFFA80000 + #define PS_MODE0 BIT(0) #define PS_MODE1 BIT(1) #define PS_MODE2 BIT(2) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 88386b23e5d..8fcae2c6a66 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -22,6 +23,9 @@ void board_init_f(ulong dummy) { board_early_init_f(); board_early_init_r(); +#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT + zynqmp_ecc_init(); +#endif } static void ps_mode_reset(ulong mode) From 742fdd1e6b4e94832e1cc3751a077babbaea090e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:04 +0100 Subject: [PATCH 135/250] ARM: zynq: Convert at25 binding to new description on zc770-xm013 The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding document to yaml") converted binding to yaml and 3 deprecated properties pop up. The patch is fixing these warnings: .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property >From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml by converting them to new binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com --- arch/arm/dts/zynq-zc770-xm013.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index bdf0c2f956d..7218ee3ad8e 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -68,13 +68,12 @@ num-cs = <4>; is-decoded-cs = <0>; eeprom: eeprom@2 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - compatible = "atmel,at25"; reg = <2>; spi-max-frequency = <1000000>; + size = <8192>; + address-width = <16>; + pagesize = <32>; }; }; From e246dc49cffb63667b5ec9ba02f74d9edf09c3a2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:03 +0100 Subject: [PATCH 136/250] ARM: zynq: Fix OCM mapping to be aligned with binding on zc702 The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to json-schema") converted binding to yaml and some missing required properties started to be reported. Align binding based on it. The patch is fixing these warnings: .../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property >From schema: .../Documentation/devicetree/bindings/sram/sram.yaml Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com --- arch/arm/dts/zynq-zc702.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index e45eba3d90b..4474f4bfd7b 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -68,6 +68,12 @@ ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; }; }; From aee1ed87e71e4e66a5874c32e700ab076c3d3c26 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 15 Apr 2021 05:12:15 -0600 Subject: [PATCH 137/250] arm64: zynqmp: Fix application loading on R5 core1 From U-Boot, loading application on RPU core 0 is fine but loading on core 1 is not handled properly. Lock-step mode needs both the R5 cores to be initialized and it is working fine. Whereas in SPLIT mode individual R5 cores needs to be initialized as they need to execute differenet applications. Handle both these lock-step and split modes by propagating mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions and by adding conditions in those functions. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/mp.c | 70 ++++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 656678a1551..74783ae5a78 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -37,6 +37,8 @@ #define ZYNQMP_CORE_APU0 0 #define ZYNQMP_CORE_APU3 3 +#define ZYNQMP_CORE_RPU0 4 +#define ZYNQMP_CORE_RPU1 5 #define ZYNQMP_MAX_CORES 6 @@ -54,18 +56,20 @@ int cpu_reset(u32 nr) return 0; } -static void set_r5_halt_mode(u8 halt, u8 mode) +static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) { u32 tmp; - tmp = readl(&rpu_base->rpu0_cfg); - if (halt == HALT) - tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; - else - tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; - writel(tmp, &rpu_base->rpu0_cfg); + if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) { + tmp = readl(&rpu_base->rpu0_cfg); + if (halt == HALT) + tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; + else + tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu0_cfg); + } - if (mode == LOCK) { + if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) { tmp = readl(&rpu_base->rpu1_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -93,30 +97,34 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void set_r5_reset(u8 mode) +static void set_r5_reset(u32 nr, u8 mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); + if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) + tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - if (mode == LOCK) - tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); writel(tmp, &crlapb_base->rst_lpd_top); } -static void release_r5_reset(u8 mode) +static void release_r5_reset(u32 nr, u8 mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); + if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) + tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - if (mode == LOCK) - tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); writel(tmp, &crlapb_base->rst_lpd_top); } @@ -141,7 +149,7 @@ int cpu_disable(u32 nr) val |= 1 << nr; writel(val, &crfapb_base->rst_fpd_apu); } else { - set_r5_reset(LOCK); + set_r5_reset(nr, SPLIT); } return 0; @@ -212,14 +220,14 @@ void initialize_tcm(bool mode) { if (!mode) { set_r5_tcm_mode(LOCK); - set_r5_halt_mode(HALT, LOCK); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK); enable_clock_r5(); - release_r5_reset(LOCK); + release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); } else { set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(HALT, SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); enable_clock_r5(); - release_r5_reset(SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); } } @@ -268,28 +276,28 @@ int cpu_release(u32 nr, int argc, char *const argv[]) if (!strncmp(argv[1], "lockstep", 8)) { printf("R5 lockstep mode\n"); - set_r5_reset(LOCK); + set_r5_reset(nr, LOCK); set_r5_tcm_mode(LOCK); - set_r5_halt_mode(HALT, LOCK); + set_r5_halt_mode(nr, HALT, LOCK); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(LOCK); + release_r5_reset(nr, LOCK); dcache_disable(); write_tcm_boot_trampoline(boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(RELEASE, LOCK); + set_r5_halt_mode(nr, RELEASE, LOCK); } else if (!strncmp(argv[1], "split", 5)) { printf("R5 split mode\n"); - set_r5_reset(SPLIT); + set_r5_reset(nr, SPLIT); set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(HALT, SPLIT); + set_r5_halt_mode(nr, HALT, SPLIT); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(SPLIT); + release_r5_reset(nr, SPLIT); dcache_disable(); write_tcm_boot_trampoline(boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(RELEASE, SPLIT); + set_r5_halt_mode(nr, RELEASE, SPLIT); } else { printf("Unsupported mode\n"); return 1; From 122ca834f2f4a9d70abeece3d1ff200a3556ab24 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 29 Apr 2021 08:02:30 -0600 Subject: [PATCH 138/250] arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc CONFIG_ZYNQMP_FIRMWARE enables zynqmp firmware driver. Signed-off-by: T Karthik Reddy --- configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 8837987e35e..5721e005d7c 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_ZYNQMP_FIRMWARE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ARM_DCC=y diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index b07dc040607..db06ea3ab64 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_ZYNQMP_FIRMWARE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ARM_DCC=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 4594f8096d3..bafbd8a3d31 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQMP_FIRMWARE=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index d7c64b9da53..ef2be75e1fa 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQMP_FIRMWARE=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y From ab09e16d5a4afb958d668554b56c5f717a92e9cd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 May 2021 13:58:58 +0200 Subject: [PATCH 139/250] arm64: zynqmp: Enable EFI secure boot Enabling EFI secure boot which is required for EBBR specification. Enabling this will fix "RT.SetVariable - Create one Time Base Auth Variable, the expect return status should be EFI_SUCCESS" Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 6adbe987cb7..997a2a785cd 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -189,3 +189,4 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y From ddf8deabc39db86c95d6d85afeb8689bf6fe1f90 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Oct 2020 09:35:40 +0200 Subject: [PATCH 140/250] arm64: zynqmp: Add support for SVD devices SVDs are using different name which can't be handled via zynqmp_devices structure. That's why introduce zynqmp_detect_svd_name() which checks ID code for these devices and show proper name for them. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ee4d0c85e6b..d3c68260d3f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -185,6 +185,32 @@ static const struct { }, }; +static const struct { + u32 id; + char *name; +} zynqmp_svd_devices[] = { + { + .id = 0x04714093, + .name = "xck24" + }, + { + .id = 0x04724093, + .name = "xck26", + }, +}; + +static char *zynqmp_detect_svd_name(u32 idcode) +{ + u32 i; + + for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) { + if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF)) + return zynqmp_svd_devices[i].name; + } + + return "unknown"; +} + static char *zynqmp_get_silicon_idcode_name(void) { u32 i; @@ -219,7 +245,7 @@ static char *zynqmp_get_silicon_idcode_name(void) } if (i >= ARRAY_SIZE(zynqmp_devices)) - return "unknown"; + return zynqmp_detect_svd_name(idcode); /* Add device prefix to the name */ ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d", From 351b9f5f9503c4441c9025162aced5c69025f084 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 11 May 2021 13:59:01 +0200 Subject: [PATCH 141/250] arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285 Enable gpio driver on these boards. GPIOs can be used on any board. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu1275-revA.dts | 4 ++++ arch/arm/dts/zynqmp-zcu1275-revB.dts | 4 ++++ arch/arm/dts/zynqmp-zcu1285-revA.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index cdd5c341878..b9a9d9802d9 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -39,6 +39,10 @@ status = "okay"; }; +&gpio { + status = "okay"; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 1de890c30f6..f14707419b4 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -64,6 +64,10 @@ }; }; +&gpio { + status = "okay"; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 21d62e993a3..42a73ea31ae 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -245,6 +245,10 @@ }; }; +&gpio { + status = "okay"; +}; + &qspi { status = "okay"; flash@0 { From 767aa16d41a94cfc39acbb796c300e575d4e3d4d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:01 +0100 Subject: [PATCH 142/250] ARM: zynq: Rename bus to be align with simple-bus yaml Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI point-to-point channels for communicating addresses, data, and response transactions between master and slave clients. This ARM AMBA 3.0..." Issues are reported as: .. amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' >From schema: ../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml Similar change has been done for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index c35eb2344fa..4dda753671c 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -95,7 +95,7 @@ }; }; - amba: amba { + amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; From 02ac1553b8329f866c1761f5d9fe66972817782c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 19 May 2021 13:02:20 +0200 Subject: [PATCH 143/250] arm64: zynqmp: Add psu_init_gpl for k26 boards Add psu_init_gpl file for getting SPL to work directly from the tree. Signed-off-by: Michal Simek --- .../zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 673 ++++++++++++++++++ board/xilinx/zynqmp/zynqmp-smk-k26-revA | 1 + 2 files changed, 674 insertions(+) create mode 100644 board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c create mode 120000 board/xilinx/zynqmp/zynqmp-smk-k26-revA diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c new file mode 100644 index 00000000000..c448f2abb1a --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102411U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07221008U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00311008U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xD4000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0001007EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33843384U, 0x02841284U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000006U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000007CU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00040000U); + psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00040000U); + psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U); + mask_delay(1); + psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0000U); + mask_delay(5); + psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U); + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + int cur_r006_trefprd; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + + cur_r006_trefprd = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-smk-k26-revA b/board/xilinx/zynqmp/zynqmp-smk-k26-revA new file mode 120000 index 00000000000..41c70a7f16f --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-smk-k26-revA @@ -0,0 +1 @@ +zynqmp-sm-k26-revA \ No newline at end of file From 476588c9b484d9483a1d309499cd83dad49cec73 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 19 May 2021 15:16:19 +0200 Subject: [PATCH 144/250] arm64: zynqmp: Handle MMC seq number based on boot device K26 has EMMC and SD and default 0 is not working when system is booting out of SD which is controller 1. Add controller autodetection via mmc_get_env_dev(). The same code is used for distro_boot selection done in board_late_init(). bootseq variable can't be reused because this is called so late. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 35 ++++++++++++++++++++++++++++ configs/xilinx_zynqmp_virt_defconfig | 1 + 2 files changed, 36 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d3c68260d3f..208eadef454 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -720,6 +720,41 @@ int checkboard(void) return 0; } +int mmc_get_env_dev(void) +{ + struct udevice *dev; + int bootseq = 0; + + switch (zynqmp_get_bootmode()) { + case EMMC_MODE: + case SD_MODE: + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@ff160000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, + "sdhci@ff160000", &dev)) { + return -1; + } + bootseq = dev_seq(dev); + break; + case SD1_LSHFT_MODE: + case SD_MODE1: + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@ff170000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, + "sdhci@ff170000", &dev)) { + return -1; + } + bootseq = dev_seq(dev); + break; + default: + break; + } + + debug("bootseq %d\n", bootseq); + + return bootseq; +} + enum env_location env_get_location(enum env_operation op, int prio) { u32 bootmode = zynqmp_get_bootmode(); diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 997a2a785cd..5f250c07e79 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -76,6 +76,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y From 1242a6b13d2eb24b2c9678a544ffd880c4c45d37 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 09:56:58 +0200 Subject: [PATCH 145/250] arm64: zynqmp: Update psgtr clocks index for boards Update the psgtr clock indexing for couple of zynqmp boards. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu100-revC.dts | 18 +++++++++--------- arch/arm/dts/zynqmp-zcu106-revA.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu111-revA.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu208-revA.dts | 6 +++--- arch/arm/dts/zynqmp-zcu216-revA.dts | 6 +++--- 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index b83696cccd2..3be69ad9bce 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -132,13 +132,13 @@ io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; - si5335a_0: clk26 { + si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5335a_1: clk27 { + si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -483,13 +483,6 @@ }; }; -&psgtr { - status = "okay"; - /* usb3, dps */ - clocks = <&si5335a_0>, <&si5335a_1>; - clock-names = "ref0", "ref1"; -}; - &rtc { status = "okay"; }; @@ -525,6 +518,13 @@ }; }; +&psgtr { + status = "okay"; + /* usb3, dp */ + clocks = <&si5335_0>, <&si5335_1>; + clock-names = "ref0", "ref1"; +}; + &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index ae20e581c0f..e86fef5be6f 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -958,13 +958,6 @@ }; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref1", "ref2", "ref3"; -}; - &qspi { status = "okay"; is-dual = <1>; @@ -995,6 +988,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref1", "ref2", "ref3"; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index d564f74344c..10bb45b49f1 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -773,13 +773,6 @@ }; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref1", "ref2", "ref3"; -}; - &qspi { status = "okay"; is-dual = <1>; @@ -810,6 +803,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, dp, usb3, sata */ + clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 880281d4e79..496e8d1de22 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -651,9 +651,9 @@ &psgtr { status = "okay"; - /* pcie, sata, usb3, dp */ - clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref0", "ref1", "ref2", "ref3"; + /* nc, nc, usb3, sata */ + clocks = <&si5341 0 2>, <&si5341 0 3>; + clock-names = "ref2", "ref3"; }; &rtc { diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index f899226ae19..3a205c08944 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -132,9 +132,9 @@ &psgtr { status = "okay"; - /* pcie, sata, usb3, dp */ - clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref0", "ref1", "ref2", "ref3"; + /* nc, nc, usb3, sata */ + clocks = <&si5341 0 2>, <&si5341 0 3>; + clock-names = "ref2", "ref3"; }; &dcc { From d9be8b4f2fab89234779921601d5bf9b9e719af0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 11 May 2020 10:14:34 +0200 Subject: [PATCH 146/250] arm64: zynqmp: Disable CCI by default There is no reason to have CCI no enabled by default. Enable it when your system configuration requires it. In Xilinx configuration flow this is work for Device Tree Generator which reads information from HW Design configuration. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 84d9770225a..db4099b7516 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -246,6 +246,7 @@ cci: cci@fd6e0000 { compatible = "arm,cci-400"; + status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; From ce42bd2fa3fc288e5eb9287fc4c924a13118b8e4 Mon Sep 17 00:00:00 2001 From: Stefano Stabellini Date: Wed, 5 May 2021 14:18:21 -0700 Subject: [PATCH 147/250] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi The SMMU is disabled in device tree so this change has no impact. The benefit is that this way it is in sync with xen.dtsi. Xen enables the SMMU and makes use of it. Signed-off-by: Stefano Stabellini --- arch/arm/dts/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index db4099b7516..37ee9539801 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -648,6 +648,8 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; From fee3e307f2d0e896e930c8694cef1374b03e8bd3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 May 2021 13:49:05 +0200 Subject: [PATCH 148/250] arm64: zynqmp: Add reset description for sata Sata needs to get reset before configuration that's why add property for it there. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 37ee9539801..345ab97e269 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -701,6 +701,7 @@ interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; From f2b5dd38de3d852a5723a63772794f13032a58f8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 May 2021 13:44:35 +0200 Subject: [PATCH 149/250] arm64: zynqmp: Move DP nodes to the end of file (zcu106) Just sync it with others for easier comparison. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu106-revA.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index e86fef5be6f..2fd41ad2d52 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -163,17 +163,6 @@ status = "okay"; }; -&zynqmp_dpdma { - status = "okay"; -}; - -&zynqmp_dpsub { - status = "okay"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 3>, - <&psgtr 0 PHY_TYPE_DP 1 3>; -}; - /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; @@ -1056,3 +1045,14 @@ &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; +}; From eca0376b5407f73c09122032e44c953a98341f39 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 09:42:08 +0200 Subject: [PATCH 150/250] arm64: zynqmp: Add label for zynqmp_ipi Add label which is used by bootloader for adding bootloader specific flag. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 345ab97e269..deb3fa3ab3f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -100,7 +100,7 @@ }; }; - zynqmp_ipi { + zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; From 447fb8db02021f57c710d492511b9adec72e026a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 09:50:01 +0200 Subject: [PATCH 151/250] arm64: zynqmp: Update Copyright years to 2021 Trivial change for all files I have touched recently. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index ef7cf0a36b2..65dd4e1f3a5 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 039a8da1a96..0c6a2a92dfe 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index d6e92480335..1a8cfdeb7f4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 46b27a00094..41ab20c3895 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 3be69ad9bce..cad1a23e953 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek * Nathalie Chan King Choy diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index ec61b7089da..7190e876d8d 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index c25ac9af48e..76c635f0d46 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index ce9d8fb3b81..f9eb4caaf8c 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 2fd41ad2d52..4da7a3edf54 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 10bb45b49f1..85821065dd4 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index b9a9d9802d9..10d8bc8f9a1 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index f14707419b4..97ae1b2d2d7 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 42a73ea31ae..eaf99a9fa82 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 496e8d1de22..03c84ae21ac 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 3a205c08944..fd1d9bfbd19 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index deb3fa3ab3f..47ffdf1b165 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2020, Xilinx, Inc. + * (C) Copyright 2014 - 2021, Xilinx, Inc. * * Michal Simek * From 43ef4c82fe4d9a4790b358b82de336f4dd5bf681 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 10:38:30 +0200 Subject: [PATCH 152/250] zynqmp: Enable regulators Enable command and fixed regulators. XDP platform is using them. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 5f250c07e79..dc5778fb470 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -61,6 +61,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y @@ -142,6 +143,8 @@ CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_SCSI=y From ce39ee28ec31b04c5c4e50d57a852ef8c1b2b26f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 11:03:19 +0200 Subject: [PATCH 153/250] zynqmp: Do not place u-boot to reserved memory location TF-A and SecureOS can allocate the part of DDR for self but U-Boot is not handling this configuration that the part of memory is reserved and shouldn't be used by U-Boot. That's why read all reserved memory locations and don't use it. The code was taken from commit 4a1b975dac02 ("board: stm32mp1: reserve memory for OP-TEE in device tree") and commit 1419e5b5167e ("stm32mp: update MMU config before the relocation") which is used by stm32 and does the job properly. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 208eadef454..7177c5a5a89 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -453,6 +455,25 @@ int dram_init(void) return 0; } + +ulong board_get_usable_ram_top(ulong total_size) +{ + phys_size_t size; + phys_addr_t reg; + struct lmb lmb; + + /* found enough not-reserved memory to relocated U-Boot */ + lmb_init(&lmb); + lmb_add(&lmb, gd->ram_base, gd->ram_size); + boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); + size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), + reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); + + if (!reg) + reg = gd->ram_top - size; + + return reg + size; +} #else int dram_init_banksize(void) { From 84c88d6ef2e8d03ed2d90884c9d931383d146852 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 11:13:45 +0200 Subject: [PATCH 154/250] zynqmp: Generate u-boot.its also with TEE dynamically The first change is to trying to find out TF-A load address based on reading elf file. Expectation is that bl31.bin is in the same folder as bl31.elf. It brings new flexibility to place TF-A to any address (DDR included). And also enable TEE generation also with TEE configuration. Expecation is the same as above that tee.bin and tee.elf are in the same folder. User has to just define link to BL31/BL32 binary files and the rest should be handled by the script. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 41 ++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh index 92e31849f88..700871dbe10 100755 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -8,9 +8,19 @@ BL33="u-boot-nodtb.bin" [ -z "$BL31" ] && BL31="bl31.bin" -# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/ { print $3 }' +BL31_ELF="${BL31%.*}.elf" +[ -f ${BL31_ELF} ] && ATF_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL31_ELF}" | \ +awk '/Entry point/ { print $3 }'` + [ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000" +[ -z "$BL32" ] && BL32="tee.bin" +BL32_ELF="${BL32%.*}.elf" +[ -f ${BL32_ELF} ] && TEE_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL32_ELF}" | \ +awk '/Entry point/ { print $3 }'` + +[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x60000000" + if [ -z "$BL33_LOAD_ADDR" ];then BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h` fi @@ -75,6 +85,24 @@ cat << __ATF __ATF fi +if [ -f $BL32 ]; then +cat << __TEE + tee { + description = "TEE firmware"; + data = /incbin/("$BL32"); + type = "firmware"; + os = "tee"; + arch = "arm64"; + compression = "none"; + load = <$TEE_LOAD_ADDR>; + entry = <$TEE_LOAD_ADDR>; + hash { + algo = "md5"; + }; + }; +__TEE +fi + DEFAULT=1 cnt=1 for dtname in $DT @@ -117,6 +145,16 @@ cat << __CONF_SECTION1_EOF }; __CONF_SECTION1_EOF else +if [ -f $BL32 ]; then +cat << __CONF_SECTION1_EOF + config_$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "atf"; + loadables = "uboot", "tee"; + fdt = "fdt_$cnt"; + }; +__CONF_SECTION1_EOF +else cat << __CONF_SECTION1_EOF config_$cnt { description = "$(basename $dtname .dtb)"; @@ -126,6 +164,7 @@ cat << __CONF_SECTION1_EOF }; __CONF_SECTION1_EOF fi +fi cnt=$((cnt+1)) done From 653736c2431317e07fce1e302f0a69d4d5b8b1a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 11:06:59 +0200 Subject: [PATCH 155/250] zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure There is need to pass entry about secure OS when bl32_entry is defined. Currently only 64bit support is added but /fit-images node have been extended to also record if this is 32bit or 64bit secure OS. When this is tested the code will be update to support this configuration too. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/handoff.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 7d7ab9da6ec..31346d9b2e2 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -71,6 +71,7 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, uintptr_t fdt_addr) { struct xfsbl_atf_handoff_params *atfhandoffparams; + u32 index = 0; atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE; atfhandoffparams->magic[0] = 'X'; @@ -78,14 +79,22 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, atfhandoffparams->magic[2] = 'N'; atfhandoffparams->magic[3] = 'X'; - atfhandoffparams->num_entries = 0; - if (bl33_entry) { - atfhandoffparams->partition[0].entry_point = bl33_entry; - atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << - FSBL_FLAGS_EL_SHIFT; - atfhandoffparams->num_entries++; + if (bl32_entry) { + atfhandoffparams->partition[index].entry_point = bl32_entry; + atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL1 << FSBL_FLAGS_EL_SHIFT | + FSBL_FLAGS_SECURE << FSBL_FLAGS_TZ_SHIFT; + index++; } + if (bl33_entry) { + atfhandoffparams->partition[index].entry_point = bl33_entry; + atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL2 << + FSBL_FLAGS_EL_SHIFT; + index++; + } + + atfhandoffparams->num_entries = index; + writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6); return NULL; From 02860e156272d11c57fe9e05e1c1a050d270775e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 14:41:23 +0200 Subject: [PATCH 156/250] zynqmp: Remove u-boot,dm-pre-reloc for uart instances Uarts already have u-boot,dm-pre-reloc via zynqmp.dtsi that's why there is no need to have them in platform DT files too. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-a2197-revA.dts | 1 - arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 -- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 -- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 -- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 -- 7 files changed, 11 deletions(-) diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts index 31531385425..27a9c60949a 100644 --- a/arch/arm/dts/zynqmp-a2197-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -35,7 +35,6 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 8ec2e866535..7bcdbdfdbb0 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -124,7 +124,6 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index f94b797d1a2..69a3901ccf6 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -75,7 +75,6 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &gem0 { /* eth MDIO 76/77 */ diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 213149a3dc8..a5db599c949 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -94,12 +94,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index c458110e5a8..58df328c987 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -90,12 +90,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index cee7ca1fa99..25d87532be7 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -90,12 +90,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 1f5201ac888..82d5ef83f76 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -68,12 +68,10 @@ &uart0 { /* uart0 MIO38-39 */ status = "okay"; - u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; - u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ From 7c3ad8f6a32cafd0732bfad31b2e53fd33666323 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 17:44:51 +0200 Subject: [PATCH 157/250] arm64: zynqmp: Remove additional header from zc1232 DT Remove unused phy.h from zc1232 DTS. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1232-revA.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 65dd4e1f3a5..7543855c9fd 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -11,7 +11,6 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" -#include / { model = "ZynqMP ZC1232 RevA"; From 184309b8c69efa9610d8a1de918672eb322bd5ba Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 May 2021 17:51:58 +0200 Subject: [PATCH 158/250] arm64: zynqmp: Add maximum-speed property for dwc3 nodes dwc3 can be used only for higher speeds than super-speed that's why explicitly set it up. This is also aligned with other ZynqMP dts files. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 + arch/arm/dts/zynqmp-zcu106-revA.dts | 1 + arch/arm/dts/zynqmp-zcu111-revA.dts | 1 + arch/arm/dts/zynqmp-zcu208-revA.dts | 1 + arch/arm/dts/zynqmp-zcu216-revA.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 0c6a2a92dfe..b0506c08418 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -433,6 +433,7 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 4da7a3edf54..d7140fc950e 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -1040,6 +1040,7 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; &watchdog0 { diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 85821065dd4..223bb8a6146 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -861,6 +861,7 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 03c84ae21ac..7607098ac07 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -701,4 +701,5 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index fd1d9bfbd19..7ba60da131f 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -705,4 +705,5 @@ snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + maximum-speed = "super-speed"; }; From 70fbcdb8254457efbf38b512beb395cbd8412f2e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Jun 2021 16:37:32 +0200 Subject: [PATCH 159/250] arm64: zynqmp: Remove addition newline from zc1751 dc1 Trivial patch. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index b0506c08418..8f361e47bda 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -443,4 +443,3 @@ &zynqmp_dpsub { status = "okay"; }; - From af04516992cf3e1f70843f372ceee932a9aebd97 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Jun 2021 16:40:43 +0200 Subject: [PATCH 160/250] arm64: zynqmp: Remove unused dp_aclk clock dp_aclk is not used anywhere that's why remove it. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 987792e5c51..b27b0aaf7c9 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -67,13 +67,6 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; - - dp_aclk: dp_aclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-accuracy = <100>; - }; }; &zynqmp_firmware { From abd30371d33ea187216e9bf2687496eda8a11de6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Jun 2021 16:42:02 +0200 Subject: [PATCH 161/250] arm64: zynqmp: Sync dp port location on zc1751 dc4 Historically dpdma and dpsub are placed at the end of files. Move nodes there for easier comparison among dts files. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index aadda179c32..48acea62c88 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -115,14 +115,6 @@ status = "okay"; }; -&zynqmp_dpsub { - status = "okay"; -}; - -&zynqmp_dpdma { - status = "okay"; -}; - &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -221,3 +213,11 @@ &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; From 5fa96722485c44dcbf29be800e03d15e84264816 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Jun 2021 16:42:50 +0200 Subject: [PATCH 162/250] arm64: zynqmp: Sync psgtr location on zcu100/zcu106 psgtr node should be below pinctrl for easier comparion among dts files. That's why move that nodes to different location. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu100-revC.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu106-revA.dts | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index cad1a23e953..45dd7da7179 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -483,6 +483,13 @@ }; }; +&psgtr { + status = "okay"; + /* usb3, dp */ + clocks = <&si5335_0>, <&si5335_1>; + clock-names = "ref0", "ref1"; +}; + &rtc { status = "okay"; }; @@ -518,13 +525,6 @@ }; }; -&psgtr { - status = "okay"; - /* usb3, dp */ - clocks = <&si5335_0>, <&si5335_1>; - clock-names = "ref0", "ref1"; -}; - &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index d7140fc950e..2b1255dc5f3 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -947,6 +947,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; is-dual = <1>; @@ -977,13 +984,6 @@ }; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; - clock-names = "ref1", "ref2", "ref3"; -}; - &rtc { status = "okay"; }; From ee6b3c54e96917411e10f7eb3f249e339d1536c3 Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Mon, 8 Mar 2021 14:05:19 +0530 Subject: [PATCH 163/250] arm64: zynqmp: rtc: Update rtc calibration value As per the design specification "The 16-bit Seconds Calibration Value represents the number of Oscillator Ticks that are required to measure the largest time period that is less than or equal to 1 second. For an oscillator that is 32.768 KHz, this value will be 0x7FFF." Signed-off-by: Srinivas Neeli Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 47ffdf1b165..d7e551630d6 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -691,7 +691,7 @@ interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; - calibration = <0x8000>; + calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { From 531abcb71e60d8a17e61612404478f365d64d13f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 11:46:50 +0200 Subject: [PATCH 164/250] xilinx: Convert xlnx,eeprom property to nvmem alias Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is done based on discussion in the link below. Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com Signed-off-by: Michal Simek --- arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 2 +- arch/arm/dts/zynq-syzygy-hub.dts | 2 +- arch/arm/dts/zynqmp-a2197-revA.dts | 3 ++- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 3 +-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 1 + arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- 17 files changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts index 85ab9e9e29a..6d1448e8697 100644 --- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts @@ -15,10 +15,10 @@ "xlnx,zynqmp"; chosen { stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; aliases { ethernet0 = &gem3; + nvmem0 = &eeprom; serial0 = &uart0; }; }; diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts index 55f8e8a2da4..cb878b0d0dc 100644 --- a/arch/arm/dts/zynq-syzygy-hub.dts +++ b/arch/arm/dts/zynq-syzygy-hub.dts @@ -16,6 +16,7 @@ ethernet0 = &gem0; serial0 = &uart0; mmc0 = &sdhci0; + nvmem0 = &eeprom; i2c0 = &i2c1; }; @@ -27,7 +28,6 @@ chosen { bootargs = ""; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; usb_phy0: phy0 { diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts index 27a9c60949a..89c3a281d0d 100644 --- a/arch/arm/dts/zynqmp-a2197-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -18,13 +18,14 @@ aliases { i2c0 = &i2c0; + nvmem0 = &eeprom1; + nvmem1 = &eeprom0; serial0 = &uart0; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 7bcdbdfdbb0..65ab67a32c0 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -24,6 +24,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -32,7 +33,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 69a3901ccf6..26eca135e1b 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -22,6 +22,7 @@ gpio0 = &gpio; i2c0 = &i2c0; mmc0 = &sdhci0; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -31,7 +32,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index a5db599c949..157c301951e 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -24,6 +24,7 @@ i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 58df328c987..cbdd69c2489 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -24,6 +24,7 @@ i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 25d87532be7..e4f92233340 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -24,6 +24,7 @@ i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 82d5ef83f76..fe759331528 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -25,6 +25,7 @@ i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,8 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; - /* xlnx,fmc-eeprom = FIXME */ }; memory@0 { diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e4cf382a497..7b8a8f83c49 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -27,6 +27,8 @@ i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; + nvmem0 = &eeprom; + nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -36,8 +38,6 @@ spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; - nvmem0 = &eeprom; - nvmem1 = &eeprom_cc; }; chosen { diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 7190e876d8d..1b08ac02afa 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -26,6 +26,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -37,7 +38,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 76c635f0d46..f368309d68f 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -24,6 +24,7 @@ gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index f9eb4caaf8c..9b816476a94 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -24,6 +24,7 @@ gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -35,7 +36,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 2b1255dc5f3..25076f4e78e 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -26,6 +26,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; @@ -37,7 +38,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 223bb8a6146..98488245fa2 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -26,6 +26,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -36,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 7607098ac07..82dc1dce68c 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -26,6 +26,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -36,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = &eeprom; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 7ba60da131f..bc54feadd54 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -26,6 +26,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; + nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; @@ -36,7 +37,6 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; - xlnx,eeprom = <&eeprom>; }; memory@0 { From 43086886ad5252d515542727d6cf5e27f63bcb34 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 11:58:08 +0200 Subject: [PATCH 165/250] arm64: zynqmp: Remove si5328 and si5382 nodes There are no drivers for these devices that's why remove that nodes completely. This change is done based on Linux kernel. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com --- arch/arm/dts/zynqmp-zcu102-revA.dts | 10 +--------- arch/arm/dts/zynqmp-zcu104-revA.dts | 5 +---- arch/arm/dts/zynqmp-zcu104-revC.dts | 5 +---- arch/arm/dts/zynqmp-zcu106-revA.dts | 20 +------------------- arch/arm/dts/zynqmp-zcu111-revA.dts | 5 +---- 5 files changed, 5 insertions(+), 40 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 1b08ac02afa..44e1b2877fd 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -605,15 +605,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - compatible = "silabs,si5328"; - reg = <0x69>; - /* - * Chip has interrupt present connected to PL - * interrupt-parent = <&>; - * interrupts = <>; - */ - }; + /* SI5328 - u20 */ }; /* 5 - 7 unconnected */ }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index f368309d68f..596251e9794 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -166,10 +166,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - compatible = "idt,8t49n287"; - reg = <0x6c>; - }; + /* 8T49N287 - u182 */ }; i2c@2 { diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 9b816476a94..6045b56e874 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -190,10 +190,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - compatible = "idt,8t49n287"; - reg = <0x6c>; - }; + /* 8T49N287 - u182 */ }; i2c@2 { diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 25076f4e78e..86ab94fb2f6 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -595,25 +595,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - reg = <0x69>; - /* - * Chip has interrupt present connected to PL - * interrupt-parent = <&>; - * interrupts = <>; - */ - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - clocks = <&refhdmi>; - clock-names = "xtal"; - clock-output-names = "si5328"; - - si5328_clk: clk0@0 { - reg = <0>; - clock-frequency = <27000000>; - }; - }; + /* SI5328 - u20 */ }; i2c@5 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 98488245fa2..84eb899ecb3 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -481,10 +481,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5382: clock-generator@69 { /* SI5382 - u48 */ - compatible = "silabs,si5382"; - reg = <0x69>; - }; + /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; From 0c79419d35ae71350ae2c1e41429f5c4cf274860 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 12:32:18 +0200 Subject: [PATCH 166/250] arm64: zynqmp: Remove can aliases from zc1751 Networking subsystem is not using aliases that's why remove them for CAN devices. There is also no any other Xilinx ZynqMP DT file with them. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 -- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 1a8cfdeb7f4..c70a8da022e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -19,8 +19,6 @@ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { - can0 = &can0; - can1 = &can1; ethernet0 = &gem2; gpio0 = &gpio; i2c0 = &i2c0; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 48acea62c88..cfcfe9327f4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -17,8 +17,6 @@ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { - can0 = &can0; - can1 = &can1; ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; From d245d0dfd8eb7cade37d6e2203ef6e9b7f9586d4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 13:46:27 +0200 Subject: [PATCH 167/250] arm64: zynqmp: Remove unused property from SD/USB Linux kernel is not using these properties that's why they can be removed. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index d7e551630d6..7de7166bd7f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -719,8 +719,6 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -737,8 +735,6 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -853,8 +849,6 @@ clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; ranges; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; @@ -879,8 +873,6 @@ clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; ranges; - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; From e0f99280ee097cebcc8d1f71551d639df6aad9bb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 14:12:05 +0200 Subject: [PATCH 168/250] arm64: zynqmp: Remove information about dma clock on zcu106 Clock setting is not static anymore that's why it depends on firmware setup that's why remove this comment. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu106-revA.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 86ab94fb2f6..a5f534f3be8 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -163,7 +163,6 @@ status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; From 6a2ce6ec247d05d2112057819f7680af64426231 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 15:18:04 +0200 Subject: [PATCH 169/250] arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1 psgtr node should be below pinctrl for easier comparion among dts files. That's why move that nodes to different location. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu104-revA.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu104-revC.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu111-revA.dts | 14 +++++++------- 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 8f361e47bda..48802532e01 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -60,13 +60,6 @@ }; }; -&psgtr { - status = "okay"; - /* dp, usb3, sata */ - clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &fpd_dma_chan1 { status = "okay"; }; @@ -345,6 +338,13 @@ }; }; +&psgtr { + status = "okay"; + /* dp, usb3, sata */ + clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 596251e9794..9f5f9994961 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -421,6 +421,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; flash@0 { @@ -450,13 +457,6 @@ }; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &rtc { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 6045b56e874..00d7c8cb098 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -433,6 +433,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; flash@0 { @@ -466,13 +473,6 @@ status = "okay"; }; -&psgtr { - status = "okay"; - /* nc, sata, usb3, dp */ - clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &sata { status = "okay"; /* SATA OOB timing settings */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 84eb899ecb3..2ac788a9476 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -770,6 +770,13 @@ }; }; +&psgtr { + status = "okay"; + /* nc, dp, usb3, sata */ + clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &qspi { status = "okay"; is-dual = <1>; @@ -800,13 +807,6 @@ }; }; -&psgtr { - status = "okay"; - /* nc, dp, usb3, sata */ - clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; - clock-names = "ref1", "ref2", "ref3"; -}; - &rtc { status = "okay"; }; From 4d3de8abff4dae76569751265fe8b636ac51138b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 Jun 2021 12:37:32 +0200 Subject: [PATCH 170/250] arm64: zynqmp: Add support for 64bit addresses in its Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also generate u-boot.its with 64bit load/entry addresses to also support different configurations. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh index 700871dbe10..592be7f6706 100755 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -13,6 +13,8 @@ BL31_ELF="${BL31%.*}.elf" awk '/Entry point/ { print $3 }'` [ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000" +ATF_LOAD_ADDR_LOW=`printf 0x%x $((ATF_LOAD_ADDR & 0xffffffff))` +ATF_LOAD_ADDR_HIGH=`printf 0x%x $((ATF_LOAD_ADDR >> 32))` [ -z "$BL32" ] && BL32="tee.bin" BL32_ELF="${BL32%.*}.elf" @@ -20,14 +22,20 @@ BL32_ELF="${BL32%.*}.elf" awk '/Entry point/ { print $3 }'` [ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x60000000" +TEE_LOAD_ADDR_LOW=`printf 0x%x $((TEE_LOAD_ADDR & 0xffffffff))` +TEE_LOAD_ADDR_HIGH=`printf 0x%x $((TEE_LOAD_ADDR >> 32))` if [ -z "$BL33_LOAD_ADDR" ];then BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h` fi +BL33_LOAD_ADDR_LOW=`printf 0x%x $((BL33_LOAD_ADDR & 0xffffffff))` +BL33_LOAD_ADDR_HIGH=`printf 0x%x $((BL33_LOAD_ADDR >> 32))` DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h` if [ ! -z "$DTB_LOAD_ADDR" ]; then - DTB_LOAD="load = <$DTB_LOAD_ADDR>;" + DTB_LOAD_ADDR_LOW=`printf 0x%x $((DTB_LOAD_ADDR & 0xffffffff))` + DTB_LOAD_ADDR_HIGH=`printf 0x%x $((DTB_LOAD_ADDR >> 32))` + DTB_LOAD="load = <$DTB_LOAD_ADDR_HIGH $DTB_LOAD_ADDR_LOW>;" else DTB_LOAD="" fi @@ -59,8 +67,8 @@ cat << __HEADER_EOF os = "u-boot"; arch = "arm64"; compression = "none"; - load = <$BL33_LOAD_ADDR>; - entry = <$BL33_LOAD_ADDR>; + load = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>; + entry = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>; hash { algo = "md5"; }; @@ -76,8 +84,8 @@ cat << __ATF os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; - load = <$ATF_LOAD_ADDR>; - entry = <$ATF_LOAD_ADDR>; + load = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>; + entry = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>; hash { algo = "md5"; }; @@ -94,8 +102,8 @@ cat << __TEE os = "tee"; arch = "arm64"; compression = "none"; - load = <$TEE_LOAD_ADDR>; - entry = <$TEE_LOAD_ADDR>; + load = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>; + entry = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>; hash { algo = "md5"; }; From 2b157d8127804d879d2624e1ed79085950957476 Mon Sep 17 00:00:00 2001 From: Zhengxun Date: Fri, 11 Jun 2021 15:10:48 +0000 Subject: [PATCH 171/250] clk: zynq: Add clock wizard driver The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by: Zhengxun Reviewed-by: Sean Anderson Signed-off-by: Michal Simek --- drivers/clk/Kconfig | 11 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-xlnx-clock-wizard.c | 186 ++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+) create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 40a5a5dd883..a0ac661f28f 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -128,6 +128,17 @@ config CLK_ZYNQ This clock driver adds support for clock related settings for Zynq platform. +config CLK_XLNX_CLKWZRD + bool "Xilinx Clocking Wizard" + depends on CLK + help + Support for the Xilinx Clocking Wizard IP core clock generator. + The wizard support for dynamically reconfiguring the clocking + primitives for Multiply, Divide, Phase Shift/Offset, or Duty + Cycle. Limited by U-Boot clk uclass without set_phase API and + set_duty_cycle API, this driver only supports set_rate to modify + the frequency. + config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 645709b855e..4fcc33953a9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o +obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c new file mode 100644 index 00000000000..70ee3af1074 --- /dev/null +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx 'Clocking Wizard' driver + * + * Copyright (c) 2021 Macronix Inc. + * + * Author: Zhengxun Li + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define SRR 0x0 + +#define SR 0x4 +#define SR_LOCKED BIT(0) + +#define CCR(x) (0x200 + ((x) * 4)) + +#define FBOUT_CFG CCR(0) +#define FBOUT_DIV(x) (x) +#define FBOUT_DIV_MASK GENMASK(7, 0) +#define FBOUT_GET_DIV(x) FIELD_GET(FBOUT_DIV_MASK, x) +#define FBOUT_MUL(x) ((x) << 8) +#define FBOUT_MUL_MASK GENMASK(15, 8) +#define FBOUT_GET_MUL(x) FIELD_GET(FBOUT_MUL_MASK, x) +#define FBOUT_FRAC(x) ((x) << 16) +#define FBOUT_FRAC_MASK GENMASK(25, 16) +#define FBOUT_GET_FRAC(x) FIELD_GET(FBOUT_FRAC_MASK, x) +#define FBOUT_FRAC_EN BIT(26) + +#define FBOUT_PHASE CCR(1) + +#define OUT_CFG(x) CCR(2 + ((x) * 3)) +#define OUT_DIV(x) (x) +#define OUT_DIV_MASK GENMASK(7, 0) +#define OUT_GET_DIV(x) FIELD_GET(OUT_DIV_MASK, x) +#define OUT_FRAC(x) ((x) << 8) +#define OUT_GET_MASK GENMASK(17, 8) +#define OUT_GET_FRAC(x) FIELD_GET(OUT_GET_MASK, x) +#define OUT_FRAC_EN BIT(18) + +#define OUT_PHASE(x) CCR(3 + ((x) * 3)) +#define OUT_DUTY(x) CCR(4 + ((x) * 3)) + +#define CTRL CCR(23) +#define CTRL_SEN BIT(2) +#define CTRL_SADDR BIT(1) +#define CTRL_LOAD BIT(0) + +/** + * struct clkwzrd - Clock wizard private data structure + * + * @base: memory base + * @vco_clk: voltage-controlled oscillator frequency + * + */ +struct clkwzd { + void *base; + u64 vco_clk; +}; + +struct clkwzd_plat { + fdt_addr_t addr; +}; + +static int clk_wzrd_enable(struct clk *clk) +{ + struct clkwzd *priv = dev_get_priv(clk->dev); + int ret; + u32 val; + + ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED, + 1, 100); + if (!ret) { + writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL); + writel(CTRL_SADDR, priv->base + CTRL); + ret = readl_poll_sleep_timeout(priv->base + SR, val, + val & SR_LOCKED, 1, 100); + } + + return ret; +} + +static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate) +{ + struct clkwzd *priv = dev_get_priv(clk->dev); + u64 div; + u32 cfg; + + /* Get output clock divide value */ + div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate); + if (div < 1000 || div > 255999) + return -EINVAL; + + cfg = OUT_DIV((u32)div / 1000); + + writel(cfg, priv->base + OUT_CFG(clk->id)); + + return 0; +} + +static struct clk_ops clk_wzrd_ops = { + .enable = clk_wzrd_enable, + .set_rate = clk_wzrd_set_rate, +}; + +static int clk_wzrd_probe(struct udevice *dev) +{ + struct clkwzd_plat *plat = dev_get_plat(dev); + struct clkwzd *priv = dev_get_priv(dev); + struct clk clk_in1; + u64 clock, vco_clk; + u32 cfg; + int ret; + + priv->base = (void *)plat->addr; + + ret = clk_get_by_name(dev, "clk_in1", &clk_in1); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk_in1); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + + ret = clk_enable(&clk_in1); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + clk_free(&clk_in1); + return ret; + } + + /* Read clock configuration registers */ + cfg = readl(priv->base + FBOUT_CFG); + + /* Recalculate VCO rate */ + if (cfg & FBOUT_FRAC_EN) + vco_clk = DIV_ROUND_DOWN_ULL(clock * + ((FBOUT_GET_MUL(cfg) * 1000) + + FBOUT_GET_FRAC(cfg)), + 1000); + else + vco_clk = clock * FBOUT_GET_MUL(cfg); + + priv->vco_clk = DIV_ROUND_DOWN_ULL(vco_clk, FBOUT_GET_DIV(cfg)); + + return 0; +} + +static int clk_wzrd_of_to_plat(struct udevice *dev) +{ + struct clkwzd_plat *plat = dev_get_plat(dev); + + plat->addr = dev_read_addr(dev); + if (plat->addr == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct udevice_id clk_wzrd_ids[] = { + { .compatible = "xlnx,clocking-wizard" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(clk_wzrd) = { + .name = "zynq-clk-wizard", + .id = UCLASS_CLK, + .of_match = clk_wzrd_ids, + .ops = &clk_wzrd_ops, + .probe = clk_wzrd_probe, + .of_to_plat = clk_wzrd_of_to_plat, + .priv_auto = sizeof(struct clkwzd), + .plat_auto = sizeof(struct clkwzd_plat), +}; From 3dbd53144c03f70cc0b24182f04bd0a44f320cb1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Jun 2021 18:52:14 +0200 Subject: [PATCH 172/250] arm64: zynqmp: Remove revA compatibility string from kv260 revB/1 kv260-revB is different compare to revA (usbhub is wired via i2c) that's why remove revA compatible string. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 6e46f5717b2..1393f997a01 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -17,7 +17,7 @@ /{ compatible = "xlnx,zynqmp-sk-kv260-rev1", - "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA", + "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; fragment1 { From b6d8d4b1007df5068e6c9e428b4665009486c181 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Jun 2021 17:59:46 +0200 Subject: [PATCH 173/250] arm64: zynqmp: Use overlay sugar syntax for Kria SOM dtc supports new sugar syntax which is easier compare to previous one that's why also covert overlays for SOM to it. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 622 ++++++++++++-------------- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 593 ++++++++++++------------ 2 files changed, 571 insertions(+), 644 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index cad2d057218..cca009e7c75 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -20,354 +20,316 @@ /dts-v1/; /plugin/; -/{ +&{/} { compatible = "xlnx,zynqmp-sk-kv260-revA", "xlnx,zynqmp-sk-kv260-revY", "xlnx,zynqmp-sk-kv260-revZ", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; +}; - fragment1 { - target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */ +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; - u14: ina260@40 { /* u14 */ - compatible = "ti,ina260"; - #io-channel-cells = <1>; - label = "ina260-u14"; - reg = <0x40>; - }; - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ - }; +&amba { + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; - fragment1a { - target = <&amba>; - __overlay__ { - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - - si5332_0: si5332_0 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - si5332_1: si5332_1 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - si5332_2: si5332_2 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - si5332_3: si5332_3 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - si5332_4: si5332_4 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - si5332_5: si5332_5 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - }; + si5332_0: si5332_0 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; }; + si5332_1: si5332_1 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_2: si5332_2 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5332_3: si5332_3 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + si5332_4: si5332_4 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_5: si5332_5 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + /* DP/USB 3.0 and SATA */ - fragment2 { - target = <&psgtr>; - __overlay__ { - status = "okay"; - /* pcie, usb3, sata */ - clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; - clock-names = "ref0", "ref1", "ref2"; - }; +&psgtr { + status = "okay"; + /* pcie, usb3, sata */ + clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; +}; + +&zynqmp_dpsub { + status = "disabled"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +}; + +&zynqmp_dpdma { + status = "okay"; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + usbhub: usb5744 { /* u43 */ + compatible = "microchip,usb5744"; + reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; +}; - fragment3 { - target = <&sata>; - __overlay__ { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - phy-names = "sata-phy"; - phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; - }; - }; +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + maximum-speed = "super-speed"; +}; - fragment4 { - target = <&zynqmp_dpsub>; - __overlay__ { - status = "disabled"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; - }; - }; +&sdhci1 { /* on CC with tuned parameters */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + /* + * SD 3.0 requires level shifter and this property + * should be removed if the board has level shifter and + * need to work in UHS mode + */ + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; +}; - fragment9 { - target = <&zynqmp_dpdma>; - __overlay__ { - status = "okay"; - }; - }; +&gem3 { /* required by spec */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; - fragment10 { - target = <&usb0>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; - usbhub: usb5744 { /* u43 */ - compatible = "microchip,usb5744"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; - }; - }; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; - fragment11 { - target = <&dwc3_0>; - __overlay__ { - status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - maximum-speed = "super-speed"; - }; - }; - - fragment12 { - target = <&sdhci1>; /* on CC with tuned parameters */ - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; - /* - * SD 3.0 requires level shifter and this property - * should be removed if the board has level shifter and - * need to work in UHS mode - */ - no-1-8-v; - disable-wp; - xlnx,mio-bank = <1>; - }; - }; - - fragment13 { - target = <&gem3>; /* required by spec */ - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - phy0: ethernet-phy@1 { - #phy-cells = <1>; - reg = <1>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,dp83867-rxctrl-strap-quirk; - }; - }; - }; - }; - - fragment14 { - target = <&pinctrl0>; /* required by spec */ - __overlay__ { - status = "okay"; - - pinctrl_uart1_default: uart1-default { - conf { - groups = "uart1_9_grp"; - slew-rate = ; - power-source = ; - drive-strength = <12>; - }; - - conf-rx { - pins = "MIO37"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO36"; - bias-disable; - }; - - mux { - groups = "uart1_9_grp"; - function = "uart1"; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - conf { - groups = "i2c1_6_grp"; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "i2c1_6_grp"; - function = "i2c1"; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - conf { - groups = "gpio0_24_grp", "gpio0_25_grp"; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "gpio0_24_grp", "gpio0_25_grp"; - function = "gpio0"; - }; - }; - - pinctrl_gem3_default: gem3-default { - conf { - groups = "ethernet3_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO70", "MIO72", "MIO74"; - bias-high-impedance; - low-power-disable; - }; - - conf-bootstrap { - pins = "MIO71", "MIO73", "MIO75"; - bias-disable; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", - "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - }; - - pinctrl_usb0_default: usb0-default { - conf { - groups = "usb0_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - conf { - groups = "sdio1_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - }; - }; - }; - fragment15 { - target = <&uart1>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; + phy0: ethernet-phy@1 { + #phy-cells = <1>; + reg = <1>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; }; }; }; + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem3_default: gem3-default { + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO72", "MIO74"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO71", "MIO73", "MIO75"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", + "MIO67", "MIO68", "MIO69"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 1393f997a01..d004ad14395 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -15,339 +15,304 @@ /dts-v1/; /plugin/; -/{ +&{/} { compatible = "xlnx,zynqmp-sk-kv260-rev1", "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; +}; - fragment1 { - target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */ +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + usbhub: usb5744@2d { /* u43 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; + }; + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; - u14: ina260@40 { /* u14 */ - compatible = "ti,ina260"; - #io-channel-cells = <1>; - label = "ina260-u14"; - reg = <0x40>; - }; - usbhub: usb5744@2d { /* u43 */ - compatible = "microchip,usb5744"; - reg = <0x2d>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ - }; +&amba { + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; - fragment1a { - target = <&amba>; - __overlay__ { - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - - si5332_0: si5332_0 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - si5332_1: si5332_1 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - si5332_2: si5332_2 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - si5332_3: si5332_3 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - si5332_4: si5332_4 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - si5332_5: si5332_5 { /* u17 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - }; + si5332_0: si5332_0 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; }; + si5332_1: si5332_1 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_2: si5332_2 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5332_3: si5332_3 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + si5332_4: si5332_4 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_5: si5332_5 { /* u17 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + /* DP/USB 3.0 */ - fragment2 { - target = <&psgtr>; - __overlay__ { - status = "okay"; - /* pcie, usb3, sata */ - clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; - clock-names = "ref0", "ref1", "ref2"; - }; - }; +&psgtr { + status = "okay"; + /* pcie, usb3, sata */ + clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; + clock-names = "ref0", "ref1", "ref2"; +}; - fragment4 { - target = <&zynqmp_dpsub>; - __overlay__ { - status = "disabled"; - phy-names = "dp-phy0", "dp-phy1"; - phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; - }; - }; +&zynqmp_dpsub { + status = "disabled"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; +}; - fragment9 { - target = <&zynqmp_dpdma>; - __overlay__ { - status = "okay"; - }; - }; +&zynqmp_dpdma { + status = "okay"; +}; - fragment10 { - target = <&usb0>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; - }; - }; +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; - fragment11 { - target = <&dwc3_0>; - __overlay__ { - status = "okay"; - dr_mode = "host"; - snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - maximum-speed = "super-speed"; - }; - }; +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + maximum-speed = "super-speed"; +}; - fragment12 { - target = <&sdhci1>; /* on CC with tuned parameters */ - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; - /* - * SD 3.0 requires level shifter and this property - * should be removed if the board has level shifter and - * need to work in UHS mode - */ - no-1-8-v; - disable-wp; - xlnx,mio-bank = <1>; - clk-phase-sd-hs = <126>, <60>; - clk-phase-uhs-sdr25 = <120>, <60>; - clk-phase-uhs-ddr50 = <126>, <48>; - }; - }; +&sdhci1 { /* on CC with tuned parameters */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; + /* + * SD 3.0 requires level shifter and this property + * should be removed if the board has level shifter and + * need to work in UHS mode + */ + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; + clk-phase-sd-hs = <126>, <60>; + clk-phase-uhs-sdr25 = <120>, <60>; + clk-phase-uhs-ddr50 = <126>, <48>; +}; - fragment13 { - target = <&gem3>; /* required by spec */ - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; +&gem3 { /* required by spec */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; - phy0: ethernet-phy@1 { - #phy-cells = <1>; - reg = <1>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,dp83867-rxctrl-strap-quirk; - }; - }; - }; - }; - - fragment14 { - target = <&pinctrl0>; /* required by spec */ - __overlay__ { - status = "okay"; - - pinctrl_uart1_default: uart1-default { - conf { - groups = "uart1_9_grp"; - slew-rate = ; - power-source = ; - drive-strength = <12>; - }; - - conf-rx { - pins = "MIO37"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO36"; - bias-disable; - }; - - mux { - groups = "uart1_9_grp"; - function = "uart1"; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - conf { - groups = "i2c1_6_grp"; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "i2c1_6_grp"; - function = "i2c1"; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - conf { - groups = "gpio0_24_grp", "gpio0_25_grp"; - slew-rate = ; - power-source = ; - }; - - mux { - groups = "gpio0_24_grp", "gpio0_25_grp"; - function = "gpio0"; - }; - }; - - pinctrl_gem3_default: gem3-default { - conf { - groups = "ethernet3_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO70", "MIO72", "MIO74"; - bias-high-impedance; - low-power-disable; - }; - - conf-bootstrap { - pins = "MIO71", "MIO73", "MIO75"; - bias-disable; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", - "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - }; - - pinctrl_usb0_default: usb0-default { - conf { - groups = "usb0_0_grp"; - slew-rate = ; - power-source = ; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - conf { - groups = "sdio1_0_grp"; - slew-rate = ; - power-source = ; - bias-disable; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - power-source = ; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - }; - }; - }; - fragment15 { - target = <&uart1>; - __overlay__ { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; + phy0: ethernet-phy@1 { + #phy-cells = <1>; + reg = <1>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; }; }; }; + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem3_default: gem3-default { + conf { + groups = "ethernet3_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO70", "MIO72", "MIO74"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO71", "MIO73", "MIO75"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", + "MIO67", "MIO68", "MIO69"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + conf { + groups = "sdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; From cb4380abfdeaf20c60bd732bde994851cc8d7520 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Jun 2021 08:51:19 +0200 Subject: [PATCH 174/250] arm64: zynqmp: Update usb dwc3 DT description Align USB nodes with the latest dt-bindings. It is adding resets, new interrupt and also some quirks. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 7de7166bd7f..1332f5373fb 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -848,6 +848,10 @@ reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_0: dwc3@fe200000 { @@ -855,11 +859,15 @@ status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupts = <0 65 4>, <0 69 4>; + interrupt-names = "dwc_usb3", "otg", "hiber"; + interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; + snps,enable_guctl1_resume_quirk; + snps,enable_guctl1_ipd_quirk; + snps,xhci-stream-quirk; /* dma-coherent; */ }; }; @@ -872,6 +880,10 @@ reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: dwc3@fe300000 { @@ -879,11 +891,15 @@ status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupts = <0 70 4>, <0 74 4>; + interrupt-names = "dwc_usb3", "otg", "hiber"; + interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; + snps,enable_guctl1_resume_quirk; + snps,enable_guctl1_ipd_quirk; + snps,xhci-stream-quirk; /* dma-coherent; */ }; }; From 83dc13384b19d1553320dda402f96f34f88c45b7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Jun 2021 08:52:25 +0200 Subject: [PATCH 175/250] arm64: zynqmp: Enable USB3.0 for dc2/dc3 Both boards are usb3.0 capable. dc3 was also missing enabling dwc3* nodes. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 ++ arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index c70a8da022e..b064b3b28b8 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -536,6 +536,8 @@ &dwc3_1 { status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; &uart0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index c7de59e1e98..6b19f5e5f57 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -200,11 +200,23 @@ &usb0 { status = "okay"; +}; + +&dwc3_0 { + status = "okay"; dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; - dr_mode = "host"; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; }; From 52caf2c12b870ea21fc11095e7a534c83cf848db Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Jun 2021 10:47:04 +0200 Subject: [PATCH 176/250] arm64: zynqmp: Remove gpio from aliases list It is not recommended to have aliases for gpio. In past it was used in Linux for assigning numbers via sysfs which is deprecated and libgpiod should be used instead. In U-Boot this number is used for seq number but gpio offset are not counted from this number. That's why having these aliases only for seq number is not needed. As is done in Linux it is the best to use full gpio name instead of sequence number which depends on sequence in binding. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 1 - arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-sm-k26-revA.dts | 1 - arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 3 +-- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 - arch/arm/dts/zynqmp-zcu100-revC.dts | 1 - arch/arm/dts/zynqmp-zcu102-revA.dts | 1 - arch/arm/dts/zynqmp-zcu104-revA.dts | 1 - arch/arm/dts/zynqmp-zcu104-revC.dts | 1 - arch/arm/dts/zynqmp-zcu106-revA.dts | 1 - arch/arm/dts/zynqmp-zcu111-revA.dts | 1 - arch/arm/dts/zynqmp-zcu208-revA.dts | 1 - arch/arm/dts/zynqmp-zcu216-revA.dts | 1 - 21 files changed, 1 insertion(+), 22 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 65ab67a32c0..bd0ba557e07 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -20,7 +20,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 26eca135e1b..ee530ba3e14 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; mmc0 = &sdhci0; nvmem0 = &eeprom; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 157c301951e..86f2ccf4d95 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index cbdd69c2489..e980fb07fc3 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index e4f92233340..c8c5100672f 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index fe759331528..d50b335e674 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -20,7 +20,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 7b8a8f83c49..b8a2249be42 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -22,7 +22,6 @@ "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index a377f27c50d..6ec96e0e8c9 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -19,7 +19,6 @@ "topic,miamimp", "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 48802532e01..f7dc0f7fb6f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index b064b3b28b8..5b689dbd093 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -20,7 +20,6 @@ aliases { ethernet0 = &gem2; - gpio0 = &gpio; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 6b19f5e5f57..a9bac1dec03 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -18,7 +18,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index cfcfe9327f4..f420f83ad20 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -21,7 +21,6 @@ ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 41ab20c3895..ae2d03d9832 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem1; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 45dd7da7179..2d615774782 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -23,7 +23,6 @@ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 44e1b2877fd..c1af5fc635e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 9f5f9994961..7e5eca82fda 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 00d7c8cb098..f4ebcbb318b 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index a5f534f3be8..ac6689c1673 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 2ac788a9476..8d57ca2b3bf 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 82dc1dce68c..d3e20ae85d7 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index bc54feadd54..ae7c1819689 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; From 9899f3e6b913ac76e0d70d1fc3617f0b0fb2b0e4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 Jun 2021 14:58:35 +0200 Subject: [PATCH 177/250] arm64: zynqmp: Add psgtr description to zc1751 dc1 board Wire psgtr for zc1751 dc1 board. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index f7dc0f7fb6f..b92a2ee3e60 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -441,4 +441,7 @@ &zynqmp_dpsub { status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, + <&psgtr 0 PHY_TYPE_DP 1 1>; }; From 3972ae65e43ad3a2a4f4c96cdaab5ca1863fe234 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 Jun 2021 15:07:07 +0200 Subject: [PATCH 178/250] arm64: zynqmp: Add missing year in Kria dts files DT files have been added this year but forgot to update it that's why do it in separate patch now. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index cca009e7c75..59d5751e063 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -2,7 +2,7 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * SD level shifter: * "A" – A01 board un-modified (NXP) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index d004ad14395..b5443afff98 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -2,7 +2,7 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi index 3f01233cc5a..467df9f23a1 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi +++ b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP K26/KV260 SD wiring * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index b8a2249be42..b613ab23425 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi index 8e9106792ff..34e6328fb66 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi +++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP Z2-VSOM * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index 300edc88009..c70966c1f34 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek */ From be2d1a87c73b3f722fc5b0438d780014579a43de Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 May 2021 11:40:09 +0200 Subject: [PATCH 179/250] spl: fit: Also record architecture in /fit-images On ARM64 secure OS can run as 64bit or 32bit that's why it is necessary to record information about architecture that other code can read it and properly pass it to TF-A and start in 64bit or 32bit mode. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- common/fdt_support.c | 4 +++- common/spl/spl_fit.c | 3 ++- include/fdt_support.h | 3 ++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index a9a32df1e78..240f1e57d13 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -594,7 +594,7 @@ void fdt_fixup_ethernet(void *fdt) int fdt_record_loadable(void *blob, u32 index, const char *name, uintptr_t load_addr, u32 size, uintptr_t entry_point, - const char *type, const char *os) + const char *type, const char *os, const char *arch) { int err, node; @@ -622,6 +622,8 @@ int fdt_record_loadable(void *blob, u32 index, const char *name, fdt_setprop_string(blob, node, "type", type); if (os) fdt_setprop_string(blob, node, "os", os); + if (arch) + fdt_setprop_string(blob, node, "arch", arch); return node; } diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index caddf511967..f6c475315ed 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -480,7 +480,8 @@ static int spl_fit_record_loadable(const struct spl_fit_info *ctx, int index, ret = fdt_record_loadable(blob, index, name, image->load_addr, image->size, image->entry_point, fdt_getprop(ctx->fit, node, "type", NULL), - fdt_getprop(ctx->fit, node, "os", NULL)); + fdt_getprop(ctx->fit, node, "os", NULL), + fdt_getprop(ctx->fit, node, "arch", NULL)); return ret; } diff --git a/include/fdt_support.h b/include/fdt_support.h index 1e4dbc0a8f6..f6f46bb8e9c 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -160,11 +160,12 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} * @param entry_point entry point (if specified, otherwise pass -1) * @param type type (if specified, otherwise pass NULL) * @param os os-type (if specified, otherwise pass NULL) + * @param arch architecture (if specified, otherwise pass NULL) * @return 0 if ok, or -1 or -FDT_ERR_... on error */ int fdt_record_loadable(void *blob, u32 index, const char *name, uintptr_t load_addr, u32 size, uintptr_t entry_point, - const char *type, const char *os); + const char *type, const char *os, const char *arch); #ifdef CONFIG_PCI #include From b388af9af459b049645aaecc8874721119b479b0 Mon Sep 17 00:00:00 2001 From: Jaime Liao Date: Mon, 7 Jun 2021 16:19:15 +0800 Subject: [PATCH 180/250] mtd: spinand: macronix: Add support for serial NAND flash Macronix NAND Flash devices are available in different configurations and densities. MX"35" means SPI NAND MX35"UF" , UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4) MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c). Signed-off-by: Jaime Liao Reviewed-by: Jagan Teki --- drivers/mtd/nand/spi/macronix.c | 46 +++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 215f09acc37..f4a8e816398 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,52 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_INFO("MX35UF4GE4AD", 0xb7, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AD", 0xa6, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AC", 0xa2, + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AD", 0x96, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AC", 0x92, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + }; static int macronix_spinand_detect(struct spinand_device *spinand) From 31a7b719d07ccb11950f423b5f1195375109b5fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:17 +0200 Subject: [PATCH 181/250] dm: core: add non-translating version of ofnode_get_addr_size_index() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add functions ofnode_get_addr_size_index_notrans(), which is a non-translating version of ofnode_get_addr_size_index(). Some addresses are not meant to be translated, for example those of MTD fixed-partitions. Signed-off-by: Marek Behún Reviewed-by: Simon Glass Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki --- drivers/core/ofnode.c | 19 ++++++++++++++++--- include/dm/ofnode.h | 17 +++++++++++++++++ test/dm/ofnode.c | 5 +++++ 3 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 6c771e364fb..dd34cf8ca3e 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -299,7 +299,8 @@ ofnode ofnode_get_by_phandle(uint phandle) return node; } -fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) +static fdt_addr_t __ofnode_get_addr_size_index(ofnode node, int index, + fdt_size_t *size, bool translate) { int na, ns; @@ -319,7 +320,7 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) ns = of_n_size_cells(ofnode_to_np(node)); - if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) { + if (translate && IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) { return of_translate_address(ofnode_to_np(node), prop_val); } else { na = of_n_addr_cells(ofnode_to_np(node)); @@ -330,12 +331,24 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) ns = ofnode_read_simple_size_cells(ofnode_get_parent(node)); return fdtdec_get_addr_size_fixed(gd->fdt_blob, ofnode_to_offset(node), "reg", - index, na, ns, size, true); + index, na, ns, size, + translate); } return FDT_ADDR_T_NONE; } +fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) +{ + return __ofnode_get_addr_size_index(node, index, size, true); +} + +fdt_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, + fdt_size_t *size) +{ + return __ofnode_get_addr_size_index(node, index, size, false); +} + fdt_addr_t ofnode_get_addr_index(ofnode node, int index) { fdt_size_t size; diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 8a69fd87da7..e3fccb506ea 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -489,6 +489,23 @@ int ofnode_read_size(ofnode node, const char *propname); phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size); +/** + * ofnode_get_addr_size_index_notrans() - get an address/size from a node + * based on index, without address + * translation + * + * This reads the register address/size from a node based on index. + * The resulting address is not translated. Useful for example for on-disk + * addresses. + * + * @node: node to read from + * @index: Index of address to read (0 for first) + * @size: Pointer to size of the address + * @return address, or FDT_ADDR_T_NONE if not present or invalid + */ +phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, + fdt_size_t *size); + /** * ofnode_get_addr_index() - get an address from a node * diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index e0b525eeb18..9a69cf70c1e 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -289,6 +289,11 @@ static int dm_test_ofnode_get_reg(struct unit_test_state *uts) ut_asserteq(FDT_ADDR_T_NONE, addr); ut_asserteq(FDT_SIZE_T_NONE, size); + node = ofnode_path("/translation-test@8000/noxlatebus@3,300/dev@42"); + ut_assert(ofnode_valid(node)); + addr = ofnode_get_addr_size_index_notrans(node, 0, &size); + ut_asserteq_64(0x42, addr); + return 0; } DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From 0e116bea52af1b665a656d49c328468e976be913 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:18 +0200 Subject: [PATCH 182/250] dm: core: add ofnode_get_path() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add function for retrieving full node path of a given ofnode. This uses np->full_name if OF is live, otherwise a call to fdt_get_path() is made. Signed-off-by: Marek Behún Reviewed-by: Simon Glass Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki --- drivers/core/ofnode.c | 25 +++++++++++++++++++++++++ include/dm/ofnode.h | 10 ++++++++++ test/dm/ofnode.c | 21 +++++++++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index dd34cf8ca3e..eeeccfb4467 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -286,6 +286,31 @@ const char *ofnode_get_name(ofnode node) return fdt_get_name(gd->fdt_blob, ofnode_to_offset(node), NULL); } +int ofnode_get_path(ofnode node, char *buf, int buflen) +{ + assert(ofnode_valid(node)); + + if (ofnode_is_np(node)) { + if (strlen(node.np->full_name) >= buflen) + return -ENOSPC; + + strcpy(buf, node.np->full_name); + + return 0; + } else { + int res; + + res = fdt_get_path(gd->fdt_blob, ofnode_to_offset(node), buf, + buflen); + if (!res) + return res; + else if (res == -FDT_ERR_NOSPACE) + return -ENOSPC; + else + return -EINVAL; + } +} + ofnode ofnode_get_by_phandle(uint phandle) { ofnode node; diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index e3fccb506ea..3da05d8b217 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -458,6 +458,16 @@ ofnode ofnode_get_parent(ofnode node); */ const char *ofnode_get_name(ofnode node); +/** + * ofnode_get_path() - get the full path of a node + * + * @node: valid node to look up + * @buf: buffer to write the node path into + * @buflen: buffer size + * @return 0 if OK, -ve on error + */ +int ofnode_get_path(ofnode node, char *buf, int buflen); + /** * ofnode_get_by_phandle() - get ofnode from phandle * diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 9a69cf70c1e..94a4d2189e8 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -297,3 +297,24 @@ static int dm_test_ofnode_get_reg(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +static int dm_test_ofnode_get_path(struct unit_test_state *uts) +{ + const char *path = "/translation-test@8000/noxlatebus@3,300/dev@42"; + char buf[64]; + ofnode node; + int res; + + node = ofnode_path(path); + ut_assert(ofnode_valid(node)); + + res = ofnode_get_path(node, buf, 64); + ut_asserteq(0, res); + ut_asserteq_str(path, buf); + + res = ofnode_get_path(node, buf, 32); + ut_asserteq(-ENOSPC, res); + + return 0; +} +DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From dc339bf784f08707583a5b6465381354f48d4fa8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:19 +0200 Subject: [PATCH 183/250] mtd: add support for parsing partitions defined in OF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for parsing partitions defined in device-trees via the `partitions` node with `fixed-partitions` compatible. The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions are defined for a MTD device via this mechanism, the code won't register partitions for that MTD device from OF, even if they are defined. Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- drivers/mtd/mtd_uboot.c | 106 +++++++++++++++++++++++----------------- drivers/mtd/mtdpart.c | 63 ++++++++++++++++++++++++ include/linux/mtd/mtd.h | 10 ++++ 3 files changed, 135 insertions(+), 44 deletions(-) diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index c53ec657a34..4843cf1b844 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -198,53 +198,11 @@ static void mtd_del_all_parts(void) } while (ret > 0); } -int mtd_probe_devices(void) +static int parse_mtdparts(const char *mtdparts, const char *mtdids) { - static char *old_mtdparts; - static char *old_mtdids; - const char *mtdparts = get_mtdparts(); - const char *mtdids = get_mtdids(); - const char *mtdparts_next = mtdparts; + const char *mtdparts_next; struct mtd_info *mtd; - mtd_probe_uclass_mtd_devs(); - - /* - * Check if mtdparts/mtdids changed, if the MTD dev list was updated - * or if our previous attempt to delete existing partititions failed. - * In any of these cases we want to update the partitions, otherwise, - * everything is up-to-date and we can return 0 directly. - */ - if ((!mtdparts && !old_mtdparts && !mtdids && !old_mtdids) || - (mtdparts && old_mtdparts && mtdids && old_mtdids && - !mtd_dev_list_updated() && !mtd_del_all_parts_failed && - !strcmp(mtdparts, old_mtdparts) && - !strcmp(mtdids, old_mtdids))) - return 0; - - /* Update the local copy of mtdparts */ - free(old_mtdparts); - free(old_mtdids); - old_mtdparts = strdup(mtdparts); - old_mtdids = strdup(mtdids); - - /* - * Remove all old parts. Note that partition removal can fail in case - * one of the partition is still being used by an MTD user, so this - * does not guarantee that all old partitions are gone. - */ - mtd_del_all_parts(); - - /* - * Call mtd_dev_list_updated() to clear updates generated by our own - * parts removal loop. - */ - mtd_dev_list_updated(); - - /* If either mtdparts or mtdids is empty, then exit */ - if (!mtdparts || !mtdids) - return 0; - /* Start the parsing by ignoring the extra 'mtdparts=' prefix, if any */ if (!strncmp(mtdparts, "mtdparts=", sizeof("mtdparts=") - 1)) mtdparts += 9; @@ -343,6 +301,66 @@ int mtd_probe_devices(void) put_mtd_device(mtd); } + return 0; +} + +int mtd_probe_devices(void) +{ + static char *old_mtdparts; + static char *old_mtdids; + const char *mtdparts = get_mtdparts(); + const char *mtdids = get_mtdids(); + struct mtd_info *mtd; + + mtd_probe_uclass_mtd_devs(); + + /* + * Check if mtdparts/mtdids changed, if the MTD dev list was updated + * or if our previous attempt to delete existing partititions failed. + * In any of these cases we want to update the partitions, otherwise, + * everything is up-to-date and we can return 0 directly. + */ + if ((!mtdparts && !old_mtdparts && !mtdids && !old_mtdids) || + (mtdparts && old_mtdparts && mtdids && old_mtdids && + !mtd_dev_list_updated() && !mtd_del_all_parts_failed && + !strcmp(mtdparts, old_mtdparts) && + !strcmp(mtdids, old_mtdids))) + return 0; + + /* Update the local copy of mtdparts */ + free(old_mtdparts); + free(old_mtdids); + old_mtdparts = strdup(mtdparts); + old_mtdids = strdup(mtdids); + + /* + * Remove all old parts. Note that partition removal can fail in case + * one of the partition is still being used by an MTD user, so this + * does not guarantee that all old partitions are gone. + */ + mtd_del_all_parts(); + + /* + * Call mtd_dev_list_updated() to clear updates generated by our own + * parts removal loop. + */ + mtd_dev_list_updated(); + + /* If both mtdparts and mtdids are non-empty, parse */ + if (mtdparts && mtdids) { + if (parse_mtdparts(mtdparts, mtdids) < 0) + printf("Failed parsing MTD partitions from mtdparts!\n"); + } + + /* Fallback to OF partitions */ + mtd_for_each_device(mtd) { + if (list_empty(&mtd->partitions)) { + if (add_mtd_partitions_of(mtd) < 0) + printf("Failed parsing MTD %s OF partitions!\n", + mtd->name); + } + } + /* * Call mtd_dev_list_updated() to clear updates generated by our own * parts registration loop. diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index d064ac30480..aa58f722dad 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -892,6 +892,69 @@ int add_mtd_partitions(struct mtd_info *master, return 0; } +#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(OF_CONTROL) +int add_mtd_partitions_of(struct mtd_info *master) +{ + ofnode parts, child; + int i = 0; + + if (!master->dev) + return 0; + + parts = ofnode_find_subnode(mtd_get_ofnode(master), "partitions"); + if (!ofnode_valid(parts) || !ofnode_is_available(parts) || + !ofnode_device_is_compatible(parts, "fixed-partitions")) + return 0; + + ofnode_for_each_subnode(child, parts) { + struct mtd_partition part = { 0 }; + struct mtd_info *slave; + fdt_addr_t offset, size; + + if (!ofnode_is_available(child)) + continue; + + offset = ofnode_get_addr_size_index_notrans(child, 0, &size); + if (offset == FDT_ADDR_T_NONE || !size) { + debug("Missing partition offset/size on \"%s\" partition\n", + master->name); + continue; + } + + part.name = ofnode_read_string(child, "label"); + if (!part.name) + part.name = ofnode_read_string(child, "name"); + + /* + * .mask_flags is used to remove flags in allocate_partition(), + * so when "read-only" is present, we add MTD_WRITABLE to the + * mask, and so MTD_WRITABLE will be removed on partition + * allocation + */ + if (ofnode_read_bool(child, "read-only")) + part.mask_flags |= MTD_WRITEABLE; + if (ofnode_read_bool(child, "lock")) + part.mask_flags |= MTD_POWERUP_LOCK; + + part.offset = offset; + part.size = size; + part.ecclayout = master->ecclayout; + + slave = allocate_partition(master, &part, i++, 0); + if (IS_ERR(slave)) + return PTR_ERR(slave); + + mutex_lock(&mtd_partitions_mutex); + list_add_tail(&slave->node, &master->partitions); + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(slave); + } + + return 0; +} +#endif /* CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(OF_CONTROL) */ + #ifndef __UBOOT__ static DEFINE_SPINLOCK(part_parser_lock); static LIST_HEAD(part_parsers); diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 927854950a0..3b302fb8c31 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -581,6 +581,16 @@ static inline int del_mtd_partitions(struct mtd_info *mtd) } #endif +#if defined(CONFIG_MTD_PARTITIONS) && CONFIG_IS_ENABLED(DM) && \ + CONFIG_IS_ENABLED(OF_CONTROL) +int add_mtd_partitions_of(struct mtd_info *master); +#else +static inline int add_mtd_partitions_of(struct mtd_info *master) +{ + return 0; +} +#endif + struct mtd_info *__mtd_next_device(int i); #define mtd_for_each_device(mtd) \ for ((mtd) = __mtd_next_device(0); \ From b7f060565e3161f8977a3a93e4b31ed6031af874 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:20 +0200 Subject: [PATCH 184/250] mtd: spi-nor: allow registering multiple MTDs when DM is enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently when the SPI_FLASH_MTD config option is enabled, only one SPI can be registered as MTD at any time - it is the last one probed (since with old non-DM model only one SPI NOR could be probed at any time). When DM is enabled, allow for registering multiple SPI NORs as MTDs by utilizing the nor->mtd structure, which is filled in by spi_nor_scan anyway, instead of filling a separate struct mtd_info. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- drivers/mtd/spi/sf_internal.h | 4 ++-- drivers/mtd/spi/sf_mtd.c | 18 +++++++++++++++++- drivers/mtd/spi/sf_probe.c | 6 ++++-- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 786301ba4a9..0b63e1bfc27 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -81,14 +81,14 @@ int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash); #if CONFIG_IS_ENABLED(SPI_FLASH_MTD) int spi_flash_mtd_register(struct spi_flash *flash); -void spi_flash_mtd_unregister(void); +void spi_flash_mtd_unregister(struct spi_flash *flash); #else static inline int spi_flash_mtd_register(struct spi_flash *flash) { return 0; } -static inline void spi_flash_mtd_unregister(void) +static inline void spi_flash_mtd_unregister(struct spi_flash *flash) { } #endif diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c index 987fac2501f..94854fbfc42 100644 --- a/drivers/mtd/spi/sf_mtd.c +++ b/drivers/mtd/spi/sf_mtd.c @@ -10,6 +10,20 @@ #include #include +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) + +int spi_flash_mtd_register(struct spi_flash *flash) +{ + return add_mtd_device(&flash->mtd); +} + +void spi_flash_mtd_unregister(struct spi_flash *flash) +{ + del_mtd_device(&flash->mtd); +} + +#else /* !CONFIG_IS_ENABLED(DM_SPI_FLASH) */ + static struct mtd_info sf_mtd_info; static bool sf_mtd_registered; static char sf_mtd_name[8]; @@ -123,7 +137,7 @@ int spi_flash_mtd_register(struct spi_flash *flash) return ret; } -void spi_flash_mtd_unregister(void) +void spi_flash_mtd_unregister(struct spi_flash *flash) { int ret; @@ -146,3 +160,5 @@ void spi_flash_mtd_unregister(void) printf("Failed to unregister MTD %s and the spi_flash object is going away: you're in deep trouble!", sf_mtd_info.name); } + +#endif /* !CONFIG_IS_ENABLED(DM_SPI_FLASH) */ diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 3befbe91cac..7edb8759fdc 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -84,7 +84,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs, void spi_flash_free(struct spi_flash *flash) { if (CONFIG_IS_ENABLED(SPI_FLASH_MTD)) - spi_flash_mtd_unregister(); + spi_flash_mtd_unregister(flash); spi_free_slave(flash->spi); free(flash); @@ -150,8 +150,10 @@ int spi_flash_std_probe(struct udevice *dev) static int spi_flash_std_remove(struct udevice *dev) { + struct spi_flash *flash = dev_get_uclass_priv(dev); + if (CONFIG_IS_ENABLED(SPI_FLASH_MTD)) - spi_flash_mtd_unregister(); + spi_flash_mtd_unregister(flash); return 0; } From 2d1a9a6b265f79be495201dadf7f3aa315b8a5e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:21 +0200 Subject: [PATCH 185/250] mtd: spi-nor: fill-in mtd->dev member MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fill in mtd->dev member with nor->dev. This can be used by MTD OF partition parser. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- drivers/mtd/spi/sf_mtd.c | 1 + drivers/mtd/spi/spi-nor-core.c | 1 + drivers/mtd/spi/spi-nor-tiny.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c index 94854fbfc42..04de8680809 100644 --- a/drivers/mtd/spi/sf_mtd.c +++ b/drivers/mtd/spi/sf_mtd.c @@ -125,6 +125,7 @@ int spi_flash_mtd_register(struct spi_flash *flash) sf_mtd_info.size = flash->size; sf_mtd_info.priv = flash; + sf_mtd_info.dev = flash->dev; /* Only uniform flash devices for now */ sf_mtd_info.numeraseregions = 0; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index a6625535a70..6af9c675a4f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2535,6 +2535,7 @@ int spi_nor_scan(struct spi_nor *nor) if (!mtd->name) mtd->name = info->name; + mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; mtd->writesize = 1; diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 1d5861d55cd..b0aa97d3244 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -751,6 +751,7 @@ int spi_nor_scan(struct spi_nor *nor) return ret; mtd->name = "spi-flash"; + mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; mtd->writesize = 1; From 69e57c4753dd5428e9e5ed6d1399c8532f744efc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:22 +0200 Subject: [PATCH 186/250] mtd: remove mtd_probe() function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The device_probe() function does the same thing as mtd_probe() and mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the probing can be made simpler by using uclass_foreach_dev_probe macro. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- drivers/mtd/mtd-uclass.c | 15 --------------- drivers/mtd/mtd_uboot.c | 9 +++------ include/mtd.h | 1 - 3 files changed, 3 insertions(+), 22 deletions(-) diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c index 9f5f672ba3f..4ab84de5531 100644 --- a/drivers/mtd/mtd-uclass.c +++ b/drivers/mtd/mtd-uclass.c @@ -9,21 +9,6 @@ #include #include -/** - * mtd_probe - Probe the device @dev if not already done - * - * @dev: U-Boot device to probe - * - * @return 0 on success, an error otherwise. - */ -int mtd_probe(struct udevice *dev) -{ - if (device_active(dev)) - return 0; - - return device_probe(dev); -} - /* * Implement a MTD uclass which should include most flash drivers. * The uclass private is pointed to mtd_info. diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 4843cf1b844..a652d431ba2 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -106,13 +107,9 @@ int mtd_search_alternate_name(const char *mtdname, char *altname, static void mtd_probe_uclass_mtd_devs(void) { struct udevice *dev; - int idx = 0; - /* Probe devices with DM compliant drivers */ - while (!uclass_find_device(UCLASS_MTD, idx, &dev) && dev) { - mtd_probe(dev); - idx++; - } + uclass_foreach_dev_probe(UCLASS_MTD, dev) + ; } #else static void mtd_probe_uclass_mtd_devs(void) { } diff --git a/include/mtd.h b/include/mtd.h index b0f8693386e..b569331edb0 100644 --- a/include/mtd.h +++ b/include/mtd.h @@ -8,7 +8,6 @@ #include -int mtd_probe(struct udevice *dev); int mtd_probe_devices(void); void board_mtdparts_default(const char **mtdids, const char **mtdparts); From 3c58c79b5ff1fb75780be18b86d1ae64b19c2136 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:23 +0200 Subject: [PATCH 187/250] mtd: probe SPI NOR devices in mtd_probe_devices() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order for `mtd list` U-Boot command to list SPI NOR devices without the need to run `sf probe` before, we have to probe SPI NOR devices in mtd_probe_devices(). Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- drivers/mtd/mtd_uboot.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index a652d431ba2..90767ec417a 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -115,6 +115,18 @@ static void mtd_probe_uclass_mtd_devs(void) static void mtd_probe_uclass_mtd_devs(void) { } #endif +#if IS_ENABLED(CONFIG_DM_SPI_FLASH) && IS_ENABLED(CONFIG_SPI_FLASH_MTD) +static void mtd_probe_uclass_spi_nor_devs(void) +{ + struct udevice *dev; + + uclass_foreach_dev_probe(UCLASS_SPI_FLASH, dev) + ; +} +#else +static void mtd_probe_uclass_spi_nor_devs(void) { } +#endif + #if defined(CONFIG_MTD_PARTITIONS) #define MTDPARTS_MAXLEN 512 @@ -310,6 +322,7 @@ int mtd_probe_devices(void) struct mtd_info *mtd; mtd_probe_uclass_mtd_devs(); + mtd_probe_uclass_spi_nor_devs(); /* * Check if mtdparts/mtdids changed, if the MTD dev list was updated @@ -370,6 +383,7 @@ int mtd_probe_devices(void) int mtd_probe_devices(void) { mtd_probe_uclass_mtd_devs(); + mtd_probe_uclass_spi_nor_devs(); return 0; } From 0b6f907d1543f1670460a797d62f49231b92ca98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:24 +0200 Subject: [PATCH 188/250] cmd: mtd: print device OF path in listing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Print MTD's device OF path in the output of `mtd list` command. Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- cmd/mtd.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/cmd/mtd.c b/cmd/mtd.c index 485a963bdd0..2aabfd4d298 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -126,6 +126,13 @@ static void mtd_show_device(struct mtd_info *mtd) printf(" - driver: %s\n", mtd->dev->driver->name); } #endif + if (IS_ENABLED(CONFIG_OF_CONTROL) && mtd->dev) { + char buf[256]; + int res; + + res = ofnode_get_path(mtd_get_ofnode(mtd), buf, 256); + printf(" - path: %s\n", res == 0 ? buf : "unavailable"); + } /* MTD device information */ printf(" - type: "); From dcb9a80359d699cf659c95b9b6e6604e2d68adb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:25 +0200 Subject: [PATCH 189/250] mtd: compare also with OF path and device name in get_mtd_device_nm() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The get_mtd_device_nm() function (code imported from Linux) simply iterates all registered MTD devices and compares the given name with all MTDs' names. With SPI_FLASH_MTD enabled U-Boot registers a SPI-NOR as a MTD device with name identical to the SPI flash chip name (from SPI ID table). Thus for a board with multiple same SPI-NORs it registers multiple MTDs, but all with the same name (such as "s25fl164k"). We do not want to change this behaviour, since such a change could break existing boot scripts, which can rely on a hardcoded name. In order to allow somehow to uniqely select a MTD device, change get_mtd_device_nm() function as such: - if first character of name is '/', try interpreting it as OF path - otherwise compare the name with MTDs name and MTDs device name. In the following example a board has two "s25fl164k" SPI-NORs. They both have name "s25fl164k", thus cannot be uniquely selected via this name. With this change, the user can select the second SPI-NOR either with "spi-nor@1" or "/soc/spi@10600/spi-nor@1". Example: => mtd list List of MTD devices: * s25fl164k - device: spi-nor@0 - parent: spi@10600 - driver: jedec_spi_nor - path: /soc/spi@10600/spi-nor@0 - type: NOR flash - block size: 0x1000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000000800000 : "s25fl164k" * s25fl164k - device: spi-nor@1 - parent: spi@10600 - driver: jedec_spi_nor - path: /soc/spi@10600/spi-nor@1 - type: NOR flash - block size: 0x1000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000000800000 : "s25fl164k" Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- drivers/mtd/mtdcore.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 0d1f94c6cba..582129d0df1 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -768,6 +768,32 @@ int __get_mtd_device(struct mtd_info *mtd) } EXPORT_SYMBOL_GPL(__get_mtd_device); +#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(OF_CONTROL) +static bool mtd_device_matches_name(struct mtd_info *mtd, const char *name) +{ + struct udevice *dev = NULL; + bool is_part; + + /* + * If the first character of mtd name is '/', try interpreting as OF + * path. Otherwise try comparing by mtd->name and mtd->dev->name. + */ + if (*name == '/') + device_get_global_by_ofnode(ofnode_path(name), &dev); + + is_part = mtd_is_partition(mtd); + + return (!is_part && dev && mtd->dev == dev) || + !strcmp(name, mtd->name) || + (is_part && mtd->dev && !strcmp(name, mtd->dev->name)); +} +#else +static bool mtd_device_matches_name(struct mtd_info *mtd, const char *name) +{ + return !strcmp(name, mtd->name); +} +#endif + /** * get_mtd_device_nm - obtain a validated handle for an MTD device by * device name @@ -784,10 +810,19 @@ struct mtd_info *get_mtd_device_nm(const char *name) mutex_lock(&mtd_table_mutex); mtd_for_each_device(other) { +#ifdef __UBOOT__ + if (mtd_device_matches_name(other, name)) { + if (mtd) + printf("\nWarning: MTD name \"%s\" is not unique!\n\n", + name); + mtd = other; + } +#else /* !__UBOOT__ */ if (!strcmp(name, other->name)) { mtd = other; break; } +#endif /* !__UBOOT__ */ } if (!mtd) From e41a2bc6b87397ef0aeda4132a8227d164cd592b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 26 May 2021 14:08:26 +0200 Subject: [PATCH 190/250] cmd: mtd: expand argument definition in command help MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The argument can now also be MTD's DM device name or OF path. Mention this is command help. Signed-off-by: Marek Behún Reviewed-by: Miquel Raynal Tested-by: Patrice Chotard Reviewed-by: Jagan Teki Cc: Priyanka Jain Cc: Simon Glass Cc: Heiko Schocher Cc: Patrick Delaunay --- cmd/mtd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mtd.c b/cmd/mtd.c index 2aabfd4d298..c22478c1527 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -542,7 +542,7 @@ static char mtd_help_text[] = "mtd bad \n" "\n" "With:\n" - "\t: NAND partition/chip name\n" + "\t: NAND partition/chip name (or corresponding DM device name or OF path)\n" "\t: user address from/to which data will be retrieved/stored\n" "\t: offset in in bytes (default: start of the part)\n" "\t\t* must be block-aligned for erase\n" From 44c78aa7ac0f4b22491350278f0dd77585416248 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 27 Apr 2021 19:52:53 +0200 Subject: [PATCH 191/250] clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value from cpg_pll_configs table while PLL{20,21,30,31,4} use different control offset. Introduce new types to handle this and handle those types in the Gen3 clock code. Based on "clk: renesas: Add support for R8A779A0 V3U PLLn" by Hai Pham Signed-off-by: Marek Vasut --- drivers/clk/renesas/clk-rcar-gen3.c | 24 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 9 +++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 7b42e28e838..c7dba341c13 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -253,6 +253,28 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, CPG_PLL4CR, 0, 0, "PLL4"); + case CLK_TYPE_R8A779A0_MAIN: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, 1, pll_config->extal_div, + "V3U_MAIN"); + + case CLK_TYPE_R8A779A0_PLL1: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, pll_config->pll1_mult, + pll_config->pll1_div, + "V3U_PLL1"); + + case CLK_TYPE_R8A779A0_PLL2X_3X: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + core->offset, 0, 0, + "V3U_PLL2X_3X"); + + case CLK_TYPE_R8A779A0_PLL5: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, pll_config->pll5_mult, + pll_config->pll5_div, + "V3U_PLL5"); + case CLK_TYPE_FF: return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, 0, core->mult, core->div, @@ -268,6 +290,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return rate; case CLK_TYPE_GEN3_SD: /* FIXME */ + fallthrough; + case CLK_TYPE_R8A779A0_SD: value = readl(priv->base + core->offset); value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 4fce0a99465..aa940a1ca2a 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -27,6 +27,13 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, + CLK_TYPE_R8A779A0_MAIN, + CLK_TYPE_R8A779A0_PLL1, + CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ + CLK_TYPE_R8A779A0_PLL5, + CLK_TYPE_R8A779A0_SD, + CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ + CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ /* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, @@ -69,6 +76,8 @@ struct rcar_gen3_cpg_pll_config { u8 pll3_mult; u8 pll3_div; u8 osc_prediv; + u8 pll5_mult; + u8 pll5_div; }; #define CPG_RST_MODEMR 0x060 From b092f96290539d98ebd2e9c159de8035a8142842 Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 11 Aug 2020 10:46:34 +0700 Subject: [PATCH 192/250] clk: renesas: Add R8A779A0 clock tables Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham Signed-off-by: Marek Vasut -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot --- drivers/clk/renesas/Kconfig | 6 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-rcar-gen3.c | 5 + drivers/clk/renesas/r8a779a0-cpg-mssr.c | 300 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 1 + drivers/clk/renesas/renesas-cpg-mssr.c | 4 + drivers/clk/renesas/renesas-cpg-mssr.h | 21 ++ 7 files changed, 338 insertions(+) create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 0c8b9eb47de..f4d6ef9f938 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -114,3 +114,9 @@ config CLK_R8A77995 depends on CLK_RCAR_GEN3 help Enable this to support the clocks on Renesas R8A77995 SoC. + +config CLK_R8A779A0 + bool "Renesas R8A779A0 clock driver" + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A779A0 SoC. diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index ed1a1252c40..36a5ca65f4b 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o +obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index c7dba341c13..6cf07fb4187 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -418,6 +418,11 @@ int gen3_clk_probe(struct udevice *dev) priv->info->control_regs = smstpcr; priv->info->reset_regs = srcr; priv->info->reset_clear_regs = srstclr; + } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) { + priv->info->status_regs = mstpsr_for_v3u; + priv->info->control_regs = mstpcr_for_v3u; + priv->info->reset_regs = srcr_for_v3u; + priv->info->reset_clear_regs = srstclr_for_v3u; } else { return -EINVAL; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c new file mode 100644 index 00000000000..bda69952362 --- /dev/null +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL20, + CLK_PLL21, + CLK_PLL30, + CLK_PLL31, + CLK_PLL5, + CLK_PLL1_DIV2, + CLK_PLL20_DIV2, + CLK_PLL21_DIV2, + CLK_PLL30_DIV2, + CLK_PLL31_DIV2, + CLK_PLL5_DIV2, + CLK_PLL5_DIV4, + CLK_S1, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_OCO, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +#define DEF_PLL(_name, _id, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ + .offset = _offset) + +#define DEF_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) + +#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ + (_parent0) << 16 | (_parent1), \ + .div = (_div0) << 16 | (_div1), .offset = _md) + +#define DEF_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) + +static const struct cpg_core_clk r8a779a0_core_clks[] = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), + DEF_PLL(".pll20", CLK_PLL20, 0x0834), + DEF_PLL(".pll21", CLK_PLL21, 0x0838), + DEF_PLL(".pll30", CLK_PLL30, 0x083c), + DEF_PLL(".pll31", CLK_PLL31, 0x0840), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), + DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), + DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), + DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), + DEF_RATE(".oco", CLK_OCO, 32768), + + /* Core Clock Outputs */ + DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), + DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), + DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), + DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), + DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), + DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), + DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), + DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), + DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), + DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), + + DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), + + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), + DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), + + DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), + DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), +}; + +static const struct mssr_mod_clk r8a779a0_mod_clks[] = { + DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), + DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), + DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2), + DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), + DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), + DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), + DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), + DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), + DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), + DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), + DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), + DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), + DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2), + DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2), + DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2), + DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2), + DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4), + DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4), + DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4), + DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4), + DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), + DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), + DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), + DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), + DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), + DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), + DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), + DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), + DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), + DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), + DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), + DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), + DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), + DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), + DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), + DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), + DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), + DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), + DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), + DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), + DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), + DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), + DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), + DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), + DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), + DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), + DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), + DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), + DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), + DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), + DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), + DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), + DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), + DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), + DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), + DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), + DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), + DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), + DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), + DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), + DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), + DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), + DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), + DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), + DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), + DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), + DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), + DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), + DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), + DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), + DEF_MOD("rwdt", 907, R8A779A0_CLK_R), + DEF_MOD("pfc0", 915, R8A779A0_CLK_CP), + DEF_MOD("pfc1", 916, R8A779A0_CLK_CP), + DEF_MOD("pfc2", 917, R8A779A0_CLK_CP), + DEF_MOD("pfc3", 918, R8A779A0_CLK_CP), + DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), + DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), + DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), + DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC + * 14 13 (MHz) 21 31 + * -------------------------------------------------------- + * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 + * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 + * 1 0 Prohibited setting + * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div Not used OSC prediv PLL5 mult/div */ + { 1, 128, 1, 128, 1, 16, 192, 1, }, + { 1, 106, 1, 106, 1, 19, 160, 1, }, + { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 128, 1, 128, 1, 32, 192, 1, }, +}; + +/* + * Note that the only clock left running before booting Linux are now + * MFIS, INTC-AP, INTC-EX and SCIF0 on V3U + */ +#define MSTPCR7_SCIF0 BIT(2) +#define MSTPCR6_MFIS BIT(17) +#define MSTPCR6_INTC BIT(11) /* No information: INTC-AP, INTC-EX */ + +static const struct mstp_stop_table r8a779a0_mstp_table[] = { + { 0x003f7ffe, 0x0, 0x0, 0x0 }, + { 0x00cb0000, 0x0, 0x0, 0x0 }, + { 0x0001f800, 0x0, 0x0, 0x0 }, + { 0x90000000, 0x0, 0x0, 0x0 }, + { 0x0001c807, 0x0, 0x0, 0x0 }, + { 0x7e03c380, 0x0, 0x0, 0x0 }, + { 0x1f01f001, MSTPCR6_MFIS, 0x0, 0x0 }, + { 0xffffe040, MSTPCR7_SCIF0, 0x0, 0x0 }, + { 0xffffffff, 0x0, 0x0, 0x0 }, + { 0x00003c78, 0x0, 0x0, 0x0 }, + { 0xf0000000, 0x0, 0x0, 0x0 }, + { 0x0000000f, 0x0, 0x0, 0x0 }, + { 0xbe800000, 0x0, 0x0, 0x0 }, + { 0x00000037, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, +}; + +static const void *r8a779a0_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + +static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = { + .core_clk = r8a779a0_core_clks, + .core_clk_size = ARRAY_SIZE(r8a779a0_core_clks), + .mod_clk = r8a779a0_mod_clks, + .mod_clk_size = ARRAY_SIZE(r8a779a0_mod_clks), + .mstp_table = r8a779a0_mstp_table, + .mstp_table_size = ARRAY_SIZE(r8a779a0_mstp_table), + .reset_node = "renesas,r8a779a0-rst", + .reset_modemr_offset = 0x00, + .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a779a0_get_pll_config, + .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, +}; + +static const struct udevice_id r8a779a0_clk_ids[] = { + { + .compatible = "renesas,r8a779a0-cpg-mssr", + .data = (ulong)&r8a779a0_cpg_mssr_info + }, + { } +}; + +U_BOOT_DRIVER(clk_r8a779a0) = { + .name = "clk_r8a779a0", + .id = UCLASS_CLK, + .of_match = r8a779a0_clk_ids, + .priv_auto = sizeof(struct gen3_clk_priv), + .ops = &gen3_clk_ops, + .probe = gen3_clk_probe, + .remove = gen3_clk_remove, +}; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index aa940a1ca2a..7bf57013619 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -27,6 +27,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, + CLK_TYPE_R8A779A0_MAIN, CLK_TYPE_R8A779A0_PLL1, CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index b1cf7f599c4..e0895d2c2f8 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -127,6 +127,10 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); + + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) + continue; + clrsetbits_le32(base + RMSTPCR(i), info->mstp_table[i].rdis, info->mstp_table[i].ren); diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 92421b15ee4..519f88548f8 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -17,6 +17,7 @@ enum clk_reg_layout { CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, + CLK_REG_LAYOUT_RCAR_V3U, }; struct cpg_mssr_info { @@ -146,6 +147,11 @@ static const u16 mstpsr[] = { 0x9A0, 0x9A4, 0x9A8, 0x9AC, }; +static const u16 mstpsr_for_v3u[] = { + 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, + 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, +}; + /* * System Module Stop Control Register offsets */ @@ -155,6 +161,11 @@ static const u16 smstpcr[] = { 0x990, 0x994, 0x998, 0x99C, }; +static const u16 mstpcr_for_v3u[] = { + 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, +}; + /* * Software Reset Register offsets */ @@ -164,6 +175,11 @@ static const u16 srcr[] = { 0x920, 0x924, 0x928, 0x92C, }; +static const u16 srcr_for_v3u[] = { + 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, + 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, +}; + /* Realtime Module Stop Control Register offsets */ #define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10) @@ -177,4 +193,9 @@ static const u16 srstclr[] = { 0x960, 0x964, 0x968, 0x96C, }; +static const u16 srstclr_for_v3u[] = { + 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, + 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, +}; + #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */ From e9c9e9cbef368d03ceda6d2c453f79e34b8cd203 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 27 Apr 2021 21:29:50 +0200 Subject: [PATCH 193/250] gpio: renesas: Handle R8A779A0 V3U INEN register The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN register. Add new R8A779A0 compatible string with a new quirk and also a handler for this quirk which toggles the INEN register in the right place. INEN register handling is based on "gpio: renesas: Add R8A779A0 V3U support" by Hai Pham Signed-off-by: Marek Vasut --- drivers/gpio/gpio-rcar.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 5f1ec39a9bb..76f47027a3e 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -28,13 +28,17 @@ #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ +#define GPIO_INEN 0x50 /* General Input Enable Register */ #define RCAR_MAX_GPIO_PER_BANK 32 +#define RCAR_GPIO_HAS_INEN BIT(0) + DECLARE_GLOBAL_DATA_PTR; struct rcar_gpio_priv { void __iomem *regs; + u32 quirks; int pfc_offset; }; @@ -81,6 +85,14 @@ static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset, /* Configure postive logic in POSNEG */ clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); + /* Select "Input Enable/Disable" in INEN */ + if (priv->quirks & RCAR_GPIO_HAS_INEN) { + if (output) + clrbits_le32(regs + GPIO_INEN, BIT(offset)); + else + setbits_le32(regs + GPIO_INEN, BIT(offset)); + } + /* Select "General Input/Output Mode" in IOINTSEL */ clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); @@ -149,6 +161,7 @@ static int rcar_gpio_probe(struct udevice *dev) int ret; priv->regs = dev_read_addr_ptr(dev); + priv->quirks = dev_get_driver_data(dev); uc_priv->bank_name = dev->name; ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", @@ -179,6 +192,7 @@ static const struct udevice_id rcar_gpio_ids[] = { { .compatible = "renesas,gpio-r8a77970" }, { .compatible = "renesas,gpio-r8a77990" }, { .compatible = "renesas,gpio-r8a77995" }, + { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN }, { .compatible = "renesas,rcar-gen2-gpio" }, { .compatible = "renesas,rcar-gen3-gpio" }, { /* sentinel */ } From df8adad57d7dd98163df71598e0963362bed6198 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 27 Apr 2021 01:55:54 +0200 Subject: [PATCH 194/250] pinctrl: renesas: Import R8A779A0 V3U PFC tables Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Add parts of PFC table integration from pinctrl: renesas: Add R8A779A0 V3U PFC tables by Hai Pham " . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/Kconfig | 6 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc-r8a779a0.c | 4503 ++++++++++++++++++++++++ drivers/pinctrl/renesas/pfc.c | 12 + drivers/pinctrl/renesas/sh_pfc.h | 1 + 5 files changed, 4523 insertions(+) create mode 100644 drivers/pinctrl/renesas/pfc-r8a779a0.c diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 35f10e2c2bf..1fedf632528 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -107,6 +107,12 @@ config PINCTRL_PFC_R8A77995 help Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs. +config PINCTRL_PFC_R8A779A0 + bool "Renesas RCar Gen3 R8A779A0 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs. + config PINCTRL_PFC_R7S72100 bool "Renesas RZ/A1 R7S72100 pin control driver" depends on CPU_RZA1 diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 0e2ac3c5136..1c65505eff0 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o +obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c new file mode 100644 index 00000000000..d99b6e2e07c --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -0,0 +1,4503 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R8A779A0 processor support - PFC hardware block. + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c + */ + +#include +#include +#include +#include +#include +#include + +#include "sh_pfc.h" + +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_27 FM(MMC_D7) +#define GPSR0_26 FM(MMC_D6) +#define GPSR0_25 FM(MMC_D5) +#define GPSR0_24 FM(MMC_D4) +#define GPSR0_23 FM(MMC_SD_CLK) +#define GPSR0_22 FM(MMC_SD_D3) +#define GPSR0_21 FM(MMC_SD_D2) +#define GPSR0_20 FM(MMC_SD_D1) +#define GPSR0_19 FM(MMC_SD_D0) +#define GPSR0_18 FM(MMC_SD_CMD) +#define GPSR0_17 FM(MMC_DS) +#define GPSR0_16 FM(SD_CD) +#define GPSR0_15 FM(SD_WP) +#define GPSR0_14 FM(RPC_INT_N) +#define GPSR0_13 FM(RPC_WP_N) +#define GPSR0_12 FM(RPC_RESET_N) +#define GPSR0_11 FM(QSPI1_SSL) +#define GPSR0_10 FM(QSPI1_IO3) +#define GPSR0_9 FM(QSPI1_IO2) +#define GPSR0_8 FM(QSPI1_MISO_IO1) +#define GPSR0_7 FM(QSPI1_MOSI_IO0) +#define GPSR0_6 FM(QSPI1_SPCLK) +#define GPSR0_5 FM(QSPI0_SSL) +#define GPSR0_4 FM(QSPI0_IO3) +#define GPSR0_3 FM(QSPI0_IO2) +#define GPSR0_2 FM(QSPI0_MISO_IO1) +#define GPSR0_1 FM(QSPI0_MOSI_IO0) +#define GPSR0_0 FM(QSPI0_SPCLK) + +/* GPSR1 */ +#define GPSR1_30 F_(GP1_30, IP3SR1_27_24) +#define GPSR1_29 F_(GP1_29, IP3SR1_23_20) +#define GPSR1_28 F_(GP1_28, IP3SR1_19_16) +#define GPSR1_27 F_(IRQ3, IP3SR1_15_12) +#define GPSR1_26 F_(IRQ2, IP3SR1_11_8) +#define GPSR1_25 F_(IRQ1, IP3SR1_7_4) +#define GPSR1_24 F_(IRQ0, IP3SR1_3_0) +#define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28) +#define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24) +#define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20) +#define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16) +#define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12) +#define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8) +#define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4) +#define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0) +#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28) +#define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24) +#define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20) +#define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16) +#define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12) +#define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8) +#define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4) +#define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0) +#define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28) +#define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24) +#define GPSR1_5 F_(HTX0, IP0SR1_23_20) +#define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16) +#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12) +#define GPSR1_2 F_(HSCK0, IP0SR1_11_8) +#define GPSR1_1 F_(HRX0, IP0SR1_7_4) +#define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0) + +/* GPSR2 */ +#define GPSR2_24 FM(TCLK2_A) +#define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28) +#define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24) +#define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20) +#define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16) +#define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12) +#define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8) +#define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4) +#define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0) +#define GPSR2_15 F_(GP2_15, IP1SR2_31_28) +#define GPSR2_14 F_(GP2_14, IP1SR2_27_24) +#define GPSR2_13 F_(GP2_13, IP1SR2_23_20) +#define GPSR2_12 F_(GP2_12, IP1SR2_19_16) +#define GPSR2_11 F_(GP2_11, IP1SR2_15_12) +#define GPSR2_10 F_(GP2_10, IP1SR2_11_8) +#define GPSR2_9 F_(GP2_09, IP1SR2_7_4) +#define GPSR2_8 F_(GP2_08, IP1SR2_3_0) +#define GPSR2_7 F_(GP2_07, IP0SR2_31_28) +#define GPSR2_6 F_(GP2_06, IP0SR2_27_24) +#define GPSR2_5 F_(GP2_05, IP0SR2_23_20) +#define GPSR2_4 F_(GP2_04, IP0SR2_19_16) +#define GPSR2_3 F_(GP2_03, IP0SR2_15_12) +#define GPSR2_2 F_(GP2_02, IP0SR2_11_8) +#define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4) +#define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0) + +/* GPSR3 */ +#define GPSR3_16 FM(CANFD7_RX) +#define GPSR3_15 FM(CANFD7_TX) +#define GPSR3_14 FM(CANFD6_RX) +#define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20) +#define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16) +#define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12) +#define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8) +#define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4) +#define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0) +#define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28) +#define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24) +#define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20) +#define GPSR3_4 FM(CANFD1_RX) +#define GPSR3_3 FM(CANFD1_TX) +#define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8) +#define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4) +#define GPSR3_0 FM(CAN_CLK) + +/* GPSR4 */ +#define GPSR4_26 FM(AVS1) +#define GPSR4_25 FM(AVS0) +#define GPSR4_24 FM(PCIE3_CLKREQ_N) +#define GPSR4_23 FM(PCIE2_CLKREQ_N) +#define GPSR4_22 FM(PCIE1_CLKREQ_N) +#define GPSR4_21 FM(PCIE0_CLKREQ_N) +#define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16) +#define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12) +#define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8) +#define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4) +#define GPSR4_16 FM(AVB0_PHY_INT) +#define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28) +#define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24) +#define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20) +#define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16) +#define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12) +#define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8) +#define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4) +#define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0) +#define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28) +#define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24) +#define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20) +#define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16) +#define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12) +#define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8) +#define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4) +#define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0) + +/* GPSR5 */ +#define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16) +#define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12) +#define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8) +#define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4) +#define GPSR5_16 FM(AVB1_PHY_INT) +#define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28) +#define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24) +#define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20) +#define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16) +#define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12) +#define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8) +#define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4) +#define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0) +#define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28) +#define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24) +#define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20) +#define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16) +#define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12) +#define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8) +#define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4) +#define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0) + +/* GPSR6 */ +#define GPSR6_20 FM(AVB2_AVTP_PPS) +#define GPSR6_19 FM(AVB2_AVTP_CAPTURE) +#define GPSR6_18 FM(AVB2_AVTP_MATCH) +#define GPSR6_17 FM(AVB2_LINK) +#define GPSR6_16 FM(AVB2_PHY_INT) +#define GPSR6_15 FM(AVB2_MAGIC) +#define GPSR6_14 FM(AVB2_MDC) +#define GPSR6_13 FM(AVB2_MDIO) +#define GPSR6_12 FM(AVB2_TXCREFCLK) +#define GPSR6_11 FM(AVB2_TD3) +#define GPSR6_10 FM(AVB2_TD2) +#define GPSR6_9 FM(AVB2_TD1) +#define GPSR6_8 FM(AVB2_TD0) +#define GPSR6_7 FM(AVB2_TXC) +#define GPSR6_6 FM(AVB2_TX_CTL) +#define GPSR6_5 FM(AVB2_RD3) +#define GPSR6_4 FM(AVB2_RD2) +#define GPSR6_3 FM(AVB2_RD1) +#define GPSR6_2 FM(AVB2_RD0) +#define GPSR6_1 FM(AVB2_RXC) +#define GPSR6_0 FM(AVB2_RX_CTL) + +/* GPSR7 */ +#define GPSR7_20 FM(AVB3_AVTP_PPS) +#define GPSR7_19 FM(AVB3_AVTP_CAPTURE) +#define GPSR7_18 FM(AVB3_AVTP_MATCH) +#define GPSR7_17 FM(AVB3_LINK) +#define GPSR7_16 FM(AVB3_PHY_INT) +#define GPSR7_15 FM(AVB3_MAGIC) +#define GPSR7_14 FM(AVB3_MDC) +#define GPSR7_13 FM(AVB3_MDIO) +#define GPSR7_12 FM(AVB3_TXCREFCLK) +#define GPSR7_11 FM(AVB3_TD3) +#define GPSR7_10 FM(AVB3_TD2) +#define GPSR7_9 FM(AVB3_TD1) +#define GPSR7_8 FM(AVB3_TD0) +#define GPSR7_7 FM(AVB3_TXC) +#define GPSR7_6 FM(AVB3_TX_CTL) +#define GPSR7_5 FM(AVB3_RD3) +#define GPSR7_4 FM(AVB3_RD2) +#define GPSR7_3 FM(AVB3_RD1) +#define GPSR7_2 FM(AVB3_RD0) +#define GPSR7_1 FM(AVB3_RXC) +#define GPSR7_0 FM(AVB3_RX_CTL) + +/* GPSR8 */ +#define GPSR8_20 FM(AVB4_AVTP_PPS) +#define GPSR8_19 FM(AVB4_AVTP_CAPTURE) +#define GPSR8_18 FM(AVB4_AVTP_MATCH) +#define GPSR8_17 FM(AVB4_LINK) +#define GPSR8_16 FM(AVB4_PHY_INT) +#define GPSR8_15 FM(AVB4_MAGIC) +#define GPSR8_14 FM(AVB4_MDC) +#define GPSR8_13 FM(AVB4_MDIO) +#define GPSR8_12 FM(AVB4_TXCREFCLK) +#define GPSR8_11 FM(AVB4_TD3) +#define GPSR8_10 FM(AVB4_TD2) +#define GPSR8_9 FM(AVB4_TD1) +#define GPSR8_8 FM(AVB4_TD0) +#define GPSR8_7 FM(AVB4_TXC) +#define GPSR8_6 FM(AVB4_TX_CTL) +#define GPSR8_5 FM(AVB4_RD3) +#define GPSR8_4 FM(AVB4_RD2) +#define GPSR8_3 FM(AVB4_RD1) +#define GPSR8_2 FM(AVB4_RD0) +#define GPSR8_1 FM(AVB4_RXC) +#define GPSR8_0 FM(AVB4_RX_CTL) + +/* GPSR9 */ +#define GPSR9_20 FM(AVB5_AVTP_PPS) +#define GPSR9_19 FM(AVB5_AVTP_CAPTURE) +#define GPSR9_18 FM(AVB5_AVTP_MATCH) +#define GPSR9_17 FM(AVB5_LINK) +#define GPSR9_16 FM(AVB5_PHY_INT) +#define GPSR9_15 FM(AVB5_MAGIC) +#define GPSR9_14 FM(AVB5_MDC) +#define GPSR9_13 FM(AVB5_MDIO) +#define GPSR9_12 FM(AVB5_TXCREFCLK) +#define GPSR9_11 FM(AVB5_TD3) +#define GPSR9_10 FM(AVB5_TD2) +#define GPSR9_9 FM(AVB5_TD1) +#define GPSR9_8 FM(AVB5_TD0) +#define GPSR9_7 FM(AVB5_TXC) +#define GPSR9_6 FM(AVB5_TX_CTL) +#define GPSR9_5 FM(AVB5_RD3) +#define GPSR9_4 FM(AVB5_RD2) +#define GPSR9_3 FM(AVB5_RD1) +#define GPSR9_2 FM(AVB5_RD0) +#define GPSR9_1 FM(AVB5_RXC) +#define GPSR9_0 FM(AVB5_RX_CTL) + +/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ + \ + GPSR1_30 \ + GPSR1_29 \ + GPSR1_28 \ +GPSR0_27 GPSR1_27 \ +GPSR0_26 GPSR1_26 GPSR4_26 \ +GPSR0_25 GPSR1_25 GPSR4_25 \ +GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \ +GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \ +GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \ +GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ +GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \ +GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \ +GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \ +GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \ +GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0 + +#define PINMUX_IPSR \ +\ +FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ +FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ +FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ +FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ +FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ +FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ +FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \ +FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \ +\ +FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \ +FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ +FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \ +FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ +FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \ +FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \ +FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \ +FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \ +\ +FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \ +FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \ +FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \ +FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \ +FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \ +FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \ +FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \ +FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \ +\ +FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \ +FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ +FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ +FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ +FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ +FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ +FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \ +FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ +\ +FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ +FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ +FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ +FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ +FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ +FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \ +FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \ +FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28 + +/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) +#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL2_14_15 \ +MOD_SEL2_12_13 \ +MOD_SEL2_10_11 \ +MOD_SEL2_8_9 \ +MOD_SEL2_6_7 \ +MOD_SEL2_4_5 \ +MOD_SEL2_2_3 + +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ + FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_PHYS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(MMC_D7), + PINMUX_SINGLE(MMC_D6), + PINMUX_SINGLE(MMC_D5), + PINMUX_SINGLE(MMC_D4), + PINMUX_SINGLE(MMC_SD_CLK), + PINMUX_SINGLE(MMC_SD_D3), + PINMUX_SINGLE(MMC_SD_D2), + PINMUX_SINGLE(MMC_SD_D1), + PINMUX_SINGLE(MMC_SD_D0), + PINMUX_SINGLE(MMC_SD_CMD), + PINMUX_SINGLE(MMC_DS), + + PINMUX_SINGLE(SD_CD), + PINMUX_SINGLE(SD_WP), + + PINMUX_SINGLE(RPC_INT_N), + PINMUX_SINGLE(RPC_WP_N), + PINMUX_SINGLE(RPC_RESET_N), + + PINMUX_SINGLE(QSPI1_SSL), + PINMUX_SINGLE(QSPI1_IO3), + PINMUX_SINGLE(QSPI1_IO2), + PINMUX_SINGLE(QSPI1_MISO_IO1), + PINMUX_SINGLE(QSPI1_MOSI_IO0), + PINMUX_SINGLE(QSPI1_SPCLK), + PINMUX_SINGLE(QSPI0_SSL), + PINMUX_SINGLE(QSPI0_IO3), + PINMUX_SINGLE(QSPI0_IO2), + PINMUX_SINGLE(QSPI0_MISO_IO1), + PINMUX_SINGLE(QSPI0_MOSI_IO0), + PINMUX_SINGLE(QSPI0_SPCLK), + + PINMUX_SINGLE(TCLK2_A), + + PINMUX_SINGLE(CANFD7_RX), + PINMUX_SINGLE(CANFD7_TX), + PINMUX_SINGLE(CANFD6_RX), + PINMUX_SINGLE(CANFD1_RX), + PINMUX_SINGLE(CANFD1_TX), + PINMUX_SINGLE(CAN_CLK), + + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS0), + + PINMUX_SINGLE(PCIE3_CLKREQ_N), + PINMUX_SINGLE(PCIE2_CLKREQ_N), + PINMUX_SINGLE(PCIE1_CLKREQ_N), + PINMUX_SINGLE(PCIE0_CLKREQ_N), + + PINMUX_SINGLE(AVB0_PHY_INT), + PINMUX_SINGLE(AVB0_MAGIC), + PINMUX_SINGLE(AVB0_MDC), + PINMUX_SINGLE(AVB0_MDIO), + PINMUX_SINGLE(AVB0_TXCREFCLK), + + PINMUX_SINGLE(AVB1_PHY_INT), + PINMUX_SINGLE(AVB1_MAGIC), + PINMUX_SINGLE(AVB1_MDC), + PINMUX_SINGLE(AVB1_MDIO), + PINMUX_SINGLE(AVB1_TXCREFCLK), + + PINMUX_SINGLE(AVB2_AVTP_PPS), + PINMUX_SINGLE(AVB2_AVTP_CAPTURE), + PINMUX_SINGLE(AVB2_AVTP_MATCH), + PINMUX_SINGLE(AVB2_LINK), + PINMUX_SINGLE(AVB2_PHY_INT), + PINMUX_SINGLE(AVB2_MAGIC), + PINMUX_SINGLE(AVB2_MDC), + PINMUX_SINGLE(AVB2_MDIO), + PINMUX_SINGLE(AVB2_TXCREFCLK), + PINMUX_SINGLE(AVB2_TD3), + PINMUX_SINGLE(AVB2_TD2), + PINMUX_SINGLE(AVB2_TD1), + PINMUX_SINGLE(AVB2_TD0), + PINMUX_SINGLE(AVB2_TXC), + PINMUX_SINGLE(AVB2_TX_CTL), + PINMUX_SINGLE(AVB2_RD3), + PINMUX_SINGLE(AVB2_RD2), + PINMUX_SINGLE(AVB2_RD1), + PINMUX_SINGLE(AVB2_RD0), + PINMUX_SINGLE(AVB2_RXC), + PINMUX_SINGLE(AVB2_RX_CTL), + + PINMUX_SINGLE(AVB3_AVTP_PPS), + PINMUX_SINGLE(AVB3_AVTP_CAPTURE), + PINMUX_SINGLE(AVB3_AVTP_MATCH), + PINMUX_SINGLE(AVB3_LINK), + PINMUX_SINGLE(AVB3_PHY_INT), + PINMUX_SINGLE(AVB3_MAGIC), + PINMUX_SINGLE(AVB3_MDC), + PINMUX_SINGLE(AVB3_MDIO), + PINMUX_SINGLE(AVB3_TXCREFCLK), + PINMUX_SINGLE(AVB3_TD3), + PINMUX_SINGLE(AVB3_TD2), + PINMUX_SINGLE(AVB3_TD1), + PINMUX_SINGLE(AVB3_TD0), + PINMUX_SINGLE(AVB3_TXC), + PINMUX_SINGLE(AVB3_TX_CTL), + PINMUX_SINGLE(AVB3_RD3), + PINMUX_SINGLE(AVB3_RD2), + PINMUX_SINGLE(AVB3_RD1), + PINMUX_SINGLE(AVB3_RD0), + PINMUX_SINGLE(AVB3_RXC), + PINMUX_SINGLE(AVB3_RX_CTL), + + PINMUX_SINGLE(AVB4_AVTP_PPS), + PINMUX_SINGLE(AVB4_AVTP_CAPTURE), + PINMUX_SINGLE(AVB4_AVTP_MATCH), + PINMUX_SINGLE(AVB4_LINK), + PINMUX_SINGLE(AVB4_PHY_INT), + PINMUX_SINGLE(AVB4_MAGIC), + PINMUX_SINGLE(AVB4_MDC), + PINMUX_SINGLE(AVB4_MDIO), + PINMUX_SINGLE(AVB4_TXCREFCLK), + PINMUX_SINGLE(AVB4_TD3), + PINMUX_SINGLE(AVB4_TD2), + PINMUX_SINGLE(AVB4_TD1), + PINMUX_SINGLE(AVB4_TD0), + PINMUX_SINGLE(AVB4_TXC), + PINMUX_SINGLE(AVB4_TX_CTL), + PINMUX_SINGLE(AVB4_RD3), + PINMUX_SINGLE(AVB4_RD2), + PINMUX_SINGLE(AVB4_RD1), + PINMUX_SINGLE(AVB4_RD0), + PINMUX_SINGLE(AVB4_RXC), + PINMUX_SINGLE(AVB4_RX_CTL), + + PINMUX_SINGLE(AVB5_AVTP_PPS), + PINMUX_SINGLE(AVB5_AVTP_CAPTURE), + PINMUX_SINGLE(AVB5_AVTP_MATCH), + PINMUX_SINGLE(AVB5_LINK), + PINMUX_SINGLE(AVB5_PHY_INT), + PINMUX_SINGLE(AVB5_MAGIC), + PINMUX_SINGLE(AVB5_MDC), + PINMUX_SINGLE(AVB5_MDIO), + PINMUX_SINGLE(AVB5_TXCREFCLK), + PINMUX_SINGLE(AVB5_TD3), + PINMUX_SINGLE(AVB5_TD2), + PINMUX_SINGLE(AVB5_TD1), + PINMUX_SINGLE(AVB5_TD0), + PINMUX_SINGLE(AVB5_TXC), + PINMUX_SINGLE(AVB5_TX_CTL), + PINMUX_SINGLE(AVB5_RD3), + PINMUX_SINGLE(AVB5_RD2), + PINMUX_SINGLE(AVB5_RD1), + PINMUX_SINGLE(AVB5_RD0), + PINMUX_SINGLE(AVB5_RXC), + PINMUX_SINGLE(AVB5_RX_CTL), + + /* IP0SR1 */ + PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK), + PINMUX_IPSR_GPSR(IP0SR1_3_0, A0), + + PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0), + PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0), + PINMUX_IPSR_GPSR(IP0SR1_7_4, A1), + + PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0), + PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0), + PINMUX_IPSR_GPSR(IP0SR1_11_8, A2), + + PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_15_12, A3), + + PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_19_16, A4), + + PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0), + PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0), + PINMUX_IPSR_GPSR(IP0SR1_23_20, A5), + + PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2), + PINMUX_IPSR_GPSR(IP0SR1_27_24, A6), + + PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3), + PINMUX_IPSR_GPSR(IP0SR1_31_28, A7), + + /* IP1SR1 */ + PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4), + PINMUX_IPSR_GPSR(IP1SR1_3_0, A8), + + PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5), + PINMUX_IPSR_GPSR(IP1SR1_7_4, A9), + + PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6), + PINMUX_IPSR_GPSR(IP1SR1_11_8, A10), + + PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7), + PINMUX_IPSR_GPSR(IP1SR1_15_12, A11), + + PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2), + PINMUX_IPSR_GPSR(IP1SR1_19_16, A12), + + PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3), + PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3), + PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3), + PINMUX_IPSR_GPSR(IP1SR1_23_20, A13), + + PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3), + PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N), + PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4), + PINMUX_IPSR_GPSR(IP1SR1_27_24, A14), + + PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N), + PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N), + PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5), + PINMUX_IPSR_GPSR(IP1SR1_31_28, A15), + + /* IP2SR1 */ + PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N), + PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3), + PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6), + PINMUX_IPSR_GPSR(IP2SR1_3_0, A16), + + PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3), + PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3), + PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7), + PINMUX_IPSR_GPSR(IP2SR1_7_4, A17), + + PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD), + PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1), + PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1), + PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2), + PINMUX_IPSR_GPSR(IP2SR1_11_8, A18), + + PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD), + PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3), + PINMUX_IPSR_GPSR(IP2SR1_15_12, A19), + + PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK), + PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4), + PINMUX_IPSR_GPSR(IP2SR1_19_16, A20), + + PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC), + PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1), + PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A), + PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5), + PINMUX_IPSR_GPSR(IP2SR1_23_20, A21), + + PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1), + PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1), + PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A), + PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6), + PINMUX_IPSR_GPSR(IP2SR1_27_24, A22), + + PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2), + PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B), + PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7), + PINMUX_IPSR_GPSR(IP2SR1_31_28, A23), + + /* IP3SR1 */ + PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0), + PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT), + PINMUX_IPSR_GPSR(IP3SR1_3_0, A24), + + PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1), + PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC), + PINMUX_IPSR_GPSR(IP3SR1_7_4, A25), + + PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2), + PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC), + PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26), + + PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3), + PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE), + PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N), + + PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28), + PINMUX_IPSR_GPSR(IP3SR1_19_16, D0), + + PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29), + PINMUX_IPSR_GPSR(IP3SR1_23_20, D1), + + PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30), + PINMUX_IPSR_GPSR(IP3SR1_27_24, D2), + + /* IP0SR2 */ + PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN), + PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN), + PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN), + + PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT), + PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT), + + /* GP2_02 = SCL0 */ + PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3), + + /* GP2_03 = SDA0 */ + PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3), + + /* GP2_04 = SCL1 */ + PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3), + + /* GP2_05 = SDA1 */ + PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3), + + /* GP2_06 = SCL2 */ + PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3), + + /* GP2_07 = SDA2 */ + PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3), + + /* GP2_08 = SCL3 */ + PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3), + + /* GP2_09 = SDA3 */ + PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3), + + /* GP2_10 = SCL4 */ + PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0), + PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3), + + /* GP2_11 = SDA4 */ + PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0), + PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3), + + /* GP2_12 = SCL5 */ + PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0), + PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3), + + /* GP2_13 = SDA5 */ + PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0), + PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3), + + /* GP2_14 = SCL6 */ + PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0), + PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3), + + /* GP2_15 = SDA6 */ + PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0), + PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3), + + /* IP2SR2 */ + PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A), + PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1), + + PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A), + PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2), + PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N), + + PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB), + PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD), + PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N), + + PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR), + PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD), + PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N), + + PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR), + PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK), + PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N), + + PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0), + PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC), + PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N), + + PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1), + PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT), + + PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A), + PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0), + + /* IP0SR3 */ + PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX), + PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B), + PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B), + + PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX), + PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B), + PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B), + + PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX), + PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2), + PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0), + + PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX), + PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3), + PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1), + + PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX), + PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2), + + /* IP1SR3 */ + PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX), + PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3), + + PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX), + PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4), + PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1), + + PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX), + PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2), + + PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX), + PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N), + + PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX), + PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N), + + PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX), + PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR), + + /* IP0SR4 */ + PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL), + PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV), + + PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC), + PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC), + + PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0), + PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0), + + PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1), + PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1), + + PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2), + PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2), + + PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3), + PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3), + + PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL), + PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN), + + PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC), + PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC), + + /* IP1SR4 */ + PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0), + PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0), + + PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1), + PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1), + + PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2), + PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2), + + PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3), + PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3), + + PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK), + + PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO), + + PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC), + + PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC), + + /* IP2SR4 */ + PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK), + PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER), + + PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER), + PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT), + + PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS), + + PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS), + PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL), + + /* IP0SR5 */ + PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL), + PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV), + + PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC), + PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC), + + PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0), + PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0), + + PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1), + PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1), + + PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2), + PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2), + + PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3), + PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3), + + PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL), + PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN), + + PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC), + PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC), + + /* IP1SR5 */ + PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0), + PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0), + + PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1), + PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1), + + PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2), + PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2), + + PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3), + PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3), + + PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK), + + PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO), + + PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC), + + PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC), + + /* IP2SR5 */ + PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK), + PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER), + + PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER), + + PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS), + + PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS), + PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL), +}; + +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - AVB0 ------------------------------------------------ */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, +}; +static const unsigned int avb0_magic_pins[] = { + /* AVB0_MAGIC */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int avb0_magic_mux[] = { + AVB0_MAGIC_MARK, +}; +static const unsigned int avb0_phy_int_pins[] = { + /* AVB0_PHY_INT */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int avb0_phy_int_mux[] = { + AVB0_PHY_INT_MARK, +}; +static const unsigned int avb0_mdio_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), +}; +static const unsigned int avb0_mdio_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_rgmii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, + */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int avb0_rgmii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, + AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, + AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, +}; +static const unsigned int avb0_txcrefclk_pins[] = { + /* AVB0_TXCREFCLK */ + RCAR_GP_PIN(4, 12), +}; +static const unsigned int avb0_txcrefclk_mux[] = { + AVB0_TXCREFCLK_MARK, +}; +static const unsigned int avb0_avtp_pps_pins[] = { + /* AVB0_AVTP_PPS */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int avb0_avtp_pps_mux[] = { + AVB0_AVTP_PPS_MARK, +}; +static const unsigned int avb0_avtp_capture_pins[] = { + /* AVB0_AVTP_CAPTURE */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int avb0_avtp_capture_mux[] = { + AVB0_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb0_avtp_match_pins[] = { + /* AVB0_AVTP_MATCH */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int avb0_avtp_match_mux[] = { + AVB0_AVTP_MATCH_MARK, +}; + +/* - AVB1 ------------------------------------------------ */ +static const unsigned int avb1_link_pins[] = { + /* AVB1_LINK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int avb1_link_mux[] = { + AVB1_LINK_MARK, +}; +static const unsigned int avb1_magic_pins[] = { + /* AVB1_MAGIC */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int avb1_magic_mux[] = { + AVB1_MAGIC_MARK, +}; +static const unsigned int avb1_phy_int_pins[] = { + /* AVB1_PHY_INT */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int avb1_phy_int_mux[] = { + AVB1_PHY_INT_MARK, +}; +static const unsigned int avb1_mdio_pins[] = { + /* AVB1_MDC, AVB1_MDIO */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13), +}; +static const unsigned int avb1_mdio_mux[] = { + AVB1_MDC_MARK, AVB1_MDIO_MARK, +}; +static const unsigned int avb1_rgmii_pins[] = { + /* + * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, + * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, + */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), + RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3), + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), +}; +static const unsigned int avb1_rgmii_mux[] = { + AVB1_TX_CTL_MARK, AVB1_TXC_MARK, + AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK, + AVB1_RX_CTL_MARK, AVB1_RXC_MARK, + AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK, +}; +static const unsigned int avb1_txcrefclk_pins[] = { + /* AVB1_TXCREFCLK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int avb1_txcrefclk_mux[] = { + AVB1_TXCREFCLK_MARK, +}; +static const unsigned int avb1_avtp_pps_pins[] = { + /* AVB1_AVTP_PPS */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int avb1_avtp_pps_mux[] = { + AVB1_AVTP_PPS_MARK, +}; +static const unsigned int avb1_avtp_capture_pins[] = { + /* AVB1_AVTP_CAPTURE */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int avb1_avtp_capture_mux[] = { + AVB1_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb1_avtp_match_pins[] = { + /* AVB1_AVTP_MATCH */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int avb1_avtp_match_mux[] = { + AVB1_AVTP_MATCH_MARK, +}; + +/* - AVB2 ------------------------------------------------ */ +static const unsigned int avb2_link_pins[] = { + /* AVB2_LINK */ + RCAR_GP_PIN(6, 17), +}; +static const unsigned int avb2_link_mux[] = { + AVB2_LINK_MARK, +}; +static const unsigned int avb2_magic_pins[] = { + /* AVB2_MAGIC */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int avb2_magic_mux[] = { + AVB2_MAGIC_MARK, +}; +static const unsigned int avb2_phy_int_pins[] = { + /* AVB2_PHY_INT */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int avb2_phy_int_mux[] = { + AVB2_PHY_INT_MARK, +}; +static const unsigned int avb2_mdio_pins[] = { + /* AVB2_MDC, AVB2_MDIO */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13), +}; +static const unsigned int avb2_mdio_mux[] = { + AVB2_MDC_MARK, AVB2_MDIO_MARK, +}; +static const unsigned int avb2_rgmii_pins[] = { + /* + * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, + * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, + */ + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), +}; +static const unsigned int avb2_rgmii_mux[] = { + AVB2_TX_CTL_MARK, AVB2_TXC_MARK, + AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK, + AVB2_RX_CTL_MARK, AVB2_RXC_MARK, + AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK, +}; +static const unsigned int avb2_txcrefclk_pins[] = { + /* AVB2_TXCREFCLK */ + RCAR_GP_PIN(6, 12), +}; +static const unsigned int avb2_txcrefclk_mux[] = { + AVB2_TXCREFCLK_MARK, +}; +static const unsigned int avb2_avtp_pps_pins[] = { + /* AVB2_AVTP_PPS */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int avb2_avtp_pps_mux[] = { + AVB2_AVTP_PPS_MARK, +}; +static const unsigned int avb2_avtp_capture_pins[] = { + /* AVB2_AVTP_CAPTURE */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int avb2_avtp_capture_mux[] = { + AVB2_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb2_avtp_match_pins[] = { + /* AVB2_AVTP_MATCH */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int avb2_avtp_match_mux[] = { + AVB2_AVTP_MATCH_MARK, +}; + +/* - AVB3 ------------------------------------------------ */ +static const unsigned int avb3_link_pins[] = { + /* AVB3_LINK */ + RCAR_GP_PIN(7, 17), +}; +static const unsigned int avb3_link_mux[] = { + AVB3_LINK_MARK, +}; +static const unsigned int avb3_magic_pins[] = { + /* AVB3_MAGIC */ + RCAR_GP_PIN(7, 15), +}; +static const unsigned int avb3_magic_mux[] = { + AVB3_MAGIC_MARK, +}; +static const unsigned int avb3_phy_int_pins[] = { + /* AVB3_PHY_INT */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int avb3_phy_int_mux[] = { + AVB3_PHY_INT_MARK, +}; +static const unsigned int avb3_mdio_pins[] = { + /* AVB3_MDC, AVB3_MDIO */ + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13), +}; +static const unsigned int avb3_mdio_mux[] = { + AVB3_MDC_MARK, AVB3_MDIO_MARK, +}; +static const unsigned int avb3_rgmii_pins[] = { + /* + * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3, + * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3, + */ + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), + RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1), + RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3), + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), +}; +static const unsigned int avb3_rgmii_mux[] = { + AVB3_TX_CTL_MARK, AVB3_TXC_MARK, + AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK, + AVB3_RX_CTL_MARK, AVB3_RXC_MARK, + AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK, +}; +static const unsigned int avb3_txcrefclk_pins[] = { + /* AVB3_TXCREFCLK */ + RCAR_GP_PIN(7, 12), +}; +static const unsigned int avb3_txcrefclk_mux[] = { + AVB3_TXCREFCLK_MARK, +}; +static const unsigned int avb3_avtp_pps_pins[] = { + /* AVB3_AVTP_PPS */ + RCAR_GP_PIN(7, 20), +}; +static const unsigned int avb3_avtp_pps_mux[] = { + AVB3_AVTP_PPS_MARK, +}; +static const unsigned int avb3_avtp_capture_pins[] = { + /* AVB3_AVTP_CAPTURE */ + RCAR_GP_PIN(7, 19), +}; +static const unsigned int avb3_avtp_capture_mux[] = { + AVB3_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb3_avtp_match_pins[] = { + /* AVB3_AVTP_MATCH */ + RCAR_GP_PIN(7, 18), +}; +static const unsigned int avb3_avtp_match_mux[] = { + AVB3_AVTP_MATCH_MARK, +}; + +/* - AVB4 ------------------------------------------------ */ +static const unsigned int avb4_link_pins[] = { + /* AVB4_LINK */ + RCAR_GP_PIN(8, 17), +}; +static const unsigned int avb4_link_mux[] = { + AVB4_LINK_MARK, +}; +static const unsigned int avb4_magic_pins[] = { + /* AVB4_MAGIC */ + RCAR_GP_PIN(8, 15), +}; +static const unsigned int avb4_magic_mux[] = { + AVB4_MAGIC_MARK, +}; +static const unsigned int avb4_phy_int_pins[] = { + /* AVB4_PHY_INT */ + RCAR_GP_PIN(8, 16), +}; +static const unsigned int avb4_phy_int_mux[] = { + AVB4_PHY_INT_MARK, +}; +static const unsigned int avb4_mdio_pins[] = { + /* AVB4_MDC, AVB4_MDIO */ + RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13), +}; +static const unsigned int avb4_mdio_mux[] = { + AVB4_MDC_MARK, AVB4_MDIO_MARK, +}; +static const unsigned int avb4_rgmii_pins[] = { + /* + * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3, + * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3, + */ + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), + RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), + RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1), + RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3), + RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), +}; +static const unsigned int avb4_rgmii_mux[] = { + AVB4_TX_CTL_MARK, AVB4_TXC_MARK, + AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK, + AVB4_RX_CTL_MARK, AVB4_RXC_MARK, + AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK, +}; +static const unsigned int avb4_txcrefclk_pins[] = { + /* AVB4_TXCREFCLK */ + RCAR_GP_PIN(8, 12), +}; +static const unsigned int avb4_txcrefclk_mux[] = { + AVB4_TXCREFCLK_MARK, +}; +static const unsigned int avb4_avtp_pps_pins[] = { + /* AVB4_AVTP_PPS */ + RCAR_GP_PIN(8, 20), +}; +static const unsigned int avb4_avtp_pps_mux[] = { + AVB4_AVTP_PPS_MARK, +}; +static const unsigned int avb4_avtp_capture_pins[] = { + /* AVB4_AVTP_CAPTURE */ + RCAR_GP_PIN(8, 19), +}; +static const unsigned int avb4_avtp_capture_mux[] = { + AVB4_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb4_avtp_match_pins[] = { + /* AVB4_AVTP_MATCH */ + RCAR_GP_PIN(8, 18), +}; +static const unsigned int avb4_avtp_match_mux[] = { + AVB4_AVTP_MATCH_MARK, +}; + +/* - AVB5 ------------------------------------------------ */ +static const unsigned int avb5_link_pins[] = { + /* AVB5_LINK */ + RCAR_GP_PIN(9, 17), +}; +static const unsigned int avb5_link_mux[] = { + AVB5_LINK_MARK, +}; +static const unsigned int avb5_magic_pins[] = { + /* AVB5_MAGIC */ + RCAR_GP_PIN(9, 15), +}; +static const unsigned int avb5_magic_mux[] = { + AVB5_MAGIC_MARK, +}; +static const unsigned int avb5_phy_int_pins[] = { + /* AVB5_PHY_INT */ + RCAR_GP_PIN(9, 16), +}; +static const unsigned int avb5_phy_int_mux[] = { + AVB5_PHY_INT_MARK, +}; +static const unsigned int avb5_mdio_pins[] = { + /* AVB5_MDC, AVB5_MDIO */ + RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13), +}; +static const unsigned int avb5_mdio_mux[] = { + AVB5_MDC_MARK, AVB5_MDIO_MARK, +}; +static const unsigned int avb5_rgmii_pins[] = { + /* + * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3, + * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3, + */ + RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), + RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), + RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), + RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1), + RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3), + RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), +}; +static const unsigned int avb5_rgmii_mux[] = { + AVB5_TX_CTL_MARK, AVB5_TXC_MARK, + AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK, + AVB5_RX_CTL_MARK, AVB5_RXC_MARK, + AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK, +}; +static const unsigned int avb5_txcrefclk_pins[] = { + /* AVB5_TXCREFCLK */ + RCAR_GP_PIN(9, 12), +}; +static const unsigned int avb5_txcrefclk_mux[] = { + AVB5_TXCREFCLK_MARK, +}; +static const unsigned int avb5_avtp_pps_pins[] = { + /* AVB5_AVTP_PPS */ + RCAR_GP_PIN(9, 20), +}; +static const unsigned int avb5_avtp_pps_mux[] = { + AVB5_AVTP_PPS_MARK, +}; +static const unsigned int avb5_avtp_capture_pins[] = { + /* AVB5_AVTP_CAPTURE */ + RCAR_GP_PIN(9, 19), +}; +static const unsigned int avb5_avtp_capture_mux[] = { + AVB5_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb5_avtp_match_pins[] = { + /* AVB5_AVTP_MATCH */ + RCAR_GP_PIN(9, 18), +}; +static const unsigned int avb5_avtp_match_mux[] = { + AVB5_AVTP_MATCH_MARK, +}; + +/* - CANFD0 ----------------------------------------------------------------- */ +static const unsigned int canfd0_data_pins[] = { + /* CANFD0_TX, CANFD0_RX */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), +}; +static const unsigned int canfd0_data_mux[] = { + CANFD0_TX_MARK, CANFD0_RX_MARK, +}; + +/* - CANFD1 ----------------------------------------------------------------- */ +static const unsigned int canfd1_data_pins[] = { + /* CANFD1_TX, CANFD1_RX */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + +/* - CANFD2 ----------------------------------------------------------------- */ +static const unsigned int canfd2_data_pins[] = { + /* CANFD2_TX, CANFD2_RX */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), +}; +static const unsigned int canfd2_data_mux[] = { + CANFD2_TX_MARK, CANFD2_RX_MARK, +}; + +/* - CANFD3 ----------------------------------------------------------------- */ +static const unsigned int canfd3_data_pins[] = { + /* CANFD3_TX, CANFD3_RX */ + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), +}; +static const unsigned int canfd3_data_mux[] = { + CANFD3_TX_MARK, CANFD3_RX_MARK, +}; + +/* - CANFD4 ----------------------------------------------------------------- */ +static const unsigned int canfd4_data_pins[] = { + /* CANFD4_TX, CANFD4_RX */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int canfd4_data_mux[] = { + CANFD4_TX_MARK, CANFD4_RX_MARK, +}; + +/* - CANFD5 ----------------------------------------------------------------- */ +static const unsigned int canfd5_data_pins[] = { + /* CANFD5_TX, CANFD5_RX */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int canfd5_data_mux[] = { + CANFD5_TX_MARK, CANFD5_RX_MARK, +}; + +/* - CANFD6 ----------------------------------------------------------------- */ +static const unsigned int canfd6_data_pins[] = { + /* CANFD6_TX, CANFD6_RX */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int canfd6_data_mux[] = { + CANFD6_TX_MARK, CANFD6_RX_MARK, +}; + +/* - CANFD7 ----------------------------------------------------------------- */ +static const unsigned int canfd7_data_pins[] = { + /* CANFD7_TX, CANFD7_RX */ + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), +}; +static const unsigned int canfd7_data_mux[] = { + CANFD7_TX_MARK, CANFD7_RX_MARK, +}; + +/* - CANFD Clock ------------------------------------------------------------ */ +static const unsigned int can_clk_pins[] = { + /* CAN_CLK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb888_pins[] = { + /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +}; +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, + DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, + DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, + DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_clk_out_pins[] = { + /* DU_DOTCLKOUT */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int du_clk_out_mux[] = { + DU_DOTCLKOUT_MARK, +}; +static const unsigned int du_sync_pins[] = { + /* DU_HSYNC, DU_VSYNC */ + RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26), +}; +static const unsigned int du_sync_mux[] = { + DU_HSYNC_MARK, DU_VSYNC_MARK, +}; +static const unsigned int du_oddf_pins[] = { + /* DU_EXODDF/DU_ODDF/DISP/CDE */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int du_oddf_mux[] = { + DU_ODDF_DISP_CDE_MARK, +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* HRTS0#, HCTS0# */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; + +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* HRX1, HTX1 */ + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* HSCK1 */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* HRTS1#, HCTS1# */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; + +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* HRX2, HTX2 */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* HSCK2 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* HRTS2#, HCTS2# */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; + +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_pins[] = { + /* HRX3, HTX3 */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17), +}; +static const unsigned int hscif3_data_mux[] = { + HRX3_MARK, HTX3_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* HSCK3 */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* HRTS3#, HCTS3# */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SDA0, SCL0 */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), +}; +static const unsigned int i2c0_mux[] = { + SDA0_MARK, SCL0_MARK, +}; + +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SDA1, SCL1 */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +}; +static const unsigned int i2c1_mux[] = { + SDA1_MARK, SCL1_MARK, +}; + +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SDA2, SCL2 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), +}; +static const unsigned int i2c2_mux[] = { + SDA2_MARK, SCL2_MARK, +}; + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SDA3, SCL3 */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), +}; +static const unsigned int i2c3_mux[] = { + SDA3_MARK, SCL3_MARK, +}; + +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SDA4, SCL4 */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), +}; +static const unsigned int i2c4_mux[] = { + SDA4_MARK, SCL4_MARK, +}; + +/* - I2C5 ------------------------------------------------------------------- */ +static const unsigned int i2c5_pins[] = { + /* SDA5, SCL5 */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), +}; +static const unsigned int i2c5_mux[] = { + SDA5_MARK, SCL5_MARK, +}; + +/* - I2C6 ------------------------------------------------------------------- */ +static const unsigned int i2c6_pins[] = { + /* SDA6, SCL6 */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), +}; +static const unsigned int i2c6_mux[] = { + SDA6_MARK, SCL6_MARK, +}; + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data1_pins[] = { + /* MMC_SD_D0 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_SD_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* MMC_SD_D[0:3] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* MMC_SD_D[0:3], MMC_D[4:7] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* MMC_SD_CLK, MMC_SD_CMD */ + RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* SD_CD */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int mmc_cd_mux[] = { + SD_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* SD_WP */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int mmc_wp_mux[] = { + SD_WP_MARK, +}; +static const unsigned int mmc_ds_pins[] = { + /* MMC_DS */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int mmc_ds_mux[] = { + MMC_DS_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* MSIOF0_SCK */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* MSIOF0_SYNC */ + RCAR_GP_PIN(1, 9), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* MSIOF0_SS1 */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* MSIOF0_SS2 */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* MSIOF0_TXD */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* MSIOF0_RXD */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* MSIOF1_SCK */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* MSIOF1_SYNC */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* MSIOF1_SS1 */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* MSIOF1_SS2 */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* MSIOF1_TXD */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* MSIOF1_RXD */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* MSIOF2_SCK */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* MSIOF2_SYNC */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* MSIOF2_SS1 */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* MSIOF2_SS2 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* MSIOF2_TXD */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_rxd_pins[] = { + /* MSIOF2_RXD */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int msiof2_rxd_mux[] = { + MSIOF2_RXD_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* MSIOF3_SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* MSIOF3_SYNC */ + RCAR_GP_PIN(2, 21), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* MSIOF3_SS1 */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* MSIOF3_SS2 */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* MSIOF3_TXD */ + RCAR_GP_PIN(2, 19), +}; +static const unsigned int msiof3_txd_mux[] = { + MSIOF3_TXD_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* MSIOF3_RXD */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int msiof3_rxd_mux[] = { + MSIOF3_RXD_MARK, +}; + +/* - MSIOF4 ----------------------------------------------------------------- */ +static const unsigned int msiof4_clk_pins[] = { + /* MSIOF4_SCK */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int msiof4_clk_mux[] = { + MSIOF4_SCK_MARK, +}; +static const unsigned int msiof4_sync_pins[] = { + /* MSIOF4_SYNC */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int msiof4_sync_mux[] = { + MSIOF4_SYNC_MARK, +}; +static const unsigned int msiof4_ss1_pins[] = { + /* MSIOF4_SS1 */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int msiof4_ss1_mux[] = { + MSIOF4_SS1_MARK, +}; +static const unsigned int msiof4_ss2_pins[] = { + /* MSIOF4_SS2 */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int msiof4_ss2_mux[] = { + MSIOF4_SS2_MARK, +}; +static const unsigned int msiof4_txd_pins[] = { + /* MSIOF4_TXD */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof4_txd_mux[] = { + MSIOF4_TXD_MARK, +}; +static const unsigned int msiof4_rxd_pins[] = { + /* MSIOF4_RXD */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof4_rxd_mux[] = { + MSIOF4_RXD_MARK, +}; + +/* - MSIOF5 ----------------------------------------------------------------- */ +static const unsigned int msiof5_clk_pins[] = { + /* MSIOF5_SCK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int msiof5_clk_mux[] = { + MSIOF5_SCK_MARK, +}; +static const unsigned int msiof5_sync_pins[] = { + /* MSIOF5_SYNC */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int msiof5_sync_mux[] = { + MSIOF5_SYNC_MARK, +}; +static const unsigned int msiof5_ss1_pins[] = { + /* MSIOF5_SS1 */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof5_ss1_mux[] = { + MSIOF5_SS1_MARK, +}; +static const unsigned int msiof5_ss2_pins[] = { + /* MSIOF5_SS2 */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int msiof5_ss2_mux[] = { + MSIOF5_SS2_MARK, +}; +static const unsigned int msiof5_txd_pins[] = { + /* MSIOF5_TXD */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int msiof5_txd_mux[] = { + MSIOF5_TXD_MARK, +}; +static const unsigned int msiof5_rxd_pins[] = { + /* MSIOF5_RXD */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int msiof5_rxd_mux[] = { + MSIOF5_RXD_MARK, +}; + +/* - PWM0 ------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + /* PWM0 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; + +/* - PWM1 ------------------------------------------------------------------- */ +static const unsigned int pwm1_pins[] = { + /* PWM1 */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; + +/* - PWM2 ------------------------------------------------------------------- */ +static const unsigned int pwm2_pins[] = { + /* PWM2 */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; + +/* - PWM3 ------------------------------------------------------------------- */ +static const unsigned int pwm3_pins[] = { + /* PWM3 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; + +/* - PWM4 ------------------------------------------------------------------- */ +static const unsigned int pwm4_pins[] = { + /* PWM4 */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; + +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX0, TX0 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK0 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS0#, CTS0# */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; + +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK1 */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS1#, CTS1# */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_MARK, CTS1_N_MARK, +}; + +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX3, TX3 */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK3 */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS3#, CTS3# */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_MARK, CTS3_N_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX4, TX4 */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK4 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_ctrl_pins[] = { + /* RTS4#, CTS4# */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), +}; +static const unsigned int scif4_ctrl_mux[] = { + RTS4_N_MARK, CTS4_N_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +/* - TMU -------------------------------------------------------------------- */ +static const unsigned int tmu_tclk1_a_pins[] = { + /* TCLK1 */ + RCAR_GP_PIN(2, 23), +}; +static const unsigned int tmu_tclk1_a_mux[] = { + TCLK1_A_MARK, +}; +static const unsigned int tmu_tclk1_b_pins[] = { + /* TCLK1 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int tmu_tclk1_b_mux[] = { + TCLK1_B_MARK, +}; + +static const unsigned int tmu_tclk2_a_pins[] = { + /* TCLK2 */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int tmu_tclk2_a_mux[] = { + TCLK2_A_MARK, +}; +static const unsigned int tmu_tclk2_b_pins[] = { + /* TCLK2 */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int tmu_tclk2_b_mux[] = { + TCLK2_B_MARK, +}; + +static const unsigned int tmu_tclk3_pins[] = { + /* TCLK3 */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int tmu_tclk3_mux[] = { + TCLK3_MARK, +}; + +static const unsigned int tmu_tclk4_pins[] = { + /* TCLK4 */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int tmu_tclk4_mux[] = { + TCLK4_MARK, +}; + +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(2, 21), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb0_link), + SH_PFC_PIN_GROUP(avb0_magic), + SH_PFC_PIN_GROUP(avb0_phy_int), + SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_rgmii), + SH_PFC_PIN_GROUP(avb0_txcrefclk), + SH_PFC_PIN_GROUP(avb0_avtp_pps), + SH_PFC_PIN_GROUP(avb0_avtp_capture), + SH_PFC_PIN_GROUP(avb0_avtp_match), + + SH_PFC_PIN_GROUP(avb1_link), + SH_PFC_PIN_GROUP(avb1_magic), + SH_PFC_PIN_GROUP(avb1_phy_int), + SH_PFC_PIN_GROUP(avb1_mdio), + SH_PFC_PIN_GROUP(avb1_rgmii), + SH_PFC_PIN_GROUP(avb1_txcrefclk), + SH_PFC_PIN_GROUP(avb1_avtp_pps), + SH_PFC_PIN_GROUP(avb1_avtp_capture), + SH_PFC_PIN_GROUP(avb1_avtp_match), + + SH_PFC_PIN_GROUP(avb2_link), + SH_PFC_PIN_GROUP(avb2_magic), + SH_PFC_PIN_GROUP(avb2_phy_int), + SH_PFC_PIN_GROUP(avb2_mdio), + SH_PFC_PIN_GROUP(avb2_rgmii), + SH_PFC_PIN_GROUP(avb2_txcrefclk), + SH_PFC_PIN_GROUP(avb2_avtp_pps), + SH_PFC_PIN_GROUP(avb2_avtp_capture), + SH_PFC_PIN_GROUP(avb2_avtp_match), + + SH_PFC_PIN_GROUP(avb3_link), + SH_PFC_PIN_GROUP(avb3_magic), + SH_PFC_PIN_GROUP(avb3_phy_int), + SH_PFC_PIN_GROUP(avb3_mdio), + SH_PFC_PIN_GROUP(avb3_rgmii), + SH_PFC_PIN_GROUP(avb3_txcrefclk), + SH_PFC_PIN_GROUP(avb3_avtp_pps), + SH_PFC_PIN_GROUP(avb3_avtp_capture), + SH_PFC_PIN_GROUP(avb3_avtp_match), + + SH_PFC_PIN_GROUP(avb4_link), + SH_PFC_PIN_GROUP(avb4_magic), + SH_PFC_PIN_GROUP(avb4_phy_int), + SH_PFC_PIN_GROUP(avb4_mdio), + SH_PFC_PIN_GROUP(avb4_rgmii), + SH_PFC_PIN_GROUP(avb4_txcrefclk), + SH_PFC_PIN_GROUP(avb4_avtp_pps), + SH_PFC_PIN_GROUP(avb4_avtp_capture), + SH_PFC_PIN_GROUP(avb4_avtp_match), + + SH_PFC_PIN_GROUP(avb5_link), + SH_PFC_PIN_GROUP(avb5_magic), + SH_PFC_PIN_GROUP(avb5_phy_int), + SH_PFC_PIN_GROUP(avb5_mdio), + SH_PFC_PIN_GROUP(avb5_rgmii), + SH_PFC_PIN_GROUP(avb5_txcrefclk), + SH_PFC_PIN_GROUP(avb5_avtp_pps), + SH_PFC_PIN_GROUP(avb5_avtp_capture), + SH_PFC_PIN_GROUP(avb5_avtp_match), + + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(canfd2_data), + SH_PFC_PIN_GROUP(canfd3_data), + SH_PFC_PIN_GROUP(canfd4_data), + SH_PFC_PIN_GROUP(canfd5_data), + SH_PFC_PIN_GROUP(canfd6_data), + SH_PFC_PIN_GROUP(canfd7_data), + SH_PFC_PIN_GROUP(can_clk), + + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif3_data), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c6), + + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), + SH_PFC_PIN_GROUP(mmc_ds), + + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_rxd), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), + SH_PFC_PIN_GROUP(msiof4_clk), + SH_PFC_PIN_GROUP(msiof4_sync), + SH_PFC_PIN_GROUP(msiof4_ss1), + SH_PFC_PIN_GROUP(msiof4_ss2), + SH_PFC_PIN_GROUP(msiof4_txd), + SH_PFC_PIN_GROUP(msiof4_rxd), + SH_PFC_PIN_GROUP(msiof5_clk), + SH_PFC_PIN_GROUP(msiof5_sync), + SH_PFC_PIN_GROUP(msiof5_ss1), + SH_PFC_PIN_GROUP(msiof5_ss2), + SH_PFC_PIN_GROUP(msiof5_txd), + SH_PFC_PIN_GROUP(msiof5_rxd), + + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), + + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tmu_tclk3), + SH_PFC_PIN_GROUP(tmu_tclk4), + + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), +}; + +static const char * const avb0_groups[] = { + "avb0_link", + "avb0_magic", + "avb0_phy_int", + "avb0_mdio", + "avb0_rgmii", + "avb0_txcrefclk", + "avb0_avtp_pps", + "avb0_avtp_capture", + "avb0_avtp_match", +}; + +static const char * const avb1_groups[] = { + "avb1_link", + "avb1_magic", + "avb1_phy_int", + "avb1_mdio", + "avb1_rgmii", + "avb1_txcrefclk", + "avb1_avtp_pps", + "avb1_avtp_capture", + "avb1_avtp_match", +}; + +static const char * const avb2_groups[] = { + "avb2_link", + "avb2_magic", + "avb2_phy_int", + "avb2_mdio", + "avb2_rgmii", + "avb2_txcrefclk", + "avb2_avtp_pps", + "avb2_avtp_capture", + "avb2_avtp_match", +}; + +static const char * const avb3_groups[] = { + "avb3_link", + "avb3_magic", + "avb3_phy_int", + "avb3_mdio", + "avb3_rgmii", + "avb3_txcrefclk", + "avb3_avtp_pps", + "avb3_avtp_capture", + "avb3_avtp_match", +}; + +static const char * const avb4_groups[] = { + "avb4_link", + "avb4_magic", + "avb4_phy_int", + "avb4_mdio", + "avb4_rgmii", + "avb4_txcrefclk", + "avb4_avtp_pps", + "avb4_avtp_capture", + "avb4_avtp_match", +}; + +static const char * const avb5_groups[] = { + "avb5_link", + "avb5_magic", + "avb5_phy_int", + "avb5_mdio", + "avb5_rgmii", + "avb5_txcrefclk", + "avb5_avtp_pps", + "avb5_avtp_capture", + "avb5_avtp_match", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + +static const char * const canfd2_groups[] = { + "canfd2_data", +}; + +static const char * const canfd3_groups[] = { + "canfd3_data", +}; + +static const char * const canfd4_groups[] = { + "canfd4_data", +}; + +static const char * const canfd5_groups[] = { + "canfd5_data", +}; + +static const char * const canfd6_groups[] = { + "canfd6_data", +}; + +static const char * const canfd7_groups[] = { + "canfd7_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const du_groups[] = { + "du_rgb888", + "du_clk_out", + "du_sync", + "du_oddf", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data", + "hscif3_clk", + "hscif3_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c4_groups[] = { + "i2c4", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + +static const char * const i2c6_groups[] = { + "i2c6", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", + "mmc_ds", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_txd", + "msiof3_rxd", +}; + +static const char * const msiof4_groups[] = { + "msiof4_clk", + "msiof4_sync", + "msiof4_ss1", + "msiof4_ss2", + "msiof4_txd", + "msiof4_rxd", +}; + +static const char * const msiof5_groups[] = { + "msiof5_clk", + "msiof5_sync", + "msiof5_ss1", + "msiof5_ss2", + "msiof5_txd", + "msiof5_rxd", +}; + +static const char * const pwm0_groups[] = { + "pwm0", +}; + +static const char * const pwm1_groups[] = { + "pwm1", +}; + +static const char * const pwm2_groups[] = { + "pwm2", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", +}; + +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_data_b", + "scif1_clk", + "scif1_ctrl", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_ctrl", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_ctrl", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const tmu_groups[] = { + "tmu_tclk1_a", + "tmu_tclk1_b", + "tmu_tclk2_a", + "tmu_tclk2_b", + "tmu_tclk3", + "tmu_tclk4", +}; + +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb0), + SH_PFC_FUNCTION(avb1), + SH_PFC_FUNCTION(avb2), + SH_PFC_FUNCTION(avb3), + SH_PFC_FUNCTION(avb4), + SH_PFC_FUNCTION(avb5), + + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(canfd2), + SH_PFC_FUNCTION(canfd3), + SH_PFC_FUNCTION(canfd4), + SH_PFC_FUNCTION(canfd5), + SH_PFC_FUNCTION(canfd6), + SH_PFC_FUNCTION(canfd7), + SH_PFC_FUNCTION(can_clk), + + SH_PFC_FUNCTION(du), + + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + + SH_PFC_FUNCTION(intc_ex), + + SH_PFC_FUNCTION(mmc), + + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(msiof4), + SH_PFC_FUNCTION(msiof5), + + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + + SH_PFC_FUNCTION(tmu), + + SH_PFC_FUNCTION(tpu), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_27_FN, GPSR0_27, + GP_0_26_FN, GPSR0_26, + GP_0_25_FN, GPSR0_25, + GP_0_24_FN, GPSR0_24, + GP_0_23_FN, GPSR0_23, + GP_0_22_FN, GPSR0_22, + GP_0_21_FN, GPSR0_21, + GP_0_20_FN, GPSR0_20, + GP_0_19_FN, GPSR0_19, + GP_0_18_FN, GPSR0_18, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, )) + }, + { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP( + 0, 0, + GP_1_30_FN, GPSR1_30, + GP_1_29_FN, GPSR1_29, + GP_1_28_FN, GPSR1_28, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, )) + }, + { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_24_FN, GPSR2_24, + GP_2_23_FN, GPSR2_23, + GP_2_22_FN, GPSR2_22, + GP_2_21_FN, GPSR2_21, + GP_2_20_FN, GPSR2_20, + GP_2_19_FN, GPSR2_19, + GP_2_18_FN, GPSR2_18, + GP_2_17_FN, GPSR2_17, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, )) + }, + { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_16_FN, GPSR3_16, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, )) + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_26_FN, GPSR4_26, + GP_4_25_FN, GPSR4_25, + GP_4_24_FN, GPSR4_24, + GP_4_23_FN, GPSR4_23, + GP_4_22_FN, GPSR4_22, + GP_4_21_FN, GPSR4_21, + GP_4_20_FN, GPSR4_20, + GP_4_19_FN, GPSR4_19, + GP_4_18_FN, GPSR4_18, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, )) + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, )) + }, + { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_20_FN, GPSR6_20, + GP_6_19_FN, GPSR6_19, + GP_6_18_FN, GPSR6_18, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, )) + }, + { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_20_FN, GPSR7_20, + GP_7_19_FN, GPSR7_19, + GP_7_18_FN, GPSR7_18, + GP_7_17_FN, GPSR7_17, + GP_7_16_FN, GPSR7_16, + GP_7_15_FN, GPSR7_15, + GP_7_14_FN, GPSR7_14, + GP_7_13_FN, GPSR7_13, + GP_7_12_FN, GPSR7_12, + GP_7_11_FN, GPSR7_11, + GP_7_10_FN, GPSR7_10, + GP_7_9_FN, GPSR7_9, + GP_7_8_FN, GPSR7_8, + GP_7_7_FN, GPSR7_7, + GP_7_6_FN, GPSR7_6, + GP_7_5_FN, GPSR7_5, + GP_7_4_FN, GPSR7_4, + GP_7_3_FN, GPSR7_3, + GP_7_2_FN, GPSR7_2, + GP_7_1_FN, GPSR7_1, + GP_7_0_FN, GPSR7_0, )) + }, + { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_8_20_FN, GPSR8_20, + GP_8_19_FN, GPSR8_19, + GP_8_18_FN, GPSR8_18, + GP_8_17_FN, GPSR8_17, + GP_8_16_FN, GPSR8_16, + GP_8_15_FN, GPSR8_15, + GP_8_14_FN, GPSR8_14, + GP_8_13_FN, GPSR8_13, + GP_8_12_FN, GPSR8_12, + GP_8_11_FN, GPSR8_11, + GP_8_10_FN, GPSR8_10, + GP_8_9_FN, GPSR8_9, + GP_8_8_FN, GPSR8_8, + GP_8_7_FN, GPSR8_7, + GP_8_6_FN, GPSR8_6, + GP_8_5_FN, GPSR8_5, + GP_8_4_FN, GPSR8_4, + GP_8_3_FN, GPSR8_3, + GP_8_2_FN, GPSR8_2, + GP_8_1_FN, GPSR8_1, + GP_8_0_FN, GPSR8_0, )) + }, + { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_9_20_FN, GPSR9_20, + GP_9_19_FN, GPSR9_19, + GP_9_18_FN, GPSR9_18, + GP_9_17_FN, GPSR9_17, + GP_9_16_FN, GPSR9_16, + GP_9_15_FN, GPSR9_15, + GP_9_14_FN, GPSR9_14, + GP_9_13_FN, GPSR9_13, + GP_9_12_FN, GPSR9_12, + GP_9_11_FN, GPSR9_11, + GP_9_10_FN, GPSR9_10, + GP_9_9_FN, GPSR9_9, + GP_9_8_FN, GPSR9_8, + GP_9_7_FN, GPSR9_7, + GP_9_6_FN, GPSR9_6, + GP_9_5_FN, GPSR9_5, + GP_9_4_FN, GPSR9_4, + GP_9_3_FN, GPSR9_3, + GP_9_2_FN, GPSR9_2, + GP_9_1_FN, GPSR9_1, + GP_9_0_FN, GPSR9_0, )) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP( + IP0SR1_31_28 + IP0SR1_27_24 + IP0SR1_23_20 + IP0SR1_19_16 + IP0SR1_15_12 + IP0SR1_11_8 + IP0SR1_7_4 + IP0SR1_3_0)) + }, + { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP( + IP1SR1_31_28 + IP1SR1_27_24 + IP1SR1_23_20 + IP1SR1_19_16 + IP1SR1_15_12 + IP1SR1_11_8 + IP1SR1_7_4 + IP1SR1_3_0)) + }, + { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP( + IP2SR1_31_28 + IP2SR1_27_24 + IP2SR1_23_20 + IP2SR1_19_16 + IP2SR1_15_12 + IP2SR1_11_8 + IP2SR1_7_4 + IP2SR1_3_0)) + }, + { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP( + IP3SR1_31_28 + IP3SR1_27_24 + IP3SR1_23_20 + IP3SR1_19_16 + IP3SR1_15_12 + IP3SR1_11_8 + IP3SR1_7_4 + IP3SR1_3_0)) + }, + { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP( + IP0SR2_31_28 + IP0SR2_27_24 + IP0SR2_23_20 + IP0SR2_19_16 + IP0SR2_15_12 + IP0SR2_11_8 + IP0SR2_7_4 + IP0SR2_3_0)) + }, + { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP( + IP1SR2_31_28 + IP1SR2_27_24 + IP1SR2_23_20 + IP1SR2_19_16 + IP1SR2_15_12 + IP1SR2_11_8 + IP1SR2_7_4 + IP1SR2_3_0)) + }, + { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP( + IP2SR2_31_28 + IP2SR2_27_24 + IP2SR2_23_20 + IP2SR2_19_16 + IP2SR2_15_12 + IP2SR2_11_8 + IP2SR2_7_4 + IP2SR2_3_0)) + }, + { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP( + IP0SR3_31_28 + IP0SR3_27_24 + IP0SR3_23_20 + IP0SR3_19_16 + IP0SR3_15_12 + IP0SR3_11_8 + IP0SR3_7_4 + IP0SR3_3_0)) + }, + { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP( + IP1SR3_31_28 + IP1SR3_27_24 + IP1SR3_23_20 + IP1SR3_19_16 + IP1SR3_15_12 + IP1SR3_11_8 + IP1SR3_7_4 + IP1SR3_3_0)) + }, + { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP( + IP0SR4_31_28 + IP0SR4_27_24 + IP0SR4_23_20 + IP0SR4_19_16 + IP0SR4_15_12 + IP0SR4_11_8 + IP0SR4_7_4 + IP0SR4_3_0)) + }, + { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP( + IP1SR4_31_28 + IP1SR4_27_24 + IP1SR4_23_20 + IP1SR4_19_16 + IP1SR4_15_12 + IP1SR4_11_8 + IP1SR4_7_4 + IP1SR4_3_0)) + }, + { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP( + IP2SR4_31_28 + IP2SR4_27_24 + IP2SR4_23_20 + IP2SR4_19_16 + IP2SR4_15_12 + IP2SR4_11_8 + IP2SR4_7_4 + IP2SR4_3_0)) + }, + { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP( + IP0SR5_31_28 + IP0SR5_27_24 + IP0SR5_23_20 + IP0SR5_19_16 + IP0SR5_15_12 + IP0SR5_11_8 + IP0SR5_7_4 + IP0SR5_3_0)) + }, + { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP( + IP1SR5_31_28 + IP1SR5_27_24 + IP1SR5_23_20 + IP1SR5_19_16 + IP1SR5_15_12 + IP1SR5_11_8 + IP1SR5_7_4 + IP1SR5_3_0)) + }, + { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP( + IP2SR5_31_28 + IP2SR5_27_24 + IP2SR5_23_20 + IP2SR5_19_16 + IP2SR5_15_12 + IP2SR5_11_8 + IP2SR5_7_4 + IP2SR5_3_0)) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32, + GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1), + GROUP( + /* RESERVED 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL2_14_15 + MOD_SEL2_12_13 + MOD_SEL2_10_11 + MOD_SEL2_8_9 + MOD_SEL2_6_7 + MOD_SEL2_4_5 + MOD_SEL2_2_3 + 0, 0, + 0, 0, )) + }, + { }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) { + { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ + { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */ + { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */ + { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */ + { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */ + { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */ + { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */ + { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) { + { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */ + { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */ + { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */ + { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */ + { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */ + { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */ + { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */ + { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) { + { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */ + { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */ + { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */ + { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */ + { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */ + { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */ + { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */ + { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) { + { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */ + { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */ + { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */ + { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) { + { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */ + { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */ + { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */ + { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */ + { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) { + { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */ + { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */ + { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */ + { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */ + { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) { + { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */ + { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */ + { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */ + { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */ + { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */ + { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */ + { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) { + { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */ + { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */ + { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */ + { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) { + { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */ + { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */ + { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */ + { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */ + { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */ + { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */ + { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */ + { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) { + { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */ + { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */ + { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */ + { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */ + { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */ + { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */ + { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */ + { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) { + { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */ + { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */ + { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */ + { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */ + { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */ + { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */ + { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */ + { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) { + { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) { + { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */ + { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */ + { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */ + { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */ + { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */ + { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */ + { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */ + { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) { + { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */ + { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */ + { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */ + { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */ + { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */ + { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/ + { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) { + { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) { + { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */ + { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */ + { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */ + { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */ + { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */ + { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */ + { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */ + { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) { + { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */ + { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */ + { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */ + { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */ + { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */ + { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */ + { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/ + { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) { + { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */ + { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */ + { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ + { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */ + { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */ + { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */ + { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */ + { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) { + { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */ + { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */ + { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) { + { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */ + { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */ + { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */ + { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */ + { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */ + { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */ + { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */ + { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) { + { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */ + { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */ + { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */ + { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */ + { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */ + { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */ + { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/ + { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) { + { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */ + { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */ + { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */ + { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */ + { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) { + { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */ + { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */ + { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */ + { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */ + { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */ + { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */ + { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */ + { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) { + { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */ + { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */ + { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */ + { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */ + { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */ + { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */ + { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/ + { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) { + { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */ + { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */ + { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */ + { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */ + { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) { + { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */ + { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */ + { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */ + { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */ + { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */ + { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */ + { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */ + { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) { + { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */ + { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */ + { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */ + { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */ + { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */ + { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */ + { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/ + { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) { + { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */ + { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */ + { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */ + { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */ + { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) { + { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */ + { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */ + { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */ + { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */ + { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */ + { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */ + { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */ + { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) { + { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */ + { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */ + { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */ + { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */ + { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */ + { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */ + { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/ + { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) { + { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */ + { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */ + { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */ + { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */ + { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) { + { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */ + { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */ + { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */ + { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */ + { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */ + { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */ + { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */ + { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) { + { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */ + { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */ + { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */ + { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */ + { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */ + { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */ + { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/ + { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) { + { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */ + { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */ + { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */ + { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */ + { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */ + } }, + { }, +}; + +enum ioctrl_regs { + POC0, + POC1, + POC2, + POC4, + POC5, + POC6, + POC7, + POC8, + POC9, + TD1SEL0, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POC0] = { 0xe60580a0, }, + [POC1] = { 0xe60500a0, }, + [POC2] = { 0xe60508a0, }, + [POC4] = { 0xe60600a0, }, + [POC5] = { 0xe60608a0, }, + [POC6] = { 0xe60680a0, }, + [POC7] = { 0xe60688a0, }, + [POC8] = { 0xe60690a0, }, + [POC9] = { 0xe60698a0, }, + [TD1SEL0] = { 0xe6058124, }, + { /* sentinel */ }, +}; + +static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[POC0].reg; + if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC1].reg; + if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC2].reg; + if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC4].reg; + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC5].reg; + if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC6].reg; + if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC7].reg; + if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC8].reg; + if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC9].reg; + if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17)) + return bit; + + return -EINVAL; +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) { + [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */ + [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */ + [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */ + [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */ + [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */ + [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */ + [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */ + [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */ + [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */ + [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */ + [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */ + [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */ + [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */ + [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */ + [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */ + [15] = RCAR_GP_PIN(0, 15), /* SD_WP */ + [16] = RCAR_GP_PIN(0, 16), /* SD_CD */ + [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */ + [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */ + [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */ + [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */ + [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */ + [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */ + [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */ + [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */ + [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */ + [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */ + [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */ + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) { + [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */ + [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */ + [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */ + [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */ + [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */ + [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */ + [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */ + [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */ + [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */ + [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */ + [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */ + [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */ + [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */ + [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */ + [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */ + [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */ + [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */ + [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */ + [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */ + [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */ + [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */ + [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */ + [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */ + [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */ + [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */ + [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */ + [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */ + [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */ + [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */ + [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */ + [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */ + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) { + [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */ + [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */ + [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */ + [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */ + [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */ + [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */ + [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */ + [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */ + [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */ + [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */ + [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */ + [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */ + [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */ + [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */ + [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */ + [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */ + [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */ + [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */ + [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */ + [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */ + [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */ + [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */ + [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */ + [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */ + [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */ + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) { + [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */ + [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */ + [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */ + [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */ + [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */ + [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */ + [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */ + [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */ + [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */ + [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */ + [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */ + [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */ + [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */ + [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */ + [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */ + [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */ + [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) { + [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */ + [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */ + [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */ + [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */ + [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */ + [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */ + [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */ + [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */ + [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */ + [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */ + [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */ + [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */ + [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */ + [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */ + [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */ + [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */ + [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */ + [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */ + [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */ + [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */ + [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ + [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */ + [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */ + [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */ + [25] = RCAR_GP_PIN(4, 25), /* AVS0 */ + [26] = RCAR_GP_PIN(4, 26), /* AVS1 */ + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) { + [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */ + [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */ + [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */ + [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */ + [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */ + [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */ + [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */ + [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */ + [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */ + [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */ + [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */ + [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */ + [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */ + [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */ + [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */ + [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */ + [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */ + [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */ + [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */ + [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) { + [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */ + [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */ + [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */ + [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */ + [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */ + [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */ + [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */ + [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */ + [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */ + [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */ + [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */ + [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */ + [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */ + [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */ + [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/ + [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */ + [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */ + [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */ + [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */ + [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) { + [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */ + [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */ + [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */ + [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */ + [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */ + [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */ + [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */ + [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */ + [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */ + [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */ + [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */ + [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */ + [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */ + [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */ + [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */ + [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */ + [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */ + [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */ + [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */ + [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) { + [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */ + [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */ + [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */ + [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */ + [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */ + [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */ + [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */ + [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */ + [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */ + [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */ + [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */ + [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */ + [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */ + [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */ + [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */ + [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */ + [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */ + [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */ + [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */ + [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) { + [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */ + [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */ + [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */ + [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */ + [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */ + [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */ + [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */ + [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */ + [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */ + [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */ + [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */ + [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */ + [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */ + [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */ + [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */ + [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */ + [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */ + [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */ + [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */ + [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static unsigned int r8a779a0_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +static void r8a779a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + u32 enable, updown; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= BIT(bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); +} + +static const struct sh_pfc_soc_operations pinmux_ops = { + .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, + .get_bias = r8a779a0_pinmux_get_bias, + .set_bias = r8a779a0_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a779a0_pinmux_info = { + .name = "r8a779a0_pfc", + .ops = &pinmux_ops, + .unlock_reg = 0x1ff, /* PMMRn mask */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 2498eb57164..490d34e56b8 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -41,6 +41,7 @@ enum sh_pfc_model { SH_PFC_R8A77980, SH_PFC_R8A77990, SH_PFC_R8A77995, + SH_PFC_R8A779A0, }; struct sh_pfc_pin_config { @@ -955,6 +956,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A77995) priv->pfc.info = &r8a77995_pinmux_info; #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779A0 + if (model == SH_PFC_R8A779A0) + priv->pfc.info = &r8a779a0_pinmux_info; +#endif priv->pmx.pfc = &priv->pfc; sh_pfc_init_ranges(&priv->pfc); @@ -1060,6 +1065,13 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A77995, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779A0 + { + .compatible = "renesas,pfc-r8a779a0", + .data = SH_PFC_R8A779A0, + }, +#endif + { }, }; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 48d737a1414..c94757b9a2c 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -319,6 +319,7 @@ extern const struct sh_pfc_soc_info r8a77970_pinmux_info; extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; +extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; /* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists From b6ec11b62ddee0b4e1df558e98a017fc489a1247 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 25 Apr 2021 22:28:00 +0200 Subject: [PATCH 195/250] ARM: dts: renesas: Add R8A779A0 V3U DTs and headers Import R8A779A0 V3U DTs and headers from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779a0.dtsi | 970 ++++++++++++++++++ include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 + include/dt-bindings/power/r8a779a0-sysc.h | 59 ++ 3 files changed, 1084 insertions(+) create mode 100644 arch/arm/dts/r8a779a0.dtsi create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a779a0-sysc.h diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi new file mode 100644 index 00000000000..dfd6ae8b564 --- /dev/null +++ b/arch/arm/dts/r8a779a0.dtsi @@ -0,0 +1,970 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car V3U (R8A779A0) SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779a0"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779A0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779a0-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + + pfc: pin-controller@e6050000 { + compatible = "renesas,pfc-r8a779a0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, + <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + }; + + gpio0: gpio@e6058180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6058180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 28>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6050180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 31>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6050980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6050980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6058980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6060180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 128 27>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6060980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 160 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@e6068180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6068180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 192 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@e6068980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6068980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 224 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@e6069180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6069180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 256 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio9: gpio@e6069980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6069980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 288 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779a0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779a0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779a0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + dmas = <&dmac1 0x99>, <&dmac1 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + dmas = <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 524>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 524>; + dmas = <&dmac1 0x9d>, <&dmac1 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 211>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6810000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 212>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 213>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb3: ethernet@e6830000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6830000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 214>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 214>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb4: ethernet@e6840000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6840000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 215>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 215>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb5: ethernet@e6850000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6850000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 216>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 216>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 618>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 619>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + dmas = <&dmac1 0x45>, <&dmac1 0x44>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + dmas = <&dmac1 0x47>, <&dmac1 0x46>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof4: spi@e6c20000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + dmas = <&dmac1 0x49>, <&dmac1 0x48>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof5: spi@e6c28000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c28000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + dmas = <&dmac1 0x4b>, <&dmac1 0x4a>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac1: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779a0"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779a0"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779a0", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h new file mode 100644 index 00000000000..f1d737ca7ca --- /dev/null +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ + +#include + +/* r8a779A0 CPG Core Clocks */ +#define R8A779A0_CLK_Z0 0 +#define R8A779A0_CLK_ZX 1 +#define R8A779A0_CLK_Z1 2 +#define R8A779A0_CLK_ZR 3 +#define R8A779A0_CLK_ZS 4 +#define R8A779A0_CLK_ZT 5 +#define R8A779A0_CLK_ZTR 6 +#define R8A779A0_CLK_S1D1 7 +#define R8A779A0_CLK_S1D2 8 +#define R8A779A0_CLK_S1D4 9 +#define R8A779A0_CLK_S1D8 10 +#define R8A779A0_CLK_S1D12 11 +#define R8A779A0_CLK_S3D1 12 +#define R8A779A0_CLK_S3D2 13 +#define R8A779A0_CLK_S3D4 14 +#define R8A779A0_CLK_LB 15 +#define R8A779A0_CLK_CP 16 +#define R8A779A0_CLK_CL 17 +#define R8A779A0_CLK_CL16MCK 18 +#define R8A779A0_CLK_ZB30 19 +#define R8A779A0_CLK_ZB30D2 20 +#define R8A779A0_CLK_ZB30D4 21 +#define R8A779A0_CLK_ZB31 22 +#define R8A779A0_CLK_ZB31D2 23 +#define R8A779A0_CLK_ZB31D4 24 +#define R8A779A0_CLK_SD0H 25 +#define R8A779A0_CLK_SD0 26 +#define R8A779A0_CLK_RPC 27 +#define R8A779A0_CLK_RPCD2 28 +#define R8A779A0_CLK_MSO 29 +#define R8A779A0_CLK_CANFD 30 +#define R8A779A0_CLK_CSI0 31 +#define R8A779A0_CLK_FRAY 32 +#define R8A779A0_CLK_DSI 33 +#define R8A779A0_CLK_VIP 34 +#define R8A779A0_CLK_ADGH 35 +#define R8A779A0_CLK_CNNDSP 36 +#define R8A779A0_CLK_ICU 37 +#define R8A779A0_CLK_ICUD2 38 +#define R8A779A0_CLK_VCBUS 39 +#define R8A779A0_CLK_CBFUSA 40 +#define R8A779A0_CLK_R 41 +#define R8A779A0_CLK_OSC 42 + +#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h new file mode 100644 index 00000000000..57929e459a6 --- /dev/null +++ b/include/dt-bindings/power/r8a779a0-sysc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779A0_PD_A1E0D0C0 0 +#define R8A779A0_PD_A1E0D0C1 1 +#define R8A779A0_PD_A1E0D1C0 2 +#define R8A779A0_PD_A1E0D1C1 3 +#define R8A779A0_PD_A1E1D0C0 4 +#define R8A779A0_PD_A1E1D0C1 5 +#define R8A779A0_PD_A1E1D1C0 6 +#define R8A779A0_PD_A1E1D1C1 7 +#define R8A779A0_PD_A2E0D0 16 +#define R8A779A0_PD_A2E0D1 17 +#define R8A779A0_PD_A2E1D0 18 +#define R8A779A0_PD_A2E1D1 19 +#define R8A779A0_PD_A3E0 20 +#define R8A779A0_PD_A3E1 21 +#define R8A779A0_PD_3DG_A 24 +#define R8A779A0_PD_3DG_B 25 +#define R8A779A0_PD_A1CNN2 32 +#define R8A779A0_PD_A1DSP0 33 +#define R8A779A0_PD_A2IMP01 34 +#define R8A779A0_PD_A2DP0 35 +#define R8A779A0_PD_A2CV0 36 +#define R8A779A0_PD_A2CV1 37 +#define R8A779A0_PD_A2CV4 38 +#define R8A779A0_PD_A2CV6 39 +#define R8A779A0_PD_A2CN2 40 +#define R8A779A0_PD_A1CNN0 41 +#define R8A779A0_PD_A2CN0 42 +#define R8A779A0_PD_A3IR 43 +#define R8A779A0_PD_A1CNN1 44 +#define R8A779A0_PD_A1DSP1 45 +#define R8A779A0_PD_A2IMP23 46 +#define R8A779A0_PD_A2DP1 47 +#define R8A779A0_PD_A2CV2 48 +#define R8A779A0_PD_A2CV3 49 +#define R8A779A0_PD_A2CV5 50 +#define R8A779A0_PD_A2CV7 51 +#define R8A779A0_PD_A2CN1 52 +#define R8A779A0_PD_A3VIP0 56 +#define R8A779A0_PD_A3VIP1 57 +#define R8A779A0_PD_A3VIP2 58 +#define R8A779A0_PD_A3VIP3 59 +#define R8A779A0_PD_A3ISP01 60 +#define R8A779A0_PD_A3ISP23 61 + +/* Always-on power area */ +#define R8A779A0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */ From 6232d0a74037c07bfaacd451c0560e97616d6f6f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 25 Apr 2021 22:28:00 +0200 Subject: [PATCH 196/250] ARM: dts: renesas: Add R8A779A0 V3U Falcon DTs Import R8A779A0 V3U Falcon DTs from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779a0-falcon-cpu.dtsi | 184 ++++++++++++++++++++++++++ arch/arm/dts/r8a779a0-falcon.dts | 28 ++++ 2 files changed, 212 insertions(+) create mode 100644 arch/arm/dts/r8a779a0-falcon-cpu.dtsi create mode 100644 arch/arm/dts/r8a779a0-falcon.dts diff --git a/arch/arm/dts/r8a779a0-falcon-cpu.dtsi b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi new file mode 100644 index 00000000000..fa284a7260d --- /dev/null +++ b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Falcon CPU board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include "r8a779a0.dtsi" + +/ { + model = "Renesas Falcon CPU board"; + compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c6 { + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + i2c6_pins: i2c6 { + groups = "i2c6"; + function = "i2c6"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts new file mode 100644 index 00000000000..5617b81dd7d --- /dev/null +++ b/arch/arm/dts/r8a779a0-falcon.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Falcon CPU and BreakOut boards + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779a0-falcon-cpu.dtsi" + +/ { + model = "Renesas Falcon CPU and Breakout boards based on r8a779a0"; + compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; + + aliases { + ethernet0 = &avb0; + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; From b35fc0dabd0d7df5247f9c5be79d3ae8de5fce82 Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Thu, 21 May 2020 17:37:33 +0700 Subject: [PATCH 197/250] ARM: dts: renesas: Add R8A779A0 V3U DT extras Add R8A779A0 V3U DT extras for U-Boot. Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs" by Hai Pham Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779a0-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm/dts/r8a779a0-u-boot.dtsi diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi new file mode 100644 index 00000000000..f6101289e88 --- /dev/null +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + u-boot,dm-pre-reloc; +}; From ae3c0d42fa8e816efd7a0e682623b37de21d5a7f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 25 Apr 2021 23:00:21 +0200 Subject: [PATCH 198/250] ARM: dts: renesas: Add RPC node to R8A779A0 V3U The R-Car V3U does support RPC interface, however the support for it is missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"), add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779a0-u-boot.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi index f6101289e88..83dbe3f20ef 100644 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -7,6 +7,19 @@ #include "r8a779x-u-boot.dtsi" +/ { + soc { + rpc: spi@ee200000 { + compatible = "renesas,rpc-r8a779a0", "renesas,rcar-gen3-rpc"; + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; + clocks = <&cpg CPG_MOD 629>; + bank-width = <2>; + num-cs = <1>; + status = "disabled"; + }; + }; +}; + &extalr_clk { u-boot,dm-pre-reloc; }; From 0f08fa49643dd2218122b7adca62e7a5c19486cd Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Thu, 21 May 2020 14:11:13 +0700 Subject: [PATCH 199/250] ARM: renesas: Add R8A779A0 V3U platform code Add platform code to support R8A779A0 V3U SoC. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- arch/arm/mach-rmobile/Kconfig.64 | 5 +++++ arch/arm/mach-rmobile/cpu_info.c | 1 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + 3 files changed, 7 insertions(+) diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 3f7ec053795..e22012e3b84 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -57,6 +57,11 @@ config R8A77995 imply CLK_R8A77995 imply PINCTRL_PFC_R8A77995 +config R8A779A0 + bool "Renesas SoC R8A779A0" + imply CLK_R8A779A0 + imply PINCTRL_PFC_R8A779A0 + config RZ_G2 bool "Renesas ARM SoCs RZ/G2 (64bit)" diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 9ec622bdb51..2bb6d502b87 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -76,6 +76,7 @@ static const struct { { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" }, { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" }, { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" }, + { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index a688636141e..dc6f87631bc 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -39,6 +39,7 @@ #define RMOBILE_CPU_TYPE_R8A77980 0x56 #define RMOBILE_CPU_TYPE_R8A77990 0x57 #define RMOBILE_CPU_TYPE_R8A77995 0x58 +#define RMOBILE_CPU_TYPE_R8A779A0 0x59 #ifndef __ASSEMBLY__ const u8 *rzg_get_cpu_name(void); From 4cfdcf39482640527e6ca8e8c092a43bff3599c4 Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Thu, 21 May 2020 20:14:05 +0700 Subject: [PATCH 200/250] ARM: renesas: Add R8A779A0 V3U Falcon board code Add board code for the R8A779A0 V3U Falcon board. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut -- Marek: - various small rebase fixes and clean ups --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/r8a779a0-falcon-u-boot.dts | 32 +++++++++++++ arch/arm/mach-rmobile/Kconfig.64 | 7 +++ board/renesas/falcon/Kconfig | 15 ++++++ board/renesas/falcon/MAINTAINERS | 6 +++ board/renesas/falcon/Makefile | 13 +++++ board/renesas/falcon/falcon.c | 47 ++++++++++++++++++ configs/r8a779a0_falcon_defconfig | 64 +++++++++++++++++++++++++ include/configs/falcon.h | 25 ++++++++++ 9 files changed, 211 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r8a779a0-falcon-u-boot.dts create mode 100644 board/renesas/falcon/Kconfig create mode 100644 board/renesas/falcon/MAINTAINERS create mode 100644 board/renesas/falcon/Makefile create mode 100644 board/renesas/falcon/falcon.c create mode 100644 configs/r8a779a0_falcon_defconfig create mode 100644 include/configs/falcon.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e61..6610ce5c13c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -904,7 +904,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77970-eagle-u-boot.dtb \ r8a77980-condor-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \ - r8a77995-draak-u-boot.dtb + r8a77995-draak-u-boot.dtb \ + r8a779a0-falcon-u-boot.dtb ifdef CONFIG_RCAR_GEN3 DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dts b/arch/arm/dts/r8a779a0-falcon-u-boot.dts new file mode 100644 index 00000000000..06d3922a383 --- /dev/null +++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Falcon board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a779a0-falcon.dts" +#include "r8a779a0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&rpc { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + spi-max-frequency = <50000000>; + status = "okay"; + + spi-flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "okay"; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index e22012e3b84..8df90acb4ea 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -110,6 +110,12 @@ config TARGET_EBISU help Support for Renesas R-Car Gen3 Ebisu platform +config TARGET_FALCON + bool "Falcon board" + imply R8A779A0 + help + Support for Renesas R-Car Gen3 Falcon platform + config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" imply R8A774A1 @@ -160,6 +166,7 @@ source "board/renesas/condor/Kconfig" source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" +source "board/renesas/falcon/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" diff --git a/board/renesas/falcon/Kconfig b/board/renesas/falcon/Kconfig new file mode 100644 index 00000000000..1fcefa7e3cd --- /dev/null +++ b/board/renesas/falcon/Kconfig @@ -0,0 +1,15 @@ +if TARGET_FALCON + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "falcon" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "falcon" + +endif diff --git a/board/renesas/falcon/MAINTAINERS b/board/renesas/falcon/MAINTAINERS new file mode 100644 index 00000000000..2cacc91494f --- /dev/null +++ b/board/renesas/falcon/MAINTAINERS @@ -0,0 +1,6 @@ +FALCON BOARD +M: Marek Vasut +S: Maintained +F: board/renesas/falcon/ +F: include/configs/falcon.h +F: configs/r8a779a0_falcon_defconfig diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile new file mode 100644 index 00000000000..3b202c24fb1 --- /dev/null +++ b/board/renesas/falcon/Makefile @@ -0,0 +1,13 @@ +# +# board/renesas/falcon/Makefile +# +# Copyright (C) 2020 Renesas Electronics Corp. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := falcon.o ../rcar-common/common.o +endif diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c new file mode 100644 index 00000000000..3e591e4b425 --- /dev/null +++ b/board/renesas/falcon/falcon.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/renesas/falcon/falcon.c + * This file is Falcon board support. + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPR 0xE6150000 +#define CPGWPCR 0xE6150004 + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + return 0; +} + +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void reset_cpu(void) +{ + writel(RST_SPRES, RST_SRESCR0); +} diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig new file mode 100644 index 00000000000..dad8b77acf5 --- /dev/null +++ b/configs/r8a779a0_falcon_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0xC00000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xe6338000 +CONFIG_RCAR_GEN3=y +CONFIG_TARGET_FALCON=y +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot" +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/falcon.h b/include/configs/falcon.h new file mode 100644 index 00000000000..b9c82a7674d --- /dev/null +++ b/include/configs/falcon.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/falcon.h + * This file is Falcon board configuration. + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#ifndef __FALCON_H +#define __FALCON_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 16.66MHz */ +#define CONFIG_SYS_CLK_FREQ 16666666u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __FALCON_H */ From b3494132f068906a73e86826ffb7b19f4ad5ec5f Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Tue, 21 Jul 2020 15:21:53 +0900 Subject: [PATCH 201/250] ARM: renesas: Add generic timer initialization for V3U Falcon Init the Generic Timer for V3U Falcon in early phase Signed-off-by: Koji Matsuoka Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- board/renesas/falcon/falcon.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index 3e591e4b425..c3241bc21d2 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -20,6 +20,31 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGWPR 0xE6150000 #define CPGWPCR 0xE6150004 +#define EXTAL_CLK 16666600u +#define CNTCR_BASE 0xE6080000 +#define CNTFID0 (CNTCR_BASE + 0x020) +#define CNTCR_EN BIT(0) + +static void init_generic_timer(void) +{ + u32 freq; + + /* Set frequency data in CNTFID0 */ + freq = EXTAL_CLK; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +void s_init(void) +{ + init_generic_timer(); +} + int board_early_init_f(void) { /* Unlock CPG access */ From cdaa69c46eee3c75cca2f72296044d2bd1405343 Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Thu, 16 Jul 2020 12:11:16 +0900 Subject: [PATCH 202/250] ARM: renesas: Add GICv3 initialization for V3U Falcon Init GICv3 for V3U Falcon in early phase Signed-off-by: Koji Matsuoka Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- board/renesas/falcon/falcon.c | 29 +++++++++++++++++++++++++++++ include/configs/falcon.h | 11 +++++++++++ 2 files changed, 40 insertions(+) diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index c3241bc21d2..3e743847167 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -40,6 +40,33 @@ static void init_generic_timer(void) setbits_le32(CNTCR_BASE, CNTCR_EN); } +/* Distributor Registers */ +#define GICD_BASE 0xF1000000 + +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_LPI_BASE 0xF1060000 +#define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 +#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER) +#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR) + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_SGI_BASE 0xF1070000 +#define GICR_IGROUPR0 0x0080 + +static void init_gic_v3(void) +{ + /* GIC v3 power on */ + writel(0x00000002, (GICR_LPI_PWRR)); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER)); + while (readl(GICR_LPI_WAKER) & 0x00000004) + ; + + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); +} + void s_init(void) { init_generic_timer(); @@ -59,6 +86,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + init_gic_v3(); + return 0; } diff --git a/include/configs/falcon.h b/include/configs/falcon.h index b9c82a7674d..5ecbd1d3edd 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,6 +11,17 @@ #include "rcar-gen3-common.h" +/* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV2 +#undef CONFIG_GICV2 +#undef GICD_BASE +#undef GICC_BASE +#undef GICR_BASE +#endif +#define CONFIG_GICV3 +#define GICD_BASE 0xF1000000 +#define GICR_BASE 0xF1060000 + /* Ethernet RAVB */ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI From 0beaae223dd55b3f727f07f38b799a1c58612b1b Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 27 Oct 2020 19:06:51 +0700 Subject: [PATCH 203/250] ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon Enable basic PSCI support for R8A779A0 V3U Falcon Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- arch/arm/mach-rmobile/Makefile | 4 +++ arch/arm/mach-rmobile/psci-r8a779a0.c | 49 +++++++++++++++++++++++++++ configs/r8a779a0_falcon_defconfig | 1 + 3 files changed, 54 insertions(+) create mode 100644 arch/arm/mach-rmobile/psci-r8a779a0.c diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 81a0dedb41a..195bbeb5c88 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -15,6 +15,10 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o +ifneq ($(CONFIG_R8A779A0),) +obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o +endif + OBJCOPYFLAGS_u-boot-spl.srec := -O srec quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-rmobile/psci-r8a779a0.c new file mode 100644 index 00000000000..6a85eb22cac --- /dev/null +++ b/arch/arm/mach-rmobile/psci-r8a779a0.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file implements basic PSCI support for Renesas r8a779a0 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + */ + +#include +#include +#include +#include + +int __secure psci_features(u32 function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + return 0x0; + } + /* case ARM_PSCI_0_2_FN_CPU_ON: */ + /* case ARM_PSCI_0_2_FN_CPU_OFF: */ + /* case ARM_PSCI_0_2_FN_AFFINITY_INFO: */ + /* case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: */ + /* case ARM_PSCI_0_2_FN_SYSTEM_OFF: */ + return ARM_PSCI_RET_NI; +} + +u32 __secure psci_version(void) +{ + return ARM_PSCI_VER_0_2; +} + +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void __secure __noreturn psci_system_reset(void) +{ + writel(RST_SPRES, RST_SRESCR0); + + while (1) + ; +} + +int psci_update_dt(void *fdt) +{ + return 0; +} diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index dad8b77acf5..8df647acfb5 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_FALCON=y # CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y From 0d7066bce23d3732cd3a59176ccd7a3ee7be9d63 Mon Sep 17 00:00:00 2001 From: Zhengxun Date: Wed, 23 Jun 2021 17:15:15 +0000 Subject: [PATCH 204/250] spi: Add MXIC controller driver Add a driver for Macronix SPI controller IP. This patch referred from linux spi-mxic.c. The difference from the linux version is described here. 1. To adapt uboot spi framework, modify some functions naming. 2. Remove the incompatible functions of Uboot. 3. Add dummy byte recalculattion function to support dummy buswidth not align data buswidth operation.(ex: 1-1-4, 1-1-8) 4. Add Octal mode support. Signed-off-by: Zhengxun Reviewed-by: Jagan Teki [jagan: fixed file permission, comment line, kconfig] Signed-off-by: Jagan Teki --- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-mxic.c | 547 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 555 insertions(+) create mode 100644 drivers/spi/spi-mxic.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1494c917635..e317d8a2c64 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -255,6 +255,13 @@ config MXS_SPI Enable the MXS SPI controller driver. This driver can be used on the i.MX23 and i.MX28 SoCs. +config SPI_MXIC + bool "Macronix MX25F0A SPI controller" + help + Enable the Macronix MX25F0A SPI controller driver. This driver + can be used to access the SPI flash on platforms embedding + this Macronix IP core. + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cfe4fae1d4b..3dc83089b8f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_PIC32_SPI) += pic32_spi.o obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_SPI_QUP) += spi-qup.o +obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c new file mode 100644 index 00000000000..6aae9f79556 --- /dev/null +++ b/drivers/spi/spi-mxic.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Macronix International Co., Ltd. + * + * Authors: + * zhengxunli + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HC_CFG 0x0 +#define HC_CFG_IF_CFG(x) ((x) << 27) +#define HC_CFG_DUAL_SLAVE BIT(31) +#define HC_CFG_INDIVIDUAL BIT(30) +#define HC_CFG_NIO(x) (((x) / 4) << 27) +#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2))) +#define HC_CFG_TYPE_SPI_NOR 0 +#define HC_CFG_TYPE_SPI_NAND 1 +#define HC_CFG_TYPE_SPI_RAM 2 +#define HC_CFG_TYPE_RAW_NAND 3 +#define HC_CFG_SLV_ACT(x) ((x) << 21) +#define HC_CFG_CLK_PH_EN BIT(20) +#define HC_CFG_CLK_POL_INV BIT(19) +#define HC_CFG_BIG_ENDIAN BIT(18) +#define HC_CFG_DATA_PASS BIT(17) +#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16) +#define HC_CFG_MAN_START_EN BIT(3) +#define HC_CFG_MAN_START BIT(2) +#define HC_CFG_MAN_CS_EN BIT(1) +#define HC_CFG_MAN_CS_ASSERT BIT(0) + +#define INT_STS 0x4 +#define INT_STS_EN 0x8 +#define INT_SIG_EN 0xc +#define INT_STS_ALL GENMASK(31, 0) +#define INT_RDY_PIN BIT(26) +#define INT_RDY_SR BIT(25) +#define INT_LNR_SUSP BIT(24) +#define INT_ECC_ERR BIT(17) +#define INT_CRC_ERR BIT(16) +#define INT_LWR_DIS BIT(12) +#define INT_LRD_DIS BIT(11) +#define INT_SDMA_INT BIT(10) +#define INT_DMA_FINISH BIT(9) +#define INT_RX_NOT_FULL BIT(3) +#define INT_RX_NOT_EMPTY BIT(2) +#define INT_TX_NOT_FULL BIT(1) +#define INT_TX_EMPTY BIT(0) + +#define HC_EN 0x10 +#define HC_EN_BIT BIT(0) + +#define TXD(x) (0x14 + ((x) * 4)) +#define RXD 0x24 + +#define SS_CTRL(s) (0x30 + ((s) * 4)) +#define LRD_CFG 0x44 +#define LWR_CFG 0x80 +#define RWW_CFG 0x70 +#define OP_READ BIT(23) +#define OP_DUMMY_CYC(x) ((x) << 17) +#define OP_ADDR_BYTES(x) ((x) << 14) +#define OP_CMD_BYTES(x) (((x) - 1) << 13) +#define OP_OCTA_CRC_EN BIT(12) +#define OP_DQS_EN BIT(11) +#define OP_ENHC_EN BIT(10) +#define OP_PREAMBLE_EN BIT(9) +#define OP_DATA_DDR BIT(8) +#define OP_DATA_BUSW(x) ((x) << 6) +#define OP_ADDR_DDR BIT(5) +#define OP_ADDR_BUSW(x) ((x) << 3) +#define OP_CMD_DDR BIT(2) +#define OP_CMD_BUSW(x) (x) +#define OP_BUSW_1 0 +#define OP_BUSW_2 1 +#define OP_BUSW_4 2 +#define OP_BUSW_8 3 + +#define OCTA_CRC 0x38 +#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) +#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16))) +#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) + +#define ONFI_DIN_CNT(s) (0x3c + (s)) + +#define LRD_CTRL 0x48 +#define RWW_CTRL 0x74 +#define LWR_CTRL 0x84 +#define LMODE_EN BIT(31) +#define LMODE_SLV_ACT(x) ((x) << 21) +#define LMODE_CMD1(x) ((x) << 8) +#define LMODE_CMD0(x) (x) + +#define LRD_ADDR 0x4c +#define LWR_ADDR 0x88 +#define LRD_RANGE 0x50 +#define LWR_RANGE 0x8c + +#define AXI_SLV_ADDR 0x54 + +#define DMAC_RD_CFG 0x58 +#define DMAC_WR_CFG 0x94 +#define DMAC_CFG_PERIPH_EN BIT(31) +#define DMAC_CFG_ALLFLUSH_EN BIT(30) +#define DMAC_CFG_LASTFLUSH_EN BIT(29) +#define DMAC_CFG_QE(x) (((x) + 1) << 16) +#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12) +#define DMAC_CFG_BURST_SZ(x) ((x) << 8) +#define DMAC_CFG_DIR_READ BIT(1) +#define DMAC_CFG_START BIT(0) + +#define DMAC_RD_CNT 0x5c +#define DMAC_WR_CNT 0x98 + +#define SDMA_ADDR 0x60 + +#define DMAM_CFG 0x64 +#define DMAM_CFG_START BIT(31) +#define DMAM_CFG_CONT BIT(30) +#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2) +#define DMAM_CFG_DIR_READ BIT(1) +#define DMAM_CFG_EN BIT(0) + +#define DMAM_CNT 0x68 + +#define LNR_TIMER_TH 0x6c + +#define RDM_CFG0 0x78 +#define RDM_CFG0_POLY(x) (x) + +#define RDM_CFG1 0x7c +#define RDM_CFG1_RDM_EN BIT(31) +#define RDM_CFG1_SEED(x) (x) + +#define LWR_SUSP_CTRL 0x90 +#define LWR_SUSP_CTRL_EN BIT(31) + +#define DMAS_CTRL 0x9c +#define DMAS_CTRL_EN BIT(31) +#define DMAS_CTRL_DIR_READ BIT(30) + +#define DATA_STROB 0xa0 +#define DATA_STROB_EDO_EN BIT(2) +#define DATA_STROB_INV_POL BIT(1) +#define DATA_STROB_DELAY_2CYC BIT(0) + +#define IDLY_CODE(x) (0xa4 + ((x) * 4)) +#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8)) + +#define GPIO 0xc4 +#define GPIO_PT(x) BIT(3 + ((x) * 16)) +#define GPIO_RESET(x) BIT(2 + ((x) * 16)) +#define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) +#define GPIO_WPB(x) BIT((x) * 16) + +#define HC_VER 0xd0 + +#define HW_TEST(x) (0xe0 + ((x) * 4)) + +struct mxic_spi_priv { + struct clk *send_clk; + struct clk *send_dly_clk; + void __iomem *regs; + u32 cur_speed_hz; +}; + +static int mxic_spi_clk_enable(struct mxic_spi_priv *priv) +{ + int ret; + + ret = clk_prepare_enable(priv->send_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->send_dly_clk); + if (ret) + goto err_send_dly_clk; + + return ret; + +err_send_dly_clk: + clk_disable_unprepare(priv->send_clk); + + return ret; +} + +static void mxic_spi_clk_disable(struct mxic_spi_priv *priv) +{ + clk_disable_unprepare(priv->send_clk); + clk_disable_unprepare(priv->send_dly_clk); +} + +static void mxic_spi_set_input_delay_dqs(struct mxic_spi_priv *priv, + u8 idly_code) +{ + writel(IDLY_CODE_VAL(0, idly_code) | + IDLY_CODE_VAL(1, idly_code) | + IDLY_CODE_VAL(2, idly_code) | + IDLY_CODE_VAL(3, idly_code), + priv->regs + IDLY_CODE(0)); + writel(IDLY_CODE_VAL(4, idly_code) | + IDLY_CODE_VAL(5, idly_code) | + IDLY_CODE_VAL(6, idly_code) | + IDLY_CODE_VAL(7, idly_code), + priv->regs + IDLY_CODE(1)); +} + +static int mxic_spi_clk_setup(struct mxic_spi_priv *priv, uint freq) +{ + int ret; + + ret = clk_set_rate(priv->send_clk, freq); + if (ret) + return ret; + + ret = clk_set_rate(priv->send_dly_clk, freq); + if (ret) + return ret; + + /* + * A constant delay range from 0x0 ~ 0x1F for input delay, + * the unit is 78 ps, the max input delay is 2.418 ns. + */ + mxic_spi_set_input_delay_dqs(priv, 0xf); + + return 0; +} + +static int mxic_spi_set_speed(struct udevice *bus, uint freq) +{ + struct mxic_spi_priv *priv = dev_get_priv(bus); + int ret; + + if (priv->cur_speed_hz == freq) + return 0; + + mxic_spi_clk_disable(priv); + ret = mxic_spi_clk_setup(priv, freq); + if (ret) + return ret; + + ret = mxic_spi_clk_enable(priv); + if (ret) + return ret; + + priv->cur_speed_hz = freq; + + return 0; +} + +static int mxic_spi_set_mode(struct udevice *bus, uint mode) +{ + struct mxic_spi_priv *priv = dev_get_priv(bus); + u32 hc_config = 0; + + if (mode & SPI_CPHA) + hc_config |= HC_CFG_CLK_PH_EN; + if (mode & SPI_CPOL) + hc_config |= HC_CFG_CLK_POL_INV; + + writel(hc_config, priv->regs + HC_CFG); + + return 0; +} + +static void mxic_spi_hw_init(struct mxic_spi_priv *priv) +{ + writel(0, priv->regs + DATA_STROB); + writel(INT_STS_ALL, priv->regs + INT_STS_EN); + writel(0, priv->regs + HC_EN); + writel(0, priv->regs + LRD_CFG); + writel(0, priv->regs + LRD_CTRL); + writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1), + priv->regs + HC_CFG); +} + +static int mxic_spi_data_xfer(struct mxic_spi_priv *priv, const void *txbuf, + void *rxbuf, unsigned int len) +{ + unsigned int pos = 0; + + while (pos < len) { + unsigned int nbytes = len - pos; + u32 data = 0xffffffff; + u32 sts; + int ret; + + if (nbytes > 4) + nbytes = 4; + + if (txbuf) + memcpy(&data, txbuf + pos, nbytes); + + ret = readl_poll_timeout(priv->regs + INT_STS, sts, + sts & INT_TX_EMPTY, 1000000); + if (ret) + return ret; + + writel(data, priv->regs + TXD(nbytes % 4)); + + if (rxbuf) { + ret = readl_poll_timeout(priv->regs + INT_STS, sts, + sts & INT_TX_EMPTY, + 1000000); + if (ret) + return ret; + + ret = readl_poll_timeout(priv->regs + INT_STS, sts, + sts & INT_RX_NOT_EMPTY, + 1000000); + if (ret) + return ret; + + data = readl(priv->regs + RXD); + data >>= (8 * (4 - nbytes)); + memcpy(rxbuf + pos, &data, nbytes); + WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY); + } else { + readl(priv->regs + RXD); + } + WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY); + + pos += nbytes; + } + + return 0; +} + +static bool mxic_spi_mem_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) + return false; + + if (op->addr.nbytes > 7) + return false; + + return spi_mem_default_supports_op(slave, op); +} + +static int mxic_spi_mem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); + struct udevice *bus = slave->dev->parent; + struct mxic_spi_priv *priv = dev_get_priv(bus); + int nio = 1, i, ret; + u32 ss_ctrl; + u8 addr[8], dummy_bytes = 0; + + if (slave->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL)) + nio = 8; + else if (slave->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) + nio = 4; + else if (slave->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) + nio = 2; + + writel(HC_CFG_NIO(nio) | + HC_CFG_TYPE(slave_plat->cs, HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(slave_plat->cs) | HC_CFG_IDLE_SIO_LVL(1) | + HC_CFG_MAN_CS_EN, + priv->regs + HC_CFG); + writel(HC_EN_BIT, priv->regs + HC_EN); + + ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1); + + if (op->addr.nbytes) + ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) | + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1); + + /* + * Since the SPI MXIC dummy buswidth is aligned with the data buswidth, + * the dummy byte needs to be recalculated to send out the correct + * dummy cycle. + */ + if (op->dummy.nbytes) { + dummy_bytes = op->dummy.nbytes / + op->addr.buswidth * + op->data.buswidth; + ss_ctrl |= OP_DUMMY_CYC(dummy_bytes); + } + + if (op->data.nbytes) { + ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1); + if (op->data.dir == SPI_MEM_DATA_IN) + ss_ctrl |= OP_READ; + } + + writel(ss_ctrl, priv->regs + SS_CTRL(slave_plat->cs)); + + writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, + priv->regs + HC_CFG); + + ret = mxic_spi_data_xfer(priv, &op->cmd.opcode, NULL, 1); + if (ret) + goto out; + + for (i = 0; i < op->addr.nbytes; i++) + addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); + + ret = mxic_spi_data_xfer(priv, addr, NULL, op->addr.nbytes); + if (ret) + goto out; + + ret = mxic_spi_data_xfer(priv, NULL, NULL, dummy_bytes); + if (ret) + goto out; + + ret = mxic_spi_data_xfer(priv, + op->data.dir == SPI_MEM_DATA_OUT ? + op->data.buf.out : NULL, + op->data.dir == SPI_MEM_DATA_IN ? + op->data.buf.in : NULL, + op->data.nbytes); + +out: + writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, + priv->regs + HC_CFG); + writel(0, priv->regs + HC_EN); + + return ret; +} + +static const struct spi_controller_mem_ops mxic_spi_mem_ops = { + .supports_op = mxic_spi_mem_supports_op, + .exec_op = mxic_spi_mem_exec_op, +}; + +static int mxic_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct mxic_spi_priv *priv = dev_get_priv(bus); + + writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_EN, + priv->regs + HC_CFG); + writel(HC_EN_BIT, priv->regs + HC_EN); + writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, + priv->regs + HC_CFG); + + return 0; +} + +static int mxic_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct mxic_spi_priv *priv = dev_get_priv(bus); + + writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, + priv->regs + HC_CFG); + writel(0, priv->regs + HC_EN); + + return 0; +} + +static int mxic_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct mxic_spi_priv *priv = dev_get_priv(bus); + struct spi_slave *slave = dev_get_parent_priv(dev); + unsigned int busw = OP_BUSW_1; + unsigned int len = bitlen / 8; + int ret; + + if (dout && din) { + if (((slave->mode & SPI_TX_QUAD) && + !(slave->mode & SPI_RX_QUAD)) || + ((slave->mode & SPI_TX_DUAL) && + !(slave->mode & SPI_RX_DUAL))) + return -ENOTSUPP; + } + + if (din) { + if (slave->mode & SPI_TX_QUAD) + busw = OP_BUSW_4; + else if (slave->mode & SPI_TX_DUAL) + busw = OP_BUSW_2; + } else if (dout) { + if (slave->mode & SPI_RX_QUAD) + busw = OP_BUSW_4; + else if (slave->mode & SPI_RX_DUAL) + busw = OP_BUSW_2; + } + + writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) | + OP_DATA_BUSW(busw) | (din ? OP_READ : 0), + priv->regs + SS_CTRL(0)); + + ret = mxic_spi_data_xfer(priv, dout, din, len); + if (ret) + return ret; + + return 0; +} + +static int mxic_spi_probe(struct udevice *bus) +{ + struct mxic_spi_priv *priv = dev_get_priv(bus); + + priv->regs = (void *)dev_read_addr(bus); + + priv->send_clk = devm_clk_get(bus, "send_clk"); + if (IS_ERR(priv->send_clk)) + return PTR_ERR(priv->send_clk); + + priv->send_dly_clk = devm_clk_get(bus, "send_dly_clk"); + if (IS_ERR(priv->send_dly_clk)) + return PTR_ERR(priv->send_dly_clk); + + mxic_spi_hw_init(priv); + + return 0; +} + +static const struct dm_spi_ops mxic_spi_ops = { + .claim_bus = mxic_spi_claim_bus, + .release_bus = mxic_spi_release_bus, + .xfer = mxic_spi_xfer, + .set_speed = mxic_spi_set_speed, + .set_mode = mxic_spi_set_mode, + .mem_ops = &mxic_spi_mem_ops, +}; + +static const struct udevice_id mxic_spi_ids[] = { + { .compatible = "mxicy,mx25f0a-spi", }, + { } +}; + +U_BOOT_DRIVER(mxic_spi) = { + .name = "mxic_spi", + .id = UCLASS_SPI, + .of_match = mxic_spi_ids, + .ops = &mxic_spi_ops, + .priv_auto = sizeof(struct mxic_spi_priv), + .probe = mxic_spi_probe, +}; From a1eb40b70b40d208a72765c0f56cffed4e22ff30 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:03 +0530 Subject: [PATCH 205/250] spi: spi-mem: allow specifying whether an op is DTR or not Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/spi/spi-mem.c | 3 +++ include/spi-mem.h | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index c095ae9505a..427f7c13c56 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -164,6 +164,9 @@ bool spi_mem_default_supports_op(struct spi_slave *slave, op->data.dir == SPI_MEM_DATA_OUT)) return false; + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) + return false; + return true; } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); diff --git a/include/spi-mem.h b/include/spi-mem.h index e354c388979..8bd44596747 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -71,6 +71,7 @@ enum spi_mem_data_dir { * struct spi_mem_op - describes a SPI memory operation * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode + * @cmd.dtr: whether the command opcode should be sent in DTR mode or not * @addr.nbytes: number of address bytes to send. Can be zero if the operation * does not need to send an address * @addr.buswidth: number of IO lines used to transmit the address cycles @@ -78,10 +79,13 @@ enum spi_mem_data_dir { * Note that only @addr.nbytes are taken into account in this * address value, so users should make sure the value fits in the * assigned number of bytes. + * @addr.dtr: whether the address should be sent in DTR mode or not * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can * be zero if the operation does not require dummy bytes * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes + * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data + * @data.dtr: whether the data should be sent in DTR mode or not * @data.dir: direction of the transfer * @data.buf.in: input buffer * @data.buf.out: output buffer @@ -90,21 +94,25 @@ struct spi_mem_op { struct { u8 buswidth; u8 opcode; + u8 dtr : 1; } cmd; struct { u8 nbytes; u8 buswidth; + u8 dtr : 1; u64 val; } addr; struct { u8 nbytes; u8 buswidth; + u8 dtr : 1; } dummy; struct { u8 buswidth; + u8 dtr : 1; enum spi_mem_data_dir dir; unsigned int nbytes; /* buf.{in,out} must be DMA-able. */ From d15de623013cbb3334e9466fafb0929e7f6a31c7 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:04 +0530 Subject: [PATCH 206/250] spi: spi-mem: allow specifying a command's extension In xSPI mode, flashes expect 2-byte opcodes. The second byte is called the "command extension". There can be 3 types of extensions in xSPI: repeat, invert, and hex. When the extension type is "repeat", the same opcode is sent twice. When it is "invert", the second byte is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything. So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled. All usages of sizeof(op->cmd.opcode) also need to be changed to be op->cmd.nbytes because that is the actual indicator of opcode size. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/spi/mtk_snfi_spi.c | 3 +-- drivers/spi/spi-mem-nodm.c | 4 ++-- drivers/spi/spi-mem.c | 13 +++++++------ include/spi-mem.h | 6 +++++- 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c index b6ab5fa3ada..65d0ce0981b 100644 --- a/drivers/spi/mtk_snfi_spi.c +++ b/drivers/spi/mtk_snfi_spi.c @@ -64,8 +64,7 @@ static int mtk_snfi_adjust_op_size(struct spi_slave *slave, * or the output+input data must not exceed the GPRAM size. */ - nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes + - op->dummy.nbytes; + nbytes = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE) return 0; diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c index 765f05fe542..db54101383c 100644 --- a/drivers/spi/spi-mem-nodm.c +++ b/drivers/spi/spi-mem-nodm.c @@ -27,7 +27,7 @@ int spi_mem_exec_op(struct spi_slave *slave, tx_buf = op->data.buf.out; } - op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; op_buf = calloc(1, op_len); ret = spi_claim_bus(slave); @@ -89,7 +89,7 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, { unsigned int len; - len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; if (slave->max_write_size && len > slave->max_write_size) return -EINVAL; diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 427f7c13c56..541cd0e5a77 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -167,6 +167,9 @@ bool spi_mem_default_supports_op(struct spi_slave *slave, if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) return false; + if (op->cmd.nbytes != 1) + return false; + return true; } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); @@ -273,8 +276,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) } #ifndef __UBOOT__ - tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes + - op->dummy.nbytes; + tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; /* * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so @@ -289,7 +291,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) tmpbuf[0] = op->cmd.opcode; xfers[xferpos].tx_buf = tmpbuf; - xfers[xferpos].len = sizeof(op->cmd.opcode); + xfers[xferpos].len = op->cmd.nbytes; xfers[xferpos].tx_nbits = op->cmd.buswidth; spi_message_add_tail(&xfers[xferpos], &msg); xferpos++; @@ -353,7 +355,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) tx_buf = op->data.buf.out; } - op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; /* * Avoid using malloc() here so that we can use this code in SPL where @@ -442,8 +444,7 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) if (!ops->mem_ops || !ops->mem_ops->exec_op) { unsigned int len; - len = sizeof(op->cmd.opcode) + op->addr.nbytes + - op->dummy.nbytes; + len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; if (slave->max_write_size && len > slave->max_write_size) return -EINVAL; diff --git a/include/spi-mem.h b/include/spi-mem.h index 8bd44596747..fe249f77ba1 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -17,6 +17,7 @@ struct udevice; { \ .buswidth = __buswidth, \ .opcode = __opcode, \ + .nbytes = 1, \ } #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ @@ -69,6 +70,8 @@ enum spi_mem_data_dir { /** * struct spi_mem_op - describes a SPI memory operation + * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is + * sent MSB-first. * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode * @cmd.dtr: whether the command opcode should be sent in DTR mode or not @@ -92,9 +95,10 @@ enum spi_mem_data_dir { */ struct spi_mem_op { struct { + u8 nbytes; u8 buswidth; - u8 opcode; u8 dtr : 1; + u16 opcode; } cmd; struct { From 2299076e34f8cd5682b1fe20bcc0395f2466bcc6 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:05 +0530 Subject: [PATCH 207/250] spi: spi-mem: export spi_mem_default_supports_op() Controllers can use this function to perform basic sanity checking on the spi-mem op. Reviewed-by: Sean Anderson Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- include/spi-mem.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/spi-mem.h b/include/spi-mem.h index fe249f77ba1..de3c11c8e24 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -250,6 +250,9 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); +bool spi_mem_default_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op); + int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op); bool spi_mem_default_supports_op(struct spi_slave *mem, From 5752d6ae8daacbd2678cbf9a96627dd9c83f215c Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:06 +0530 Subject: [PATCH 208/250] spi: spi-mem: add spi_mem_dtr_supports_op() spi_mem_default_supports_op() rejects DTR ops by default to ensure that the controller drivers that haven't been updated with DTR support continue to reject them. It also makes sure that controllers that don't support DTR mode at all (which is most of them at the moment) also reject them. This means that controller drivers that want to support DTR mode can't use spi_mem_default_supports_op(). Driver authors have to roll their own supports_op() function and mimic the buswidth checks. Or even worse, driver authors might skip it completely or get it wrong. Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR ops and performs the buswidth requirement check. Move the logic for checking buswidth in spi_mem_default_supports_op() to a separate function so the logic is not repeated twice. Signed-off-by: Pratyush Yadav Acked-by: Jagan Teki --- drivers/spi/spi-mem.c | 32 +++++++++++++++++++++++++++++--- include/spi-mem.h | 2 ++ 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 541cd0e5a77..9c1ede1b61c 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -145,8 +145,8 @@ static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx) return -ENOTSUPP; } -bool spi_mem_default_supports_op(struct spi_slave *slave, - const struct spi_mem_op *op) +static bool spi_mem_check_buswidth(struct spi_slave *slave, + const struct spi_mem_op *op) { if (spi_check_buswidth_req(slave, op->cmd.buswidth, true)) return false; @@ -164,13 +164,39 @@ bool spi_mem_default_supports_op(struct spi_slave *slave, op->data.dir == SPI_MEM_DATA_OUT)) return false; + return true; +} + +bool spi_mem_dtr_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2) + return false; + + if (op->addr.nbytes && op->addr.buswidth == 8 && op->addr.nbytes % 2) + return false; + + if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2) + return false; + + if (op->data.dir != SPI_MEM_NO_DATA && + op->dummy.buswidth == 8 && op->data.nbytes % 2) + return false; + + return spi_mem_check_buswidth(slave, op); +} +EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); + +bool spi_mem_default_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) return false; if (op->cmd.nbytes != 1) return false; - return true; + return spi_mem_check_buswidth(slave, op); } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); diff --git a/include/spi-mem.h b/include/spi-mem.h index de3c11c8e24..32ffdc2e0f9 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -249,6 +249,8 @@ spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); +bool spi_mem_dtr_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op); bool spi_mem_default_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); From bd8c8dcd4d6fb1cf726d5a267be5ec33c93f1471 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:07 +0530 Subject: [PATCH 209/250] spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 26 +++++++++++++++++++++----- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 67980431ba0..de7628de276 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -141,12 +141,20 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) cadence_qspi_apb_controller_disable(priv->regbase); /* - * Calibration required for different current SCLK speed, requested - * SCLK speed or chip select + * If the device tree already provides a read delay value, use that + * instead of calibrating. */ - if (priv->previous_hz != hz || - priv->qspi_calibrated_hz != hz || - priv->qspi_calibrated_cs != spi_chip_select(bus)) { + if (plat->read_delay >= 0) { + cadence_spi_write_speed(bus, hz); + cadence_qspi_apb_readdata_capture(priv->regbase, 1, + plat->read_delay); + } else if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || + priv->qspi_calibrated_cs != spi_chip_select(bus)) { + /* + * Calibration required for different current SCLK speed, + * requested SCLK speed or chip select + */ err = spi_calibration(bus, hz); if (err) return err; @@ -320,6 +328,14 @@ static int cadence_spi_of_to_plat(struct udevice *bus) 255); plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); + /* + * Read delay should be an unsigned value but we use a signed integer + * so that negative values can indicate that the device tree did not + * specify any signed values and we need to perform the calibration + * sequence to find it out. + */ + plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay", + -1); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 64c5867609c..b06d7750e2d 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -26,6 +26,7 @@ struct cadence_spi_plat { u32 trigger_address; fdt_addr_t ahbsize; bool use_dac_mode; + int read_delay; /* Flash parameters */ u32 page_size; From a6903aa7ea98872ff66424051f85cdf0178c86f8 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:08 +0530 Subject: [PATCH 210/250] spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav Acked-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 4 ++++ drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 6 ++++++ 3 files changed, 11 insertions(+) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index de7628de276..a961193cdc3 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -20,6 +20,8 @@ #include #include "cadence_qspi.h" +#define NSEC_PER_SEC 1000000000L + #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 #define CQSPI_READ 2 @@ -208,6 +210,8 @@ static int cadence_spi_probe(struct udevice *bus) priv->qspi_is_init = 1; } + plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index b06d7750e2d..5c745541a6c 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -27,6 +27,7 @@ struct cadence_spi_plat { fdt_addr_t ahbsize; bool use_dac_mode; int read_delay; + u32 wr_delay; /* Flash parameters */ u32 page_size; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b051f462ed2..92e57730bd3 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -730,6 +730,12 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTWR_START, plat->regbase + CQSPI_REG_INDIRECTWR); + /* + * Some delay is required for the above bit to be internally + * synchronized by the QSPI module. + */ + ndelay(plat->wr_delay); + while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); From 38b0852b0eab1c5ce18ed8125572ffb0bb6973fd Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:09 +0530 Subject: [PATCH 211/250] spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav Acked-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 39 ++++- drivers/spi/cadence_qspi.h | 14 +- drivers/spi/cadence_qspi_apb.c | 288 ++++++++++++++++++++++++++++++--- 3 files changed, 314 insertions(+), 27 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index a961193cdc3..d1b3808c4db 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -43,20 +43,22 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) return 0; } -static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode) +static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len, + u8 *idcode) { struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(len, idcode, 1)); - return cadence_qspi_apb_command_read(reg_base, &op); + return cadence_qspi_apb_command_read(plat, &op); } /* Calibration sequence to determine the read data capture delay register */ static int spi_calibration(struct udevice *bus, uint hz) { struct cadence_spi_priv *priv = dev_get_priv(bus); + struct cadence_spi_plat *plat = dev_get_plat(bus); void *base = priv->regbase; unsigned int idcode = 0, temp = 0; int err = 0, i, range_lo = -1, range_hi = -1; @@ -71,7 +73,7 @@ static int spi_calibration(struct udevice *bus, uint hz) cadence_qspi_apb_controller_enable(base); /* read the ID which will be our golden value */ - err = cadence_spi_read_id(base, 3, (u8 *)&idcode); + err = cadence_spi_read_id(plat, 3, (u8 *)&idcode); if (err) { puts("SF: Calibration failed (read)\n"); return err; @@ -90,7 +92,7 @@ static int spi_calibration(struct udevice *bus, uint hz) cadence_qspi_apb_controller_enable(base); /* issue a RDID to get the ID value */ - err = cadence_spi_read_id(base, 3, (u8 *)&temp); + err = cadence_spi_read_id(plat, 3, (u8 *)&temp); if (err) { puts("SF: Calibration failed (read)\n"); return err; @@ -271,10 +273,14 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, switch (mode) { case CQSPI_STIG_READ: - err = cadence_qspi_apb_command_read(base, op); + err = cadence_qspi_apb_command_read_setup(plat, op); + if (!err) + err = cadence_qspi_apb_command_read(plat, op); break; case CQSPI_STIG_WRITE: - err = cadence_qspi_apb_command_write(base, op); + err = cadence_qspi_apb_command_write_setup(plat, op); + if (!err) + err = cadence_qspi_apb_command_write(plat, op); break; case CQSPI_READ: err = cadence_qspi_apb_read_setup(plat, op); @@ -294,6 +300,26 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, return err; } +static bool cadence_spi_mem_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + bool all_true, all_false; + + all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && + op->data.dtr; + all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && + !op->data.dtr; + + /* Mixed DTR modes not supported. */ + if (!(all_true || all_false)) + return false; + + if (all_true) + return spi_mem_dtr_supports_op(slave, op); + else + return spi_mem_default_supports_op(slave, op); +} + static int cadence_spi_of_to_plat(struct udevice *bus) { struct cadence_spi_plat *plat = dev_get_plat(bus); @@ -350,6 +376,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) static const struct spi_controller_mem_ops cadence_spi_mem_ops = { .exec_op = cadence_spi_mem_exec_op, + .supports_op = cadence_spi_mem_supports_op, }; static const struct dm_spi_ops cadence_spi_ops = { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 5c745541a6c..49b401168fc 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -36,6 +36,12 @@ struct cadence_spi_plat { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + + /* Transaction protocol parameters. */ + u8 inst_width; + u8 addr_width; + u8 data_width; + bool dtr; }; struct cadence_spi_priv { @@ -59,9 +65,13 @@ void cadence_qspi_apb_controller_enable(void *reg_base_addr); void cadence_qspi_apb_controller_disable(void *reg_base_addr); void cadence_qspi_apb_dac_mode_enable(void *reg_base); -int cadence_qspi_apb_command_read(void *reg_base_addr, +int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat, const struct spi_mem_op *op); -int cadence_qspi_apb_command_write(void *reg_base_addr, +int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat, const struct spi_mem_op *op); int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat, diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 92e57730bd3..c36a652211a 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -51,7 +51,7 @@ #define CQSPI_STIG_DATA_LEN_MAX 8 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 -#define CQSPI_DUMMY_BYTES_MAX 4 +#define CQSPI_DUMMY_CLKS_MAX 31 /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) @@ -65,6 +65,8 @@ #define CQSPI_REG_CONFIG_XIP_IMM BIT(18) #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) +#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) #define CQSPI_REG_CONFIG_IDLE_LSB 31 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF #define CQSPI_REG_CONFIG_BAUD_MASK 0xF @@ -83,6 +85,7 @@ #define CQSPI_REG_WR_INSTR 0x08 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 #define CQSPI_REG_DELAY 0x0C @@ -120,6 +123,9 @@ #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF +#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 +#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) + #define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 @@ -166,6 +172,11 @@ #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC +#define CQSPI_REG_OP_EXT_LOWER 0xE0 +#define CQSPI_REG_OP_EXT_READ_LSB 24 +#define CQSPI_REG_OP_EXT_WRITE_LSB 16 +#define CQSPI_REG_OP_EXT_STIG_LSB 0 + #define CQSPI_REG_IS_IDLE(base) \ ((readl(base + CQSPI_REG_CONFIG) >> \ CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) @@ -203,6 +214,75 @@ void cadence_qspi_apb_dac_mode_enable(void *reg_base) writel(reg, reg_base + CQSPI_REG_CONFIG); } +static unsigned int cadence_qspi_calc_dummy(const struct spi_mem_op *op, + bool dtr) +{ + unsigned int dummy_clk; + + dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); + if (dtr) + dummy_clk /= 2; + + return dummy_clk; +} + +static u32 cadence_qspi_calc_rdreg(struct cadence_spi_plat *plat) +{ + u32 rdreg = 0; + + rdreg |= plat->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; + rdreg |= plat->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; + rdreg |= plat->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; + + return rdreg; +} + +static int cadence_qspi_buswidth_to_inst_type(u8 buswidth) +{ + switch (buswidth) { + case 0: + case 1: + return CQSPI_INST_TYPE_SINGLE; + + case 2: + return CQSPI_INST_TYPE_DUAL; + + case 4: + return CQSPI_INST_TYPE_QUAD; + + case 8: + return CQSPI_INST_TYPE_OCTAL; + + default: + return -ENOTSUPP; + } +} + +static int cadence_qspi_set_protocol(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + int ret; + + plat->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr; + + ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth); + if (ret < 0) + return ret; + plat->inst_width = ret; + + ret = cadence_qspi_buswidth_to_inst_type(op->addr.buswidth); + if (ret < 0) + return ret; + plat->addr_width = ret; + + ret = cadence_qspi_buswidth_to_inst_type(op->data.buswidth); + if (ret < 0) + return ret; + plat->data_width = ret; + + return 0; +} + /* Return 1 if idle, otherwise return 0 (busy). */ static unsigned int cadence_qspi_wait_idle(void *reg_base) { @@ -434,21 +514,109 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, return 0; } -/* For command RDID, RDSR. */ -int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op) +static int cadence_qspi_setup_opcode_ext(struct cadence_spi_plat *plat, + const struct spi_mem_op *op, + unsigned int shift) { + unsigned int reg; + u8 ext; + + if (op->cmd.nbytes != 2) + return -EINVAL; + + /* Opcode extension is the LSB. */ + ext = op->cmd.opcode & 0xff; + + reg = readl(plat->regbase + CQSPI_REG_OP_EXT_LOWER); + reg &= ~(0xff << shift); + reg |= ext << shift; + writel(reg, plat->regbase + CQSPI_REG_OP_EXT_LOWER); + + return 0; +} + +static int cadence_qspi_enable_dtr(struct cadence_spi_plat *plat, + const struct spi_mem_op *op, + unsigned int shift, + bool enable) +{ + unsigned int reg; + int ret; + + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + + if (enable) { + reg |= CQSPI_REG_CONFIG_DTR_PROTO; + reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; + + /* Set up command opcode extension. */ + ret = cadence_qspi_setup_opcode_ext(plat, op, shift); + if (ret) + return ret; + } else { + reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; + reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; + } + + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + return 0; +} + +int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + int ret; + unsigned int reg; + + ret = cadence_qspi_set_protocol(plat, op); + if (ret) + return ret; + + ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_STIG_LSB, + plat->dtr); + if (ret) + return ret; + + reg = cadence_qspi_calc_rdreg(plat); + writel(reg, plat->regbase + CQSPI_REG_RD_INSTR); + + return 0; +} + +/* For command RDID, RDSR. */ +int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + void *reg_base = plat->regbase; unsigned int reg; unsigned int read_len; int status; unsigned int rxlen = op->data.nbytes; void *rxbuf = op->data.buf.in; + unsigned int dummy_clk; + u8 opcode; if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { printf("QSPI: Invalid input arguments rxlen %u\n", rxlen); return -EINVAL; } - reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + if (plat->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; + + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + /* Set up dummy cycles. */ + dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr); + if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) + return -ENOTSUPP; + + if (dummy_clk) + reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) + << CQSPI_REG_CMDCTRL_DUMMY_LSB; reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); @@ -475,15 +643,39 @@ int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op) return 0; } +int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + int ret; + unsigned int reg; + + ret = cadence_qspi_set_protocol(plat, op); + if (ret) + return ret; + + ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_STIG_LSB, + plat->dtr); + if (ret) + return ret; + + reg = cadence_qspi_calc_rdreg(plat); + writel(reg, plat->regbase + CQSPI_REG_RD_INSTR); + + return 0; +} + /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ -int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op) +int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) { unsigned int reg = 0; unsigned int wr_data; unsigned int wr_len; unsigned int txlen = op->data.nbytes; const void *txbuf = op->data.buf.out; + void *reg_base = plat->regbase; u32 addr; + u8 opcode; /* Reorder address to SPI bus order if only transferring address */ if (!txlen) { @@ -499,7 +691,12 @@ int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op) return -EINVAL; } - reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + if (plat->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; + + reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; if (txlen) { /* writing data = yes */ @@ -533,29 +730,39 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat, unsigned int rd_reg; unsigned int dummy_clk; unsigned int dummy_bytes = op->dummy.nbytes; + int ret; + u8 opcode; + + ret = cadence_qspi_set_protocol(plat, op); + if (ret) + return ret; + + ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_READ_LSB, + plat->dtr); + if (ret) + return ret; /* Setup the indirect trigger address */ writel(plat->trigger_address, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ - rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; + if (plat->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; - if (op->data.buswidth == 8) - /* Instruction and address at DQ0, data at DQ0-7. */ - rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; - else if (op->data.buswidth == 4) - /* Instruction and address at DQ0, data at DQ0-3. */ - rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; + rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; + rd_reg |= cadence_qspi_calc_rdreg(plat); writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); if (dummy_bytes) { - if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) - dummy_bytes = CQSPI_DUMMY_BYTES_MAX; - /* Convert to clock cycles. */ - dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; + dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr); + + if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) + return -ENOTSUPP; if (dummy_clk) rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) @@ -682,17 +889,52 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat, const struct spi_mem_op *op) { unsigned int reg; + int ret; + u8 opcode; + + ret = cadence_qspi_set_protocol(plat, op); + if (ret) + return ret; + + ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_WRITE_LSB, + plat->dtr); + if (ret) + return ret; /* Setup the indirect trigger address */ writel(plat->trigger_address, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ - reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; + if (plat->dtr) + opcode = op->cmd.opcode >> 8; + else + opcode = op->cmd.opcode; + + reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; + reg |= plat->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + reg |= plat->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); + reg = cadence_qspi_calc_rdreg(plat); + writel(reg, plat->regbase + CQSPI_REG_RD_INSTR); + writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); + if (plat->dtr) { + /* + * Some flashes like the cypress Semper flash expect a 4-byte + * dummy address with the Read SR command in DTR mode, but this + * controller does not support sending address with the Read SR + * command. So, disable write completion polling on the + * controller's side. spi-nor will take care of polling the + * status register. + */ + reg = readl(plat->regbase + CQSPI_REG_WR_COMPLETION_CTRL); + reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; + writel(reg, plat->regbase + CQSPI_REG_WR_COMPLETION_CTRL); + } + reg = readl(plat->regbase + CQSPI_REG_SIZE); reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |= (op->addr.nbytes - 1); @@ -787,7 +1029,15 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; - if (plat->use_dac_mode && (to + len < plat->ahbsize)) { + /* + * Some flashes like the Cypress Semper flash expect a dummy 4-byte + * address (all 0s) with the read status register command in DTR mode. + * But this controller does not support sending dummy address bytes to + * the flash when it is polling the write completion register in DTR + * mode. So, we can not use direct mode when in DTR mode for writing + * data. + */ + if (!plat->dtr && plat->use_dac_mode && (to + len < plat->ahbsize)) { memcpy_toio(plat->ahbbase + to, buf, len); if (!cadence_qspi_wait_idle(plat->regbase)) return -EIO; From 1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:10 +0530 Subject: [PATCH 212/250] mtd: spi-nor-core: Fix address width on flash chips > 16MB If a flash chip has more than 16MB capacity but its BFPT reports BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3. The check in spi_nor_scan() doesn't catch it because addr_width did get set. This fixes that check. Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 6af9c675a4f..bfe7ea55c4b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2603,7 +2603,11 @@ int spi_nor_scan(struct spi_nor *nor) /* already configured from SFDP */ } else if (info->addr_width) { nor->addr_width = info->addr_width; - } else if (mtd->size > SZ_16M) { + } else { + nor->addr_width = 3; + } + + if (nor->addr_width == 3 && mtd->size > SZ_16M) { #ifndef CONFIG_SPI_FLASH_BAR /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; @@ -2617,8 +2621,6 @@ int spi_nor_scan(struct spi_nor *nor) if (ret < 0) return ret; #endif - } else { - nor->addr_width = 3; } if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { From 18b0de0f3be223cd2f468c03b5ea02e5f6bc6d82 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:11 +0530 Subject: [PATCH 213/250] mtd: spi-nor-core: Add a ->setup() hook nor->setup() can be used by flashes to configure settings in case they have any peculiarities that can't be easily expressed by the generic spi-nor framework. This includes things like different opcodes, dummy cycles, page size, uniform/non-uniform sector sizes, etc. Move related declarations to avoid forward declarations. Inspired by the Linux kernel's setup() hook. Signed-off-by: Pratyush Yadav Acked-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 84 +++------------ drivers/mtd/spi/spi-nor-tiny.c | 22 ---- include/linux/mtd/spi-nor.h | 192 ++++++++++++++++++++++----------- 3 files changed, 147 insertions(+), 151 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index bfe7ea55c4b..b782709f146 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1451,71 +1451,6 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ #endif /* CONFIG_SPI_FLASH_SPANSION */ -struct spi_nor_read_command { - u8 num_mode_clocks; - u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; -}; - -struct spi_nor_pp_command { - u8 opcode; - enum spi_nor_protocol proto; -}; - -enum spi_nor_read_command_index { - SNOR_CMD_READ, - SNOR_CMD_READ_FAST, - SNOR_CMD_READ_1_1_1_DTR, - - /* Dual SPI */ - SNOR_CMD_READ_1_1_2, - SNOR_CMD_READ_1_2_2, - SNOR_CMD_READ_2_2_2, - SNOR_CMD_READ_1_2_2_DTR, - - /* Quad SPI */ - SNOR_CMD_READ_1_1_4, - SNOR_CMD_READ_1_4_4, - SNOR_CMD_READ_4_4_4, - SNOR_CMD_READ_1_4_4_DTR, - - /* Octo SPI */ - SNOR_CMD_READ_1_1_8, - SNOR_CMD_READ_1_8_8, - SNOR_CMD_READ_8_8_8, - SNOR_CMD_READ_1_8_8_DTR, - - SNOR_CMD_READ_MAX -}; - -enum spi_nor_pp_command_index { - SNOR_CMD_PP, - - /* Quad SPI */ - SNOR_CMD_PP_1_1_4, - SNOR_CMD_PP_1_4_4, - SNOR_CMD_PP_4_4_4, - - /* Octo SPI */ - SNOR_CMD_PP_1_1_8, - SNOR_CMD_PP_1_8_8, - SNOR_CMD_PP_8_8_8, - - SNOR_CMD_PP_MAX -}; - -struct spi_nor_flash_parameter { - u64 size; - u32 page_size; - - struct spi_nor_hwcaps hwcaps; - struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; - struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; - - int (*quad_enable)(struct spi_nor *nor); -}; - static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, @@ -2377,9 +2312,10 @@ static int spi_nor_select_erase(struct spi_nor *nor, return 0; } -static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, - const struct spi_nor_flash_parameter *params, - const struct spi_nor_hwcaps *hwcaps) +static int spi_nor_default_setup(struct spi_nor *nor, + const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) { u32 ignored_mask, shared_mask; bool enable_quad_io; @@ -2438,6 +2374,16 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return 0; } +static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps) +{ + if (!nor->setup) + return 0; + + return nor->setup(nor, info, params, hwcaps); +} + static int spi_nor_init(struct spi_nor *nor) { int err; @@ -2504,6 +2450,8 @@ int spi_nor_scan(struct spi_nor *nor) nor->read_reg = spi_nor_read_reg; nor->write_reg = spi_nor_write_reg; + nor->setup = spi_nor_default_setup; + if (spi->mode & SPI_RX_OCTAL) { hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index b0aa97d3244..70061f1a617 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -555,28 +555,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) } #endif /* CONFIG_SPI_FLASH_SPANSION */ -struct spi_nor_read_command { - u8 num_mode_clocks; - u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; -}; - -enum spi_nor_read_command_index { - SNOR_CMD_READ, - SNOR_CMD_READ_FAST, - - /* Quad SPI */ - SNOR_CMD_READ_1_1_4, - - SNOR_CMD_READ_MAX -}; - -struct spi_nor_flash_parameter { - struct spi_nor_hwcaps hwcaps; - struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; -}; - static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c3e38e499e4..47a2eced696 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -249,6 +249,134 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET = BIT(6), }; +struct spi_nor; + +/** + * struct spi_nor_hwcaps - Structure for describing the hardware capabilies + * supported by the SPI controller (bus master). + * @mask: the bitmask listing all the supported hw capabilies + */ +struct spi_nor_hwcaps { + u32 mask; +}; + +/* + *(Fast) Read capabilities. + * MUST be ordered by priority: the higher bit position, the higher priority. + * As a matter of performances, it is relevant to use Octo SPI protocols first, + * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly + * (Slow) Read. + */ +#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) +#define SNOR_HWCAPS_READ BIT(0) +#define SNOR_HWCAPS_READ_FAST BIT(1) +#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) + +#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) +#define SNOR_HWCAPS_READ_1_1_2 BIT(3) +#define SNOR_HWCAPS_READ_1_2_2 BIT(4) +#define SNOR_HWCAPS_READ_2_2_2 BIT(5) +#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) + +#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) +#define SNOR_HWCAPS_READ_1_1_4 BIT(7) +#define SNOR_HWCAPS_READ_1_4_4 BIT(8) +#define SNOR_HWCAPS_READ_4_4_4 BIT(9) +#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) + +#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) +#define SNOR_HWCAPS_READ_1_1_8 BIT(11) +#define SNOR_HWCAPS_READ_1_8_8 BIT(12) +#define SNOR_HWCAPS_READ_8_8_8 BIT(13) +#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) + +/* + * Page Program capabilities. + * MUST be ordered by priority: the higher bit position, the higher priority. + * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the + * legacy SPI 1-1-1 protocol. + * Note that Dual Page Programs are not supported because there is no existing + * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory + * implements such commands. + */ +#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) +#define SNOR_HWCAPS_PP BIT(16) + +#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) +#define SNOR_HWCAPS_PP_1_1_4 BIT(17) +#define SNOR_HWCAPS_PP_1_4_4 BIT(18) +#define SNOR_HWCAPS_PP_4_4_4 BIT(19) + +#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) +#define SNOR_HWCAPS_PP_1_1_8 BIT(20) +#define SNOR_HWCAPS_PP_1_8_8 BIT(21) +#define SNOR_HWCAPS_PP_8_8_8 BIT(22) + +struct spi_nor_read_command { + u8 num_mode_clocks; + u8 num_wait_states; + u8 opcode; + enum spi_nor_protocol proto; +}; + +struct spi_nor_pp_command { + u8 opcode; + enum spi_nor_protocol proto; +}; + +enum spi_nor_read_command_index { + SNOR_CMD_READ, + SNOR_CMD_READ_FAST, + SNOR_CMD_READ_1_1_1_DTR, + + /* Dual SPI */ + SNOR_CMD_READ_1_1_2, + SNOR_CMD_READ_1_2_2, + SNOR_CMD_READ_2_2_2, + SNOR_CMD_READ_1_2_2_DTR, + + /* Quad SPI */ + SNOR_CMD_READ_1_1_4, + SNOR_CMD_READ_1_4_4, + SNOR_CMD_READ_4_4_4, + SNOR_CMD_READ_1_4_4_DTR, + + /* Octo SPI */ + SNOR_CMD_READ_1_1_8, + SNOR_CMD_READ_1_8_8, + SNOR_CMD_READ_8_8_8, + SNOR_CMD_READ_1_8_8_DTR, + + SNOR_CMD_READ_MAX +}; + +enum spi_nor_pp_command_index { + SNOR_CMD_PP, + + /* Quad SPI */ + SNOR_CMD_PP_1_1_4, + SNOR_CMD_PP_1_4_4, + SNOR_CMD_PP_4_4_4, + + /* Octo SPI */ + SNOR_CMD_PP_1_1_8, + SNOR_CMD_PP_1_8_8, + SNOR_CMD_PP_8_8_8, + + SNOR_CMD_PP_MAX +}; + +struct spi_nor_flash_parameter { + u64 size; + u32 page_size; + + struct spi_nor_hwcaps hwcaps; + struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; + struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; + + int (*quad_enable)(struct spi_nor *nor); +}; + /** * struct flash_info - Forward declaration of a structure used internally by * spi_nor_scan() @@ -330,6 +458,9 @@ struct spi_nor { u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; + int (*setup)(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params, + const struct spi_nor_hwcaps *hwcaps); int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); @@ -368,67 +499,6 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor) } #endif /* __UBOOT__ */ -/** - * struct spi_nor_hwcaps - Structure for describing the hardware capabilies - * supported by the SPI controller (bus master). - * @mask: the bitmask listing all the supported hw capabilies - */ -struct spi_nor_hwcaps { - u32 mask; -}; - -/* - *(Fast) Read capabilities. - * MUST be ordered by priority: the higher bit position, the higher priority. - * As a matter of performances, it is relevant to use Octo SPI protocols first, - * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly - * (Slow) Read. - */ -#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) -#define SNOR_HWCAPS_READ BIT(0) -#define SNOR_HWCAPS_READ_FAST BIT(1) -#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) - -#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) -#define SNOR_HWCAPS_READ_1_1_2 BIT(3) -#define SNOR_HWCAPS_READ_1_2_2 BIT(4) -#define SNOR_HWCAPS_READ_2_2_2 BIT(5) -#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) - -#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) -#define SNOR_HWCAPS_READ_1_1_4 BIT(7) -#define SNOR_HWCAPS_READ_1_4_4 BIT(8) -#define SNOR_HWCAPS_READ_4_4_4 BIT(9) -#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) - -#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) -#define SNOR_HWCAPS_READ_1_1_8 BIT(11) -#define SNOR_HWCAPS_READ_1_8_8 BIT(12) -#define SNOR_HWCAPS_READ_8_8_8 BIT(13) -#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) - -/* - * Page Program capabilities. - * MUST be ordered by priority: the higher bit position, the higher priority. - * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the - * legacy SPI 1-1-1 protocol. - * Note that Dual Page Programs are not supported because there is no existing - * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory - * implements such commands. - */ -#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) -#define SNOR_HWCAPS_PP BIT(16) - -#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) -#define SNOR_HWCAPS_PP_1_1_4 BIT(17) -#define SNOR_HWCAPS_PP_1_4_4 BIT(18) -#define SNOR_HWCAPS_PP_4_4_4 BIT(19) - -#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) -#define SNOR_HWCAPS_PP_1_1_8 BIT(20) -#define SNOR_HWCAPS_PP_1_8_8 BIT(21) -#define SNOR_HWCAPS_PP_8_8_8 BIT(22) - /** * spi_nor_scan() - scan the SPI NOR * @nor: the spi_nor structure From e2e31fa6800f701cd370b886035c72d6116a8cb1 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:12 +0530 Subject: [PATCH 214/250] mtd: spi-nor-core: Move SFDP related declarations to top These structures will be used in a later commit inside another structure definition. Also take the declarations out of the ifdef since they won't affect the final binary anyway and will be used in a later commit. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 224 ++++++++++++++++----------------- 1 file changed, 112 insertions(+), 112 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b782709f146..312628c080a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -40,6 +40,118 @@ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) +struct sfdp_parameter_header { + u8 id_lsb; + u8 minor; + u8 major; + u8 length; /* in double words */ + u8 parameter_table_pointer[3]; /* byte address */ + u8 id_msb; +}; + +#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) +#define SFDP_PARAM_HEADER_PTP(p) \ + (((p)->parameter_table_pointer[2] << 16) | \ + ((p)->parameter_table_pointer[1] << 8) | \ + ((p)->parameter_table_pointer[0] << 0)) + +#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ +#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ +#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */ + +#define SFDP_SIGNATURE 0x50444653U +#define SFDP_JESD216_MAJOR 1 +#define SFDP_JESD216_MINOR 0 +#define SFDP_JESD216A_MINOR 5 +#define SFDP_JESD216B_MINOR 6 + +struct sfdp_header { + u32 signature; /* Ox50444653U <=> "SFDP" */ + u8 minor; + u8 major; + u8 nph; /* 0-base number of parameter headers */ + u8 unused; + + /* Basic Flash Parameter Table. */ + struct sfdp_parameter_header bfpt_header; +}; + +/* Basic Flash Parameter Table */ + +/* + * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. + * They are indexed from 1 but C arrays are indexed from 0. + */ +#define BFPT_DWORD(i) ((i) - 1) +#define BFPT_DWORD_MAX 16 + +/* The first version of JESB216 defined only 9 DWORDs. */ +#define BFPT_DWORD_MAX_JESD216 9 + +/* 1st DWORD. */ +#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) +#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) +#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) +#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) +#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) +#define BFPT_DWORD1_DTR BIT(19) +#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) +#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) +#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) + +/* 5th DWORD. */ +#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) +#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) + +/* 11th DWORD. */ +#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 +#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) + +/* 15th DWORD. */ + +/* + * (from JESD216 rev B) + * Quad Enable Requirements (QER): + * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 + * reads based on instruction. DQ3/HOLD# functions are hold during + * instruction phase. + * - 001b: QE is bit 1 of status register 2. It is set via Write Status with + * two data bytes where bit 1 of the second byte is one. + * [...] + * Writing only one byte to the status register has the side-effect of + * clearing status register 2, including the QE bit. The 100b code is + * used if writing one byte to the status register does not modify + * status register 2. + * - 010b: QE is bit 6 of status register 1. It is set via Write Status with + * one data byte where bit 6 is one. + * [...] + * - 011b: QE is bit 7 of status register 2. It is set via Write status + * register 2 instruction 3Eh with one data byte where bit 7 is one. + * [...] + * The status register 2 is read using instruction 3Fh. + * - 100b: QE is bit 1 of status register 2. It is set via Write Status with + * two data bytes where bit 1 of the second byte is one. + * [...] + * In contrast to the 001b code, writing one byte to the status + * register does not modify status register 2. + * - 101b: QE is bit 1 of status register 2. Status register 1 is read using + * Read Status instruction 05h. Status register2 is read using + * instruction 35h. QE is set via Writ Status instruction 01h with + * two data bytes where bit 1 of the second byte is one. + * [...] + */ +#define BFPT_DWORD15_QER_MASK GENMASK(22, 20) +#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ +#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) +#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ +#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) +#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) +#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ + +struct sfdp_bfpt { + u32 dwords[BFPT_DWORD_MAX]; +}; + static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op *op, void *buf) { @@ -1528,118 +1640,6 @@ read_err: return ret; } -struct sfdp_parameter_header { - u8 id_lsb; - u8 minor; - u8 major; - u8 length; /* in double words */ - u8 parameter_table_pointer[3]; /* byte address */ - u8 id_msb; -}; - -#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) -#define SFDP_PARAM_HEADER_PTP(p) \ - (((p)->parameter_table_pointer[2] << 16) | \ - ((p)->parameter_table_pointer[1] << 8) | \ - ((p)->parameter_table_pointer[0] << 0)) - -#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ -#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ -#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */ - -#define SFDP_SIGNATURE 0x50444653U -#define SFDP_JESD216_MAJOR 1 -#define SFDP_JESD216_MINOR 0 -#define SFDP_JESD216A_MINOR 5 -#define SFDP_JESD216B_MINOR 6 - -struct sfdp_header { - u32 signature; /* Ox50444653U <=> "SFDP" */ - u8 minor; - u8 major; - u8 nph; /* 0-base number of parameter headers */ - u8 unused; - - /* Basic Flash Parameter Table. */ - struct sfdp_parameter_header bfpt_header; -}; - -/* Basic Flash Parameter Table */ - -/* - * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. - * They are indexed from 1 but C arrays are indexed from 0. - */ -#define BFPT_DWORD(i) ((i) - 1) -#define BFPT_DWORD_MAX 16 - -/* The first version of JESB216 defined only 9 DWORDs. */ -#define BFPT_DWORD_MAX_JESD216 9 - -/* 1st DWORD. */ -#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) -#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) -#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) -#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) -#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) -#define BFPT_DWORD1_DTR BIT(19) -#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) -#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) -#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) - -/* 5th DWORD. */ -#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) -#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) - -/* 11th DWORD. */ -#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 -#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) - -/* 15th DWORD. */ - -/* - * (from JESD216 rev B) - * Quad Enable Requirements (QER): - * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 - * reads based on instruction. DQ3/HOLD# functions are hold during - * instruction phase. - * - 001b: QE is bit 1 of status register 2. It is set via Write Status with - * two data bytes where bit 1 of the second byte is one. - * [...] - * Writing only one byte to the status register has the side-effect of - * clearing status register 2, including the QE bit. The 100b code is - * used if writing one byte to the status register does not modify - * status register 2. - * - 010b: QE is bit 6 of status register 1. It is set via Write Status with - * one data byte where bit 6 is one. - * [...] - * - 011b: QE is bit 7 of status register 2. It is set via Write status - * register 2 instruction 3Eh with one data byte where bit 7 is one. - * [...] - * The status register 2 is read using instruction 3Fh. - * - 100b: QE is bit 1 of status register 2. It is set via Write Status with - * two data bytes where bit 1 of the second byte is one. - * [...] - * In contrast to the 001b code, writing one byte to the status - * register does not modify status register 2. - * - 101b: QE is bit 1 of status register 2. Status register 1 is read using - * Read Status instruction 05h. Status register2 is read using - * instruction 35h. QE is set via Writ Status instruction 01h with - * two data bytes where bit 1 of the second byte is one. - * [...] - */ -#define BFPT_DWORD15_QER_MASK GENMASK(22, 20) -#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ -#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) -#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ -#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) -#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) -#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ - -struct sfdp_bfpt { - u32 dwords[BFPT_DWORD_MAX]; -}; - /* Fast Read settings. */ static void From 8702188ce5479729c81863680fb8ac7fffbd6b6a Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:13 +0530 Subject: [PATCH 215/250] mtd: spi-nor-core: Introduce flash-specific fixup hooks Sometimes the information in a flash's SFDP tables is wrong. Sometimes some information just can't be expressed in the SFDP table. So, introduce the fixup hooks to allow tailoring settings for a specific flash. Three hooks are added: default_init, post_sfdp, and post_bfpt. These allow tweaking the flash settings at different point in the probe sequence. Since the hooks reside in nor->info, set that value just before the call to spi_nor_init_params(). The hooks and at what points they are executed mimics Linux's spi-nor framework. One major difference is that Linux puts the struct spi_nor_fixups in nor->info. This is not possible in U-Boot because the spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c. Since spi-nor-tiny shouldn't have those fixup hooks populated, add a separate function that lets flashes populate their fixup hooks. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 78 ++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 2 + 2 files changed, 77 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 312628c080a..013a48d2efd 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -152,6 +152,31 @@ struct sfdp_bfpt { u32 dwords[BFPT_DWORD_MAX]; }; +/** + * struct spi_nor_fixups - SPI NOR fixup hooks + * @default_init: called after default flash parameters init. Used to tweak + * flash parameters when information provided by the flash_info + * table is incomplete or wrong. + * @post_bfpt: called after the BFPT table has been parsed + * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs + * that do not support RDSFDP). Typically used to tweak various + * parameters that could not be extracted by other means (i.e. + * when information provided by the SFDP/flash_info tables are + * incomplete or wrong). + * + * Those hooks can be used to tweak the SPI NOR configuration when the SFDP + * table is broken or not available. + */ +struct spi_nor_fixups { + void (*default_init)(struct spi_nor *nor); + int (*post_bfpt)(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params); + void (*post_sfdp)(struct spi_nor *nor, + struct spi_nor_flash_parameter *params); +}; + static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op *op, void *buf) { @@ -1751,6 +1776,18 @@ static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { static int spi_nor_hwcaps_read2cmd(u32 hwcaps); +static int +spi_nor_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + if (nor->fixups && nor->fixups->post_bfpt) + return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params); + + return 0; +} + /** * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. * @nor: pointer to a 'struct spi_nor' @@ -1889,7 +1926,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, /* Stop here if not JESD216 rev A or later. */ if (bfpt_header->length < BFPT_DWORD_MAX) - return 0; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, + params); /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ params->page_size = bfpt.dwords[BFPT_DWORD(11)]; @@ -1922,7 +1960,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EINVAL; } - return 0; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); } /** @@ -2085,6 +2123,29 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, } #endif /* SPI_FLASH_SFDP_SUPPORT */ +/** + * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings + * after SFDP has been parsed (is also called for SPI NORs that do not + * support RDSFDP). + * @nor: pointer to a 'struct spi_nor' + * + * Typically used to tweak various parameters that could not be extracted by + * other means (i.e. when information provided by the SFDP/flash_info tables + * are incomplete or wrong). + */ +static void spi_nor_post_sfdp_fixups(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + if (nor->fixups && nor->fixups->post_sfdp) + nor->fixups->post_sfdp(nor, params); +} + +static void spi_nor_default_init_fixups(struct spi_nor *nor) +{ + if (nor->fixups && nor->fixups->default_init) + nor->fixups->default_init(nor); +} + static int spi_nor_init_params(struct spi_nor *nor, const struct flash_info *info, struct spi_nor_flash_parameter *params) @@ -2164,6 +2225,8 @@ static int spi_nor_init_params(struct spi_nor *nor, } } + spi_nor_default_init_fixups(nor); + /* Override the parameters with data read from SFDP tables. */ nor->addr_width = 0; nor->mtd.erasesize = 0; @@ -2180,6 +2243,8 @@ static int spi_nor_init_params(struct spi_nor *nor, } } + spi_nor_post_sfdp_fixups(nor, params); + return 0; } @@ -2428,6 +2493,10 @@ static int spi_nor_init(struct spi_nor *nor) return 0; } +void spi_nor_set_fixups(struct spi_nor *nor) +{ +} + int spi_nor_scan(struct spi_nor *nor) { struct spi_nor_flash_parameter params; @@ -2476,6 +2545,10 @@ int spi_nor_scan(struct spi_nor *nor) info = spi_nor_read_id(nor); if (IS_ERR_OR_NULL(info)) return -ENOENT; + nor->info = info; + + spi_nor_set_fixups(nor); + /* Parse the Serial Flash Discoverable Parameters table. */ ret = spi_nor_init_params(nor, info, ¶ms); if (ret) @@ -2578,7 +2651,6 @@ int spi_nor_scan(struct spi_nor *nor) } /* Send all the required SPI flash commands to initialize device */ - nor->info = info; ret = spi_nor_init(nor); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 47a2eced696..b2e9e0895b8 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -416,6 +416,7 @@ struct spi_flash { * @write_proto: the SPI protocol for write operations * @reg_proto the SPI protocol for read_reg/write_reg/erase operations * @cmd_buf: used by the write_reg + * @fixups: flash-specific fixup hooks. * @prepare: [OPTIONAL] do some preparations for the * read/write/erase/lock/unlock operations * @unprepare: [OPTIONAL] do some post work after the @@ -457,6 +458,7 @@ struct spi_nor { bool sst_write_second; u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; + struct spi_nor_fixups *fixups; int (*setup)(struct spi_nor *nor, const struct flash_info *info, const struct spi_nor_flash_parameter *params, From 71025f013ccb2da5a39e60cec319f1fdef031d3d Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:14 +0530 Subject: [PATCH 216/250] mtd: spi-nor-core: Rework hwcaps selection The spi-mem layer provides a spi_mem_supports_op() function to check whether a specific operation is supported by the controller or not. This is much more accurate than the hwcaps selection logic based on SPI_{RX,TX}_ flags. Rework the hwcaps selection logic to use spi_mem_supports_op(). To make sure the build doesn't break for boards not using CONFIG_DM_SPI, add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm similar to spi_mem_default_supports_op(). This change is only compile-tested. To avoid SPL size problems on the x530 board, the old hwcaps selection is still kept around. Leaving the code in-place was getting difficult to read and understand, so the code is restructured to have it all in one isolated function. As a result of this, the parameter hwcaps to spi_nor_setup() is no longer needed. Remove it. Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps selection for the spi-mem case, 2019-08-06) Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 9 ++ drivers/mtd/spi/spi-nor-core.c | 244 ++++++++++++++++++++++++++------- drivers/spi/spi-mem-nodm.c | 62 +++++++++ include/linux/mtd/spi-nor.h | 17 ++- 4 files changed, 280 insertions(+), 52 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index f8db8e5213a..a701167dccf 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -88,6 +88,15 @@ config SPI_FLASH_SFDP_SUPPORT SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) tables as per JESD216 standard. +config SPI_FLASH_SMART_HWCAPS + bool "Smart hardware capability detection based on SPI MEM supports_op() hook" + default y + help + Enable support for smart hardware capability detection based on SPI + MEM supports_op() hook that lets controllers express whether they + can support a type of operation in a much more refined way compared + to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. + config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 013a48d2efd..24c6b8c4a39 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2299,6 +2299,194 @@ static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) ARRAY_SIZE(hwcaps_pp2cmd)); } +#ifdef CONFIG_SPI_FLASH_SMART_HWCAPS +/** + * spi_nor_check_op - check if the operation is supported by controller + * @nor: pointer to a 'struct spi_nor' + * @op: pointer to op template to be checked + * + * Returns 0 if operation is supported, -ENOTSUPP otherwise. + */ +static int spi_nor_check_op(struct spi_nor *nor, + struct spi_mem_op *op) +{ + /* + * First test with 4 address bytes. The opcode itself might be a 3B + * addressing opcode but we don't care, because SPI controller + * implementation should not check the opcode, but just the sequence. + */ + op->addr.nbytes = 4; + if (!spi_mem_supports_op(nor->spi, op)) { + if (nor->mtd.size > SZ_16M) + return -ENOTSUPP; + + /* If flash size <= 16MB, 3 address bytes are sufficient */ + op->addr.nbytes = 3; + if (!spi_mem_supports_op(nor->spi, op)) + return -ENOTSUPP; + } + + return 0; +} + +/** + * spi_nor_check_readop - check if the read op is supported by controller + * @nor: pointer to a 'struct spi_nor' + * @read: pointer to op template to be checked + * + * Returns 0 if operation is supported, -ENOTSUPP otherwise. + */ +static int spi_nor_check_readop(struct spi_nor *nor, + const struct spi_nor_read_command *read) +{ + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1), + SPI_MEM_OP_ADDR(3, 0, 1), + SPI_MEM_OP_DUMMY(0, 1), + SPI_MEM_OP_DATA_IN(0, NULL, 1)); + + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto); + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto); + op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto); + op.dummy.buswidth = op.addr.buswidth; + op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * + op.dummy.buswidth / 8; + + return spi_nor_check_op(nor, &op); +} + +/** + * spi_nor_check_pp - check if the page program op is supported by controller + * @nor: pointer to a 'struct spi_nor' + * @pp: pointer to op template to be checked + * + * Returns 0 if operation is supported, -ENOTSUPP otherwise. + */ +static int spi_nor_check_pp(struct spi_nor *nor, + const struct spi_nor_pp_command *pp) +{ + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1), + SPI_MEM_OP_ADDR(3, 0, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(0, NULL, 1)); + + op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto); + op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); + op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); + + return spi_nor_check_op(nor, &op); +} + +/** + * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI + * controller capabilities + * @nor: pointer to a 'struct spi_nor' + * @params: pointer to the 'struct spi_nor_flash_parameter' + * representing SPI NOR flash capabilities + * @hwcaps: pointer to resulting capabilities after adjusting + * according to controller and flash's capability + * + * Discard caps based on what the SPI controller actually supports (using + * spi_mem_supports_op()). + */ +static void +spi_nor_adjust_hwcaps(struct spi_nor *nor, + const struct spi_nor_flash_parameter *params, + u32 *hwcaps) +{ + unsigned int cap; + + /* + * Enable all caps by default. We will mask them after checking what's + * really supported using spi_mem_supports_op(). + */ + *hwcaps = SNOR_HWCAPS_ALL; + + /* DTR modes are not supported yet, mask them all. */ + *hwcaps &= ~SNOR_HWCAPS_DTR; + + /* X-X-X modes are not supported yet, mask them all. */ + *hwcaps &= ~SNOR_HWCAPS_X_X_X; + + for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { + int rdidx, ppidx; + + if (!(*hwcaps & BIT(cap))) + continue; + + rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); + if (rdidx >= 0 && + spi_nor_check_readop(nor, ¶ms->reads[rdidx])) + *hwcaps &= ~BIT(cap); + + ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); + if (ppidx < 0) + continue; + + if (spi_nor_check_pp(nor, ¶ms->page_programs[ppidx])) + *hwcaps &= ~BIT(cap); + } +} +#else +/** + * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI + * controller capabilities + * @nor: pointer to a 'struct spi_nor' + * @params: pointer to the 'struct spi_nor_flash_parameter' + * representing SPI NOR flash capabilities + * @hwcaps: pointer to resulting capabilities after adjusting + * according to controller and flash's capability + * + * Select caps based on what the SPI controller and SPI flash both support. + */ +static void +spi_nor_adjust_hwcaps(struct spi_nor *nor, + const struct spi_nor_flash_parameter *params, + u32 *hwcaps) +{ + struct spi_slave *spi = nor->spi; + u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | + SNOR_HWCAPS_READ_4_4_4 | + SNOR_HWCAPS_READ_8_8_8 | + SNOR_HWCAPS_PP_4_4_4 | + SNOR_HWCAPS_PP_8_8_8); + u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | + SNOR_HWCAPS_PP); + + /* Get the hardware capabilities the SPI controller supports. */ + if (spi->mode & SPI_RX_OCTAL) { + spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8; + + if (spi->mode & SPI_TX_OCTAL) + spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 | + SNOR_HWCAPS_PP_1_1_8 | + SNOR_HWCAPS_PP_1_8_8); + } else if (spi->mode & SPI_RX_QUAD) { + spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4; + + if (spi->mode & SPI_TX_QUAD) + spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 | + SNOR_HWCAPS_PP_1_1_4 | + SNOR_HWCAPS_PP_1_4_4); + } else if (spi->mode & SPI_RX_DUAL) { + spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2; + + if (spi->mode & SPI_TX_DUAL) + spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2; + } + + /* + * Keep only the hardware capabilities supported by both the SPI + * controller and the SPI flash memory. + */ + *hwcaps = spi_hwcaps & params->hwcaps.mask; + if (*hwcaps & ignored_mask) { + dev_dbg(nor->dev, + "SPI n-n-n protocols are not supported yet.\n"); + *hwcaps &= ~ignored_mask; + } +} +#endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */ + static int spi_nor_select_read(struct spi_nor *nor, const struct spi_nor_flash_parameter *params, u32 shared_hwcaps) @@ -2379,30 +2567,13 @@ static int spi_nor_select_erase(struct spi_nor *nor, static int spi_nor_default_setup(struct spi_nor *nor, const struct flash_info *info, - const struct spi_nor_flash_parameter *params, - const struct spi_nor_hwcaps *hwcaps) + const struct spi_nor_flash_parameter *params) { - u32 ignored_mask, shared_mask; + u32 shared_mask; bool enable_quad_io; int err; - /* - * Keep only the hardware capabilities supported by both the SPI - * controller and the SPI flash memory. - */ - shared_mask = hwcaps->mask & params->hwcaps.mask; - - /* SPI n-n-n protocols are not supported yet. */ - ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | - SNOR_HWCAPS_READ_4_4_4 | - SNOR_HWCAPS_READ_8_8_8 | - SNOR_HWCAPS_PP_4_4_4 | - SNOR_HWCAPS_PP_8_8_8); - if (shared_mask & ignored_mask) { - dev_dbg(nor->dev, - "SPI n-n-n protocols are not supported yet.\n"); - shared_mask &= ~ignored_mask; - } + spi_nor_adjust_hwcaps(nor, params, &shared_mask); /* Select the (Fast) Read command. */ err = spi_nor_select_read(nor, params, shared_mask); @@ -2440,13 +2611,12 @@ static int spi_nor_default_setup(struct spi_nor *nor, } static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, - const struct spi_nor_flash_parameter *params, - const struct spi_nor_hwcaps *hwcaps) + const struct spi_nor_flash_parameter *params) { if (!nor->setup) return 0; - return nor->setup(nor, info, params, hwcaps); + return nor->setup(nor, info, params); } static int spi_nor_init(struct spi_nor *nor) @@ -2502,11 +2672,6 @@ int spi_nor_scan(struct spi_nor *nor) struct spi_nor_flash_parameter params; const struct flash_info *info = NULL; struct mtd_info *mtd = &nor->mtd; - struct spi_nor_hwcaps hwcaps = { - .mask = SNOR_HWCAPS_READ | - SNOR_HWCAPS_READ_FAST | - SNOR_HWCAPS_PP, - }; struct spi_slave *spi = nor->spi; int ret; @@ -2521,27 +2686,6 @@ int spi_nor_scan(struct spi_nor *nor) nor->setup = spi_nor_default_setup; - if (spi->mode & SPI_RX_OCTAL) { - hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; - - if (spi->mode & SPI_TX_OCTAL) - hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 | - SNOR_HWCAPS_PP_1_1_8 | - SNOR_HWCAPS_PP_1_8_8); - } else if (spi->mode & SPI_RX_QUAD) { - hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; - - if (spi->mode & SPI_TX_QUAD) - hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | - SNOR_HWCAPS_PP_1_1_4 | - SNOR_HWCAPS_PP_1_4_4); - } else if (spi->mode & SPI_RX_DUAL) { - hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; - - if (spi->mode & SPI_TX_DUAL) - hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; - } - info = spi_nor_read_id(nor); if (IS_ERR_OR_NULL(info)) return -ENOENT; @@ -2616,7 +2760,7 @@ int spi_nor_scan(struct spi_nor *nor) * - set the SPI protocols for register and memory accesses. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). */ - ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); + ret = spi_nor_setup(nor, info, ¶ms); if (ret) return ret; diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c index db54101383c..a228c808c74 100644 --- a/drivers/spi/spi-mem-nodm.c +++ b/drivers/spi/spi-mem-nodm.c @@ -105,3 +105,65 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, return 0; } + +static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx) +{ + u32 mode = slave->mode; + + switch (buswidth) { + case 1: + return 0; + + case 2: + if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) || + (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD)))) + return 0; + + break; + + case 4: + if ((tx && (mode & SPI_TX_QUAD)) || + (!tx && (mode & SPI_RX_QUAD))) + return 0; + + break; + case 8: + if ((tx && (mode & SPI_TX_OCTAL)) || + (!tx && (mode & SPI_RX_OCTAL))) + return 0; + + break; + + default: + break; + } + + return -ENOTSUPP; +} + +bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + if (spi_check_buswidth_req(slave, op->cmd.buswidth, true)) + return false; + + if (op->addr.nbytes && + spi_check_buswidth_req(slave, op->addr.buswidth, true)) + return false; + + if (op->dummy.nbytes && + spi_check_buswidth_req(slave, op->dummy.buswidth, true)) + return false; + + if (op->data.nbytes && + spi_check_buswidth_req(slave, op->data.buswidth, + op->data.dir == SPI_MEM_DATA_OUT)) + return false; + + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) + return false; + + if (op->cmd.nbytes != 1) + return false; + + return true; +} diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b2e9e0895b8..90b75ec8457 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -312,6 +312,20 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_PP_1_8_8 BIT(21) #define SNOR_HWCAPS_PP_8_8_8 BIT(22) +#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \ + SNOR_HWCAPS_READ_4_4_4 | \ + SNOR_HWCAPS_READ_8_8_8 | \ + SNOR_HWCAPS_PP_4_4_4 | \ + SNOR_HWCAPS_PP_8_8_8) + +#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \ + SNOR_HWCAPS_READ_1_2_2_DTR | \ + SNOR_HWCAPS_READ_1_4_4_DTR | \ + SNOR_HWCAPS_READ_1_8_8_DTR) + +#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \ + SNOR_HWCAPS_PP_MASK) + struct spi_nor_read_command { u8 num_mode_clocks; u8 num_wait_states; @@ -461,8 +475,7 @@ struct spi_nor { struct spi_nor_fixups *fixups; int (*setup)(struct spi_nor *nor, const struct flash_info *info, - const struct spi_nor_flash_parameter *params, - const struct spi_nor_hwcaps *hwcaps); + const struct spi_nor_flash_parameter *params); int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); From 6182d15b3e4a40929df22e403601fd24abd3f918 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:15 +0530 Subject: [PATCH 217/250] mtd: spi-nor-core: Do not set data direction when there is no data Even when spi_nor_write_reg() has no data to write, like when executing a write enable operation, it sets the data direction to SPI_MEM_DATA_OUT. This trips up spi_mem_check_buswidth() because it expects a data phase when there is none. Make sure the data direction is set to SPI_MEM_NO_DATA when there is no data to write. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 24c6b8c4a39..d795ecbc9fd 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -209,6 +209,9 @@ static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_OUT(len, NULL, 1)); + if (len == 0) + op.data.dir = SPI_MEM_NO_DATA; + return spi_nor_read_write_reg(nor, &op, buf); } From 95954f55e91af538cce19fea4a731cc3474de6ff Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:16 +0530 Subject: [PATCH 218/250] mtd: spi-nor-core: Add support for DTR protocol Double Transfer Rate (DTR) is SPI protocol in which data is transferred on each clock edge as opposed to on each clock cycle. Make framework-level changes to allow supporting flashes in DTR mode. Right now, mixed DTR modes are not supported. So, for example a mode like 4S-4D-4D will not work. All phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 178 +++++++++++++++++++++++++-------- include/linux/mtd/spi-nor.h | 50 ++++++--- 3 files changed, 175 insertions(+), 54 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 0b63e1bfc27..d3ef69ec74f 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -68,6 +68,7 @@ struct flash_info { #define USE_CLSR BIT(14) /* use CLSR command */ #define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */ #define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */ +#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */ }; extern const struct flash_info spi_nor_ids[]; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d795ecbc9fd..c2eae885e41 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -177,6 +177,76 @@ struct spi_nor_fixups { struct spi_nor_flash_parameter *params); }; +/** + * spi_nor_get_cmd_ext() - Get the command opcode extension based on the + * extension type. + * @nor: pointer to a 'struct spi_nor' + * @op: pointer to the 'struct spi_mem_op' whose properties + * need to be initialized. + * + * Right now, only "repeat" and "invert" are supported. + * + * Return: The opcode extension. + */ +static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, + const struct spi_mem_op *op) +{ + switch (nor->cmd_ext_type) { + case SPI_NOR_EXT_INVERT: + return ~op->cmd.opcode; + + case SPI_NOR_EXT_REPEAT: + return op->cmd.opcode; + + default: + dev_dbg(nor->dev, "Unknown command extension type\n"); + return 0; + } +} + +/** + * spi_nor_setup_op() - Set up common properties of a spi-mem op. + * @nor: pointer to a 'struct spi_nor' + * @op: pointer to the 'struct spi_mem_op' whose properties + * need to be initialized. + * @proto: the protocol from which the properties need to be set. + */ +static void spi_nor_setup_op(const struct spi_nor *nor, + struct spi_mem_op *op, + const enum spi_nor_protocol proto) +{ + u8 ext; + + op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); + + if (op->addr.nbytes) + op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); + + if (op->dummy.nbytes) + op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); + + if (op->data.nbytes) + op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); + + if (spi_nor_protocol_is_dtr(proto)) { + /* + * spi-mem supports mixed DTR modes, but right now we can only + * have all phases either DTR or STR. IOW, spi-mem can have + * something like 4S-4D-4D, but spi-nor can't. So, set all 4 + * phases to either DTR or STR. + */ + op->cmd.dtr = op->addr.dtr = op->dummy.dtr = + op->data.dtr = true; + + /* 2 bytes per clock cycle in DTR mode. */ + op->dummy.nbytes *= 2; + + ext = spi_nor_get_cmd_ext(nor, op); + op->cmd.opcode = (op->cmd.opcode << 8) | ext; + op->cmd.nbytes = 2; + } +} + static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op *op, void *buf) { @@ -189,12 +259,14 @@ static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) { - struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 0), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(len, NULL, 1)); + SPI_MEM_OP_DATA_IN(len, NULL, 0)); int ret; + spi_nor_setup_op(nor, &op, nor->reg_proto); + ret = spi_nor_read_write_reg(nor, &op, val); if (ret < 0) dev_dbg(nor->dev, "error %d reading %x\n", ret, code); @@ -204,10 +276,12 @@ static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { - struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(len, NULL, 1)); + SPI_MEM_OP_DATA_OUT(len, NULL, 0)); + + spi_nor_setup_op(nor, &op, nor->reg_proto); if (len == 0) op.data.dir = SPI_MEM_NO_DATA; @@ -219,21 +293,19 @@ static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u_char *buf) { struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), - SPI_MEM_OP_ADDR(nor->addr_width, from, 1), - SPI_MEM_OP_DUMMY(nor->read_dummy, 1), - SPI_MEM_OP_DATA_IN(len, buf, 1)); + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), + SPI_MEM_OP_ADDR(nor->addr_width, from, 0), + SPI_MEM_OP_DUMMY(nor->read_dummy, 0), + SPI_MEM_OP_DATA_IN(len, buf, 0)); size_t remaining = len; int ret; - /* get transfer protocols. */ - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); - op.dummy.buswidth = op.addr.buswidth; - op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); + spi_nor_setup_op(nor, &op, nor->read_proto); /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + if (spi_nor_protocol_is_dtr(nor->read_proto)) + op.dummy.nbytes *= 2; while (remaining) { op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; @@ -257,20 +329,17 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, const u_char *buf) { struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), - SPI_MEM_OP_ADDR(nor->addr_width, to, 1), + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), + SPI_MEM_OP_ADDR(nor->addr_width, to, 0), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(len, buf, 1)); + SPI_MEM_OP_DATA_OUT(len, buf, 0)); int ret; - /* get transfer protocols. */ - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); - op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); - if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) op.addr.nbytes = 0; + spi_nor_setup_op(nor, &op, nor->write_proto); + ret = spi_mem_adjust_op_size(nor->spi, &op); if (ret) return ret; @@ -668,11 +737,13 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) { struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), - SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, nor->write_proto); + if (nor->erase) return nor->erase(nor, addr); @@ -2194,11 +2265,25 @@ static int spi_nor_init_params(struct spi_nor *nor, SNOR_PROTO_1_1_8); } + if (info->flags & SPI_NOR_OCTAL_DTR_READ) { + params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, SPINOR_OP_READ_FAST, + SNOR_PROTO_8_8_8_DTR); + } + /* Page Program settings. */ params->hwcaps.mask |= SNOR_HWCAPS_PP; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], SPINOR_OP_PP, SNOR_PROTO_1_1_1); + /* + * Since xSPI Page Program opcode is backward compatible with + * Legacy SPI, use Legacy SPI opcode there as well. + */ + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], + SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); + if (info->flags & SPI_NOR_QUAD_READ) { params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], @@ -2233,7 +2318,8 @@ static int spi_nor_init_params(struct spi_nor *nor, /* Override the parameters with data read from SFDP tables. */ nor->addr_width = 0; nor->mtd.erasesize = 0; - if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && + if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_OCTAL_DTR_READ)) && !(info->flags & SPI_NOR_SKIP_SFDP)) { struct spi_nor_flash_parameter sfdp_params; @@ -2280,6 +2366,7 @@ static int spi_nor_hwcaps_read2cmd(u32 hwcaps) { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, + { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, @@ -2296,6 +2383,7 @@ static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, + { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, @@ -2342,17 +2430,17 @@ static int spi_nor_check_op(struct spi_nor *nor, static int spi_nor_check_readop(struct spi_nor *nor, const struct spi_nor_read_command *read) { - struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1), - SPI_MEM_OP_ADDR(3, 0, 1), - SPI_MEM_OP_DUMMY(0, 1), - SPI_MEM_OP_DATA_IN(0, NULL, 1)); + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), + SPI_MEM_OP_ADDR(3, 0, 0), + SPI_MEM_OP_DUMMY(1, 0), + SPI_MEM_OP_DATA_IN(2, NULL, 0)); + + spi_nor_setup_op(nor, &op, read->proto); - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto); - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto); - op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto); - op.dummy.buswidth = op.addr.buswidth; op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * op.dummy.buswidth / 8; + if (spi_nor_protocol_is_dtr(nor->read_proto)) + op.dummy.nbytes *= 2; return spi_nor_check_op(nor, &op); } @@ -2367,14 +2455,12 @@ static int spi_nor_check_readop(struct spi_nor *nor, static int spi_nor_check_pp(struct spi_nor *nor, const struct spi_nor_pp_command *pp) { - struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1), - SPI_MEM_OP_ADDR(3, 0, 1), + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), + SPI_MEM_OP_ADDR(3, 0, 0), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(0, NULL, 1)); + SPI_MEM_OP_DATA_OUT(2, NULL, 0)); - op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto); - op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); - op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); + spi_nor_setup_op(nor, &op, pp->proto); return spi_nor_check_op(nor, &op); } @@ -2404,12 +2490,16 @@ spi_nor_adjust_hwcaps(struct spi_nor *nor, */ *hwcaps = SNOR_HWCAPS_ALL; - /* DTR modes are not supported yet, mask them all. */ - *hwcaps &= ~SNOR_HWCAPS_DTR; - /* X-X-X modes are not supported yet, mask them all. */ *hwcaps &= ~SNOR_HWCAPS_X_X_X; + /* + * If the reset line is broken, we do not want to enter a stateful + * mode. + */ + if (nor->flags & SNOR_F_BROKEN_RESET) + *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR); + for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { int rdidx, ppidx; @@ -2649,6 +2739,7 @@ static int spi_nor_init(struct spi_nor *nor) } if (nor->addr_width == 4 && + !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) && (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && !(nor->info->flags & SPI_NOR_4B_OPCODES)) { /* @@ -2767,7 +2858,10 @@ int spi_nor_scan(struct spi_nor *nor) if (ret) return ret; - if (nor->addr_width) { + if (spi_nor_protocol_is_dtr(nor->read_proto)) { + /* Always use 4-byte addresses in DTR mode. */ + nor->addr_width = 4; + } else if (nor->addr_width) { /* already configured from SFDP */ } else if (info->addr_width) { nor->addr_width = info->addr_width; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 90b75ec8457..4394cb6e16b 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -200,6 +200,7 @@ enum spi_nor_protocol { SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), + SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8), }; static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) @@ -267,7 +268,7 @@ struct spi_nor_hwcaps { * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly * (Slow) Read. */ -#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) +#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0) #define SNOR_HWCAPS_READ BIT(0) #define SNOR_HWCAPS_READ_FAST BIT(1) #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) @@ -284,11 +285,12 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_READ_4_4_4 BIT(9) #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) -#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) +#define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11) #define SNOR_HWCAPS_READ_1_1_8 BIT(11) #define SNOR_HWCAPS_READ_1_8_8 BIT(12) #define SNOR_HWCAPS_READ_8_8_8 BIT(13) #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) +#define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15) /* * Page Program capabilities. @@ -299,18 +301,19 @@ struct spi_nor_hwcaps { * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory * implements such commands. */ -#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) -#define SNOR_HWCAPS_PP BIT(16) +#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16) +#define SNOR_HWCAPS_PP BIT(16) -#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) -#define SNOR_HWCAPS_PP_1_1_4 BIT(17) -#define SNOR_HWCAPS_PP_1_4_4 BIT(18) -#define SNOR_HWCAPS_PP_4_4_4 BIT(19) +#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) +#define SNOR_HWCAPS_PP_1_1_4 BIT(17) +#define SNOR_HWCAPS_PP_1_4_4 BIT(18) +#define SNOR_HWCAPS_PP_4_4_4 BIT(19) -#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) -#define SNOR_HWCAPS_PP_1_1_8 BIT(20) -#define SNOR_HWCAPS_PP_1_8_8 BIT(21) -#define SNOR_HWCAPS_PP_8_8_8 BIT(22) +#define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20) +#define SNOR_HWCAPS_PP_1_1_8 BIT(20) +#define SNOR_HWCAPS_PP_1_8_8 BIT(21) +#define SNOR_HWCAPS_PP_8_8_8 BIT(22) +#define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23) #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \ SNOR_HWCAPS_READ_4_4_4 | \ @@ -318,6 +321,9 @@ struct spi_nor_hwcaps { SNOR_HWCAPS_PP_4_4_4 | \ SNOR_HWCAPS_PP_8_8_8) +#define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \ + SNOR_HWCAPS_PP_8_8_8_DTR) + #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \ SNOR_HWCAPS_READ_1_2_2_DTR | \ SNOR_HWCAPS_READ_1_4_4_DTR | \ @@ -360,6 +366,7 @@ enum spi_nor_read_command_index { SNOR_CMD_READ_1_8_8, SNOR_CMD_READ_8_8_8, SNOR_CMD_READ_1_8_8_DTR, + SNOR_CMD_READ_8_8_8_DTR, SNOR_CMD_READ_MAX }; @@ -376,6 +383,7 @@ enum spi_nor_pp_command_index { SNOR_CMD_PP_1_1_8, SNOR_CMD_PP_1_8_8, SNOR_CMD_PP_8_8_8, + SNOR_CMD_PP_8_8_8_DTR, SNOR_CMD_PP_MAX }; @@ -391,6 +399,22 @@ struct spi_nor_flash_parameter { int (*quad_enable)(struct spi_nor *nor); }; +/** + * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode + * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy + * SPI mode + * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode + * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode + * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode + * combine to form a 16-bit opcode. + */ +enum spi_nor_cmd_ext { + SPI_NOR_EXT_NONE = 0, + SPI_NOR_EXT_REPEAT, + SPI_NOR_EXT_INVERT, + SPI_NOR_EXT_HEX, +}; + /** * struct flash_info - Forward declaration of a structure used internally by * spi_nor_scan() @@ -430,6 +454,7 @@ struct spi_flash { * @write_proto: the SPI protocol for write operations * @reg_proto the SPI protocol for read_reg/write_reg/erase operations * @cmd_buf: used by the write_reg + * @cmd_ext_type: the command opcode extension for DTR mode. * @fixups: flash-specific fixup hooks. * @prepare: [OPTIONAL] do some preparations for the * read/write/erase/lock/unlock operations @@ -472,6 +497,7 @@ struct spi_nor { bool sst_write_second; u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; + enum spi_nor_cmd_ext cmd_ext_type; struct spi_nor_fixups *fixups; int (*setup)(struct spi_nor *nor, const struct flash_info *info, From 22ae535b7d6d963481548ce66070a6784849a136 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:17 +0530 Subject: [PATCH 219/250] mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to reflect that. The check for rev A or later compared the BFPT header length with the maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so was the BFPT length for both rev A and B, this check worked fine. But now, since BFPT_DWORD_MAX is 20, it means this check will also stop BFPT parsing for rev A or B, since their length is 16. So, instead check for BFPT_DWORD_MAX_JESD216 to stop BFPT parsing for the first JESD216 version, and check for BFPT_DWORD_MAX_JESD216B for the next two versions. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index c2eae885e41..5a655976163 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -79,14 +79,15 @@ struct sfdp_header { /* Basic Flash Parameter Table */ /* - * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. + * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. * They are indexed from 1 but C arrays are indexed from 0. */ #define BFPT_DWORD(i) ((i) - 1) -#define BFPT_DWORD_MAX 16 +#define BFPT_DWORD_MAX 20 /* The first version of JESB216 defined only 9 DWORDs. */ #define BFPT_DWORD_MAX_JESD216 9 +#define BFPT_DWORD_MAX_JESD216B 16 /* 1st DWORD. */ #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) @@ -1999,7 +2000,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, } /* Stop here if not JESD216 rev A or later. */ - if (bfpt_header->length < BFPT_DWORD_MAX) + if (bfpt_header->length == BFPT_DWORD_MAX_JESD216) return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); @@ -2034,6 +2035,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EINVAL; } + /* Stop here if JESD216 rev B. */ + if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B) + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, + params); + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); } From 9ec5ea01277d8a9fdd29e797a9e0923575e5ce9f Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:18 +0530 Subject: [PATCH 220/250] mtd: spi-nor-core: Get command opcode extension type from BFPT Some devices in DTR mode expect an extra command byte called the extension. The extension can either be same as the opcode, bitwise inverse of the opcode, or another additional byte forming a 16-byte opcode. Get the extension type from the BFPT. For now, only flashes with "repeat" and "inverse" extensions are supported. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5a655976163..d9af5cbf97f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -149,6 +149,12 @@ struct sfdp_header { #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ +#define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) +#define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ +#define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ +#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ +#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ + struct sfdp_bfpt { u32 dwords[BFPT_DWORD_MAX]; }; @@ -2040,6 +2046,24 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); + /* 8D-8D-8D command extension. */ + switch (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_CMD_EXT_MASK) { + case BFPT_DWORD18_CMD_EXT_REP: + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; + break; + + case BFPT_DWORD18_CMD_EXT_INV: + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; + break; + + case BFPT_DWORD18_CMD_EXT_RES: + return -EINVAL; + + case BFPT_DWORD18_CMD_EXT_16B: + dev_err(nor->dev, "16-bit opcodes not supported\n"); + return -ENOTSUPP; + } + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); } From 4d40e82663fe5ed8b65242bc28b3faaf838f5dcc Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:19 +0530 Subject: [PATCH 221/250] mtd: spi-nor-core: Parse xSPI Profile 1.0 table This table is indication that the flash is xSPI compliant and hence supports octal DTR mode. Extract information like the fast read opcode, the number of dummy cycles needed for a Read Status Register command, and the number of address bytes needed for a Read Status Register command. The default dummy cycles for a fast octal DTR read are set to 20. Since there is no simple way of determining the dummy cycles needed for the fast read command, flashes that use a different value should update it in their flash-specific hooks. Signed-off-by: Pratyush Yadav Acked-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 100 +++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 7 +++ 2 files changed, 107 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d9af5cbf97f..b3b04db8bfb 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,8 @@ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) +#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) + struct sfdp_parameter_header { u8 id_lsb; u8 minor; @@ -58,6 +61,7 @@ struct sfdp_parameter_header { #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */ +#define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */ #define SFDP_SIGNATURE 0x50444653U #define SFDP_JESD216_MAJOR 1 @@ -155,6 +159,16 @@ struct sfdp_header { #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ +/* xSPI Profile 1.0 table (from JESD216D.01). */ +#define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8) +#define PROFILE1_DWORD1_RDSR_DUMMY BIT(28) +#define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29) +#define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7) +#define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27) +#define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17) +#define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7) +#define PROFILE1_DUMMY_DEFAULT 20 + struct sfdp_bfpt { u32 dwords[BFPT_DWORD_MAX]; }; @@ -2095,6 +2109,86 @@ spi_nor_parse_microchip_sfdp(struct spi_nor *nor, return ret; } +/** + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table + * @nor: pointer to a 'struct spi_nor' + * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing + * the 4-Byte Address Instruction Table length and version. + * @params: pointer to the 'struct spi_nor_flash_parameter' to be. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_parse_profile1(struct spi_nor *nor, + const struct sfdp_parameter_header *profile1_header, + struct spi_nor_flash_parameter *params) +{ + u32 *table, opcode, addr; + size_t len; + int ret, i; + u8 dummy; + + len = profile1_header->length * sizeof(*table); + table = kmalloc(len, GFP_KERNEL); + if (!table) + return -ENOMEM; + + addr = SFDP_PARAM_HEADER_PTP(profile1_header); + ret = spi_nor_read_sfdp(nor, addr, len, table); + if (ret) + goto out; + + /* Fix endianness of the table DWORDs. */ + for (i = 0; i < profile1_header->length; i++) + table[i] = le32_to_cpu(table[i]); + + /* Get 8D-8D-8D fast read opcode and dummy cycles. */ + opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]); + + /* + * We don't know what speed the controller is running at. Find the + * dummy cycles for the fastest frequency the flash can run at to be + * sure we are never short of dummy cycles. A value of 0 means the + * frequency is not supported. + * + * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let + * flashes set the correct value if needed in their fixup hooks. + */ + dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]); + if (!dummy) + dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]); + if (!dummy) + dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]); + if (!dummy) + dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]); + if (!dummy) + dummy = PROFILE1_DUMMY_DEFAULT; + + /* Round up to an even value to avoid tripping controllers up. */ + dummy = ROUND_UP_TO(dummy, 2); + + /* Update the fast read settings. */ + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, dummy, opcode, + SNOR_PROTO_8_8_8_DTR); + + /* + * Set the Read Status Register dummy cycles and dummy address bytes. + */ + if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY) + params->rdsr_dummy = 8; + else + params->rdsr_dummy = 4; + + if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES) + params->rdsr_addr_nbytes = 4; + else + params->rdsr_addr_nbytes = 0; + +out: + kfree(table); + return ret; +} + /** * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. * @nor: pointer to a 'struct spi_nor' @@ -2197,6 +2291,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, err = spi_nor_parse_microchip_sfdp(nor, param_header); break; + case SFDP_PROFILE1_ID: + err = spi_nor_parse_profile1(nor, param_header, params); + break; + default: break; } @@ -2926,6 +3024,8 @@ int spi_nor_scan(struct spi_nor *nor) if (ret) return ret; + nor->rdsr_dummy = params.rdsr_dummy; + nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes; nor->name = mtd->name; nor->size = mtd->size; nor->erase_size = mtd->erasesize; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4394cb6e16b..295583ed294 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -391,6 +391,8 @@ enum spi_nor_pp_command_index { struct spi_nor_flash_parameter { u64 size; u32 page_size; + u8 rdsr_dummy; + u8 rdsr_addr_nbytes; struct spi_nor_hwcaps hwcaps; struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; @@ -445,6 +447,9 @@ struct spi_flash { * @read_opcode: the read opcode * @read_dummy: the dummy needed by the read operation * @program_opcode: the program opcode + * @rdsr_dummy dummy cycles needed for Read Status Register command. + * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register + * command. * @bank_read_cmd: Bank read cmd * @bank_write_cmd: Bank write cmd * @bank_curr: Current flash bank @@ -486,6 +491,8 @@ struct spi_nor { u8 read_opcode; u8 read_dummy; u8 program_opcode; + u8 rdsr_dummy; + u8 rdsr_addr_nbytes; #ifdef CONFIG_SPI_FLASH_BAR u8 bank_read_cmd; u8 bank_write_cmd; From b862765c7c9a64640ce557bc10a10b4f20e8584b Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:20 +0530 Subject: [PATCH 222/250] mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in Octal DTR mode. Use that information to send the correct Read SR command. Some controllers might have trouble reading just 1 byte in DTR mode. So, when we are in DTR mode read 2 bytes and discard the second. This shows no side effects with the two flashes I tested: Micron mt35xu512aba and Cypress s28hs512t. Update Read FSR to mimic Read SR because they share the same characteristics. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 60 ++++++++++++++++++++++++++++++---- 1 file changed, 54 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b3b04db8bfb..b9d3101d579 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -380,16 +380,40 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, */ static int read_sr(struct spi_nor *nor) { + struct spi_mem_op op; int ret; - u8 val; + u8 val[2]; + u8 addr_nbytes, dummy; - ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); + if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { + addr_nbytes = nor->rdsr_addr_nbytes; + dummy = nor->rdsr_dummy; + } else { + addr_nbytes = 0; + dummy = 0; + } + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), + SPI_MEM_OP_ADDR(addr_nbytes, 0, 0), + SPI_MEM_OP_DUMMY(dummy, 0), + SPI_MEM_OP_DATA_IN(1, NULL, 0)); + + spi_nor_setup_op(nor, &op, nor->reg_proto); + + /* + * We don't want to read only one byte in DTR mode. So, read 2 and then + * discard the second byte. + */ + if (spi_nor_protocol_is_dtr(nor->reg_proto)) + op.data.nbytes = 2; + + ret = spi_nor_read_write_reg(nor, &op, val); if (ret < 0) { pr_debug("error %d reading SR\n", (int)ret); return ret; } - return val; + return *val; } /* @@ -399,16 +423,40 @@ static int read_sr(struct spi_nor *nor) */ static int read_fsr(struct spi_nor *nor) { + struct spi_mem_op op; int ret; - u8 val; + u8 val[2]; + u8 addr_nbytes, dummy; - ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); + if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { + addr_nbytes = nor->rdsr_addr_nbytes; + dummy = nor->rdsr_dummy; + } else { + addr_nbytes = 0; + dummy = 0; + } + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), + SPI_MEM_OP_ADDR(addr_nbytes, 0, 0), + SPI_MEM_OP_DUMMY(dummy, 0), + SPI_MEM_OP_DATA_IN(1, NULL, 0)); + + spi_nor_setup_op(nor, &op, nor->reg_proto); + + /* + * We don't want to read only one byte in DTR mode. So, read 2 and then + * discard the second byte. + */ + if (spi_nor_protocol_is_dtr(nor->reg_proto)) + op.data.nbytes = 2; + + ret = spi_nor_read_write_reg(nor, &op, val); if (ret < 0) { pr_debug("error %d reading FSR\n", ret); return ret; } - return val; + return *val; } /* From 6b808e0864dbd492d33e7149fb1666bef7e56049 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:21 +0530 Subject: [PATCH 223/250] mtd: spi-nor-core: Enable octal DTR mode when possible Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 31 +++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 33 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b9d3101d579..cdb464813bb 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2888,10 +2888,41 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return nor->setup(nor, info, params); } +/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed + * @nor: pointer to a 'struct spi_nor' + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_octal_dtr_enable(struct spi_nor *nor) +{ + int ret; + + if (!nor->octal_dtr_enable) + return 0; + + if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && + nor->write_proto == SNOR_PROTO_8_8_8_DTR)) + return 0; + + ret = nor->octal_dtr_enable(nor); + if (ret) + return ret; + + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + + return 0; +} + static int spi_nor_init(struct spi_nor *nor) { int err; + err = spi_nor_octal_dtr_enable(nor); + if (err) { + dev_dbg(nor->dev, "Octal DTR mode not supported\n"); + return err; + } + /* * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 295583ed294..aae814f5574 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -477,6 +477,7 @@ struct spi_flash { * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is * completely locked * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode + * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode. * @priv: the private data */ struct spi_nor { @@ -524,6 +525,7 @@ struct spi_nor { int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*quad_enable)(struct spi_nor *nor); + int (*octal_dtr_enable)(struct spi_nor *nor); void *priv; /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ From b058f108d7d91f9a5f47c1d0d3ddf4e6ae030440 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:22 +0530 Subject: [PATCH 224/250] mtd: spi-nor-core: Do not make invalid quad enable fatal The Micron MT35XU512ABA flash does not support the quad enable bit. But instead of programming the Quad Enable Require field to 000b ("Device does not have a QE bit"), it is programmed to 111b ("Reserved"). While this is technically incorrect, it is not reason enough to abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index cdb464813bb..b5b1ac8b5b1 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; #endif default: - return -EINVAL; + dev_dbg(nor->dev, "BFPT QER reserved value used\n"); + break; } /* Stop here if JESD216 rev B. */ From a1122a3d98430754626547eb0acba11645039881 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:23 +0530 Subject: [PATCH 225/250] mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 6 ++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b5b1ac8b5b1..0d38ffc4f33 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -153,6 +153,8 @@ struct sfdp_header { #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ +#define BFPT_DWORD16_SOFT_RST BIT(12) + #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ @@ -2104,6 +2106,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; } + /* Soft Reset support. */ + if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST) + nor->flags |= SNOR_F_SOFT_RESET; + /* Stop here if JESD216 rev B. */ if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B) return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index aae814f5574..b2159f63195 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -248,6 +248,7 @@ enum spi_nor_option_flags { SNOR_F_READY_XSR_RDY = BIT(4), SNOR_F_USE_CLSR = BIT(5), SNOR_F_BROKEN_RESET = BIT(6), + SNOR_F_SOFT_RESET = BIT(7), }; struct spi_nor; From 575caf45004fb9be983db33f86425c95d4619213 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:24 +0530 Subject: [PATCH 226/250] mtd: spi-nor-core: Perform a Soft Reset on shutdown On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it supports it. But Linux as of now expects to get the flash in 1S-1S-1S mode. Handing the flash to Linux in Octal DTR mode means the kernel will fail to detect the flash. So, we need to reset to Power-on-Reset (POR) state before handing off the flash. A Software Reset command can be used to do this. One limitation of the soft reset is that it will restore state from non-volatile registers in some flashes. This means that if the flash was set to 8D mode in a non-volatile configuration, a soft reset won't help. This commit assumes that we don't set any non-volatile bits anywhere, and the flash doesn't have any non-volatile Octal DTR mode configuration. Since spi-nor-tiny doesn't (and likely shouldn't) have spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does nothing. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 7 ++++ drivers/mtd/spi/sf_probe.c | 6 +++ drivers/mtd/spi/spi-nor-core.c | 68 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 17 +++++++++ 4 files changed, 98 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index a701167dccf..185ebbeb022 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS can support a type of operation in a much more refined way compared to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. +config SPI_FLASH_SOFT_RESET + bool "Software Reset support for SPI NOR flashes" + default n + help + Enable support for xSPI Software Reset. It will be used to switch from + Octal DTR mode to legacy mode on shutdown and boot (if enabled). + config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" help diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7edb8759fdc..f461082e03d 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -151,6 +151,11 @@ int spi_flash_std_probe(struct udevice *dev) static int spi_flash_std_remove(struct udevice *dev) { struct spi_flash *flash = dev_get_uclass_priv(dev); + int ret; + + ret = spi_nor_remove(flash); + if (ret) + return ret; if (CONFIG_IS_ENABLED(SPI_FLASH_MTD)) spi_flash_mtd_unregister(flash); @@ -178,6 +183,7 @@ U_BOOT_DRIVER(jedec_spi_nor) = { .remove = spi_flash_std_remove, .priv_auto = sizeof(struct spi_nor), .ops = &spi_flash_std_ops, + .flags = DM_FLAG_OS_PREPARE, }; DM_DRIVER_ALIAS(jedec_spi_nor, spansion_m25p16) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 0d38ffc4f33..642068a4e26 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -200,6 +201,8 @@ struct spi_nor_fixups { struct spi_nor_flash_parameter *params); }; +#define SPI_NOR_SRST_SLEEP_LEN 200 + /** * spi_nor_get_cmd_ext() - Get the command opcode extension based on the * extension type. @@ -2971,6 +2974,71 @@ static int spi_nor_init(struct spi_nor *nor) return 0; } +#ifdef CONFIG_SPI_FLASH_SOFT_RESET +/** + * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence + * @nor: the spi_nor structure + * + * This function can be used to switch from Octal DTR mode to legacy mode on a + * flash that supports it. The soft reset is executed in Octal DTR mode. + * + * Return: 0 for success, -errno for failure. + */ +static int spi_nor_soft_reset(struct spi_nor *nor) +{ + struct spi_mem_op op; + int ret; + enum spi_nor_cmd_ext ext; + + ext = nor->cmd_ext_type; + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Software reset enable failed: %d\n", ret); + goto out; + } + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Software reset failed: %d\n", ret); + goto out; + } + + /* + * Software Reset is not instant, and the delay varies from flash to + * flash. Looking at a few flashes, most range somewhere below 100 + * microseconds. So, wait for 200ms just to be sure. + */ + udelay(SPI_NOR_SRST_SLEEP_LEN); + +out: + nor->cmd_ext_type = ext; + return ret; +} +#endif /* CONFIG_SPI_FLASH_SOFT_RESET */ + +int spi_nor_remove(struct spi_nor *nor) +{ +#ifdef CONFIG_SPI_FLASH_SOFT_RESET + if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ && + nor->flags & SNOR_F_SOFT_RESET) + return spi_nor_soft_reset(nor); +#endif + + return 0; +} + void spi_nor_set_fixups(struct spi_nor *nor) { } diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b2159f63195..29ce1751567 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -67,6 +67,8 @@ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ +#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */ +#define SPINOR_OP_SRST 0x99 /* Software Reset */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ @@ -562,4 +564,19 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor) */ int spi_nor_scan(struct spi_nor *nor); +#if CONFIG_IS_ENABLED(SPI_FLASH_TINY) +static inline int spi_nor_remove(struct spi_nor *nor) +{ + return 0; +} +#else +/** + * spi_nor_remove() - perform cleanup before booting to the next stage + * @nor: the spi_nor structure + * + * Return: 0 for success, -errno for failure. + */ +int spi_nor_remove(struct spi_nor *nor); +#endif + #endif From 0be8ab1f166844d53477387dc9a1184161ef44ef Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:25 +0530 Subject: [PATCH 227/250] mtd: spi-nor-core: Perform a Soft Reset on boot When the flash is handed to us in a stateful mode like 8D-8D-8D, it is difficult to detect the mode the flash is in. One option is to read SFDP in all modes and see which one gives the correct "SFDP" signature, but not all flashes support SFDP in 8D-8D-8D mode. Further, even if you detect the mode of the flash via SFDP, you still have the problem of actually reading the ID. The Read ID command is not standardized across flash vendors. Flashes can have different dummy cycles needed for reading the ID. Some flashes even expect a 4-byte dummy address with the Read ID command. All this information cannot be obtained from the SFDP table. So, perform a Software Reset sequence before reading the ID and initializing the flash. A Soft Reset will bring back the flash in its default protocol mode assuming no non-volatile configuration was set. This will let us detect the flash even if ROM hands it to us in Octal DTR mode. To accommodate cases where there is more than one flash on a board, and only one of them needs a soft reset, failure to reset is not made fatal, and we still try to read ID if possible. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 10 ++++++++++ drivers/mtd/spi/spi-nor-core.c | 27 +++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 185ebbeb022..b46035aee4a 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -104,6 +104,16 @@ config SPI_FLASH_SOFT_RESET Enable support for xSPI Software Reset. It will be used to switch from Octal DTR mode to legacy mode on shutdown and boot (if enabled). +config SPI_FLASH_SOFT_RESET_ON_BOOT + bool "Perform a Software Reset on boot on flashes that boot in stateful mode" + depends on SPI_FLASH_SOFT_RESET + default n + help + Perform a Software Reset on boot to allow detecting flashes that are + handed to us in Octal DTR mode. Do not enable this config on flashes + that are not supposed to be handed to U-Boot in Octal DTR mode, even + if they _do_ support the Soft Reset sequence. + config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 642068a4e26..3bf94044905 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3062,6 +3062,33 @@ int spi_nor_scan(struct spi_nor *nor) nor->setup = spi_nor_default_setup; +#ifdef CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT + /* + * When the flash is handed to us in a stateful mode like 8D-8D-8D, it + * is difficult to detect the mode the flash is in. One option is to + * read SFDP in all modes and see which one gives the correct "SFDP" + * signature, but not all flashes support SFDP in 8D-8D-8D mode. + * + * Further, even if you detect the mode of the flash via SFDP, you + * still have the problem of actually reading the ID. The Read ID + * command is not standardized across flash vendors. Flashes can have + * different dummy cycles needed for reading the ID. Some flashes even + * expect a 4-byte dummy address with the Read ID command. All this + * information cannot be obtained from the SFDP table. + * + * So, perform a Software Reset sequence before reading the ID and + * initializing the flash. A Soft Reset will bring back the flash in + * its default protocol mode assuming no non-volatile configuration was + * set. This will let us detect the flash even if ROM hands it to us in + * Octal DTR mode. + * + * To accommodate cases where there is more than one flash on a board, + * and only one of them needs a soft reset, failure to reset is not + * made fatal, and we still try to read ID if possible. + */ + spi_nor_soft_reset(nor); +#endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */ + info = spi_nor_read_id(nor); if (IS_ERR_OR_NULL(info)) return -ENOENT; From aba0bcd7bda494d7fe9c82e581db9791ce41e2f3 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:26 +0530 Subject: [PATCH 228/250] mtd: spi-nor-core: allow truncated erases On devices with non-uniform sector sizes like Spansion S25 or S28 family of flashes the sector under erase does not necessarily have to be mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then 256 KiB sectors till the end. Let the flash-specific erase functions erase less than the requested length in case of the 4 or 128 KiB sectors and report the number of bytes erased back to the calling function. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3bf94044905..ece4bc9e84b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -806,7 +806,8 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) #endif /* - * Initiate the erasure of a single sector + * Initiate the erasure of a single sector. Returns the number of bytes erased + * on success, a negative error code on error. */ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) { @@ -815,6 +816,7 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + int ret; spi_nor_setup_op(nor, &op, nor->write_proto); @@ -825,7 +827,11 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) * Default implementation, if driver doesn't have a specialized HW * control */ - return spi_mem_exec_op(nor->spi, &op); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + return nor->mtd.erasesize; } /* @@ -861,11 +867,11 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) write_enable(nor); ret = spi_nor_erase_sector(nor, addr); - if (ret) + if (ret < 0) goto erase_err; - addr += mtd->erasesize; - len -= mtd->erasesize; + addr += ret; + len -= ret; ret = spi_nor_wait_till_ready(nor); if (ret) From ee52b0b764d3eaa69f20f7e142945d56fe3f6fdb Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Sat, 26 Jun 2021 00:47:27 +0530 Subject: [PATCH 229/250] mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or bottom, depending on the device configuration, while U-Boot supports uniform sector layout only. The spansion_erase_non_uniform() erases overlaid 4KB sectors, non-overlaid portion of normal sector, and remaining normal sectors, by selecting correct erase command and size based on the address to erase and size of overlaid portion in parameters. Since different Spansion flashes can use different opcode for erasing the 4K sectors, the opcode must be passed in as a parameter based on the flash being used. Signed-off-by: Takahiro Kuwano Signed-off-by: Pratyush Yadav [p.yadav@ti.com: Refactor the function to be compatible with nor->erase, make 4K opcode customizable, call spi_nor_setup_op() before executing the op.] Acked-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 61 ++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ece4bc9e84b..f2354fea7f8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -887,6 +887,67 @@ erase_err: return ret; } +#ifdef CONFIG_SPI_FLASH_S28HS512T +/** + * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress + * chips + * @nor: pointer to a 'struct spi_nor' + * @addr: address of the sector to erase + * @opcode_4k: opcode for 4K sector erase + * @ovlsz_top: size of overlaid portion at the top address + * @ovlsz_btm: size of overlaid portion at the bottom address + * + * Erase an address range on the nor chip that can contain 4KB sectors overlaid + * on top and/or bottom. The appropriate erase opcode and size are chosen by + * address to erase and size of overlaid portion. + * + * Return: number of bytes erased on success, -errno otherwise. + */ +static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr, + u8 opcode_4k, u32 ovlsz_top, + u32 ovlsz_btm) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + struct mtd_info *mtd = &nor->mtd; + u32 erasesize; + int ret; + + /* 4KB sectors */ + if (op.addr.val < ovlsz_btm || + op.addr.val >= mtd->size - ovlsz_top) { + op.cmd.opcode = opcode_4k; + erasesize = SZ_4K; + + /* Non-overlaid portion in the normal sector at the bottom */ + } else if (op.addr.val == ovlsz_btm) { + op.cmd.opcode = nor->erase_opcode; + erasesize = mtd->erasesize - ovlsz_btm; + + /* Non-overlaid portion in the normal sector at the top */ + } else if (op.addr.val == mtd->size - mtd->erasesize) { + op.cmd.opcode = nor->erase_opcode; + erasesize = mtd->erasesize - ovlsz_top; + + /* Normal sectors */ + } else { + op.cmd.opcode = nor->erase_opcode; + erasesize = mtd->erasesize; + } + + spi_nor_setup_op(nor, &op, nor->write_proto); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + return erasesize; +} +#endif + #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* Write status register and ensure bits in mask match written values */ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) From ea9a22f7e79cbc951a2aca204b3eec6948837827 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:28 +0530 Subject: [PATCH 230/250] mtd: spi-nor-core: Add support for Cypress Semper flash The Cypress Semper flash is an xSPI compliant octal DTR flash. Add support for using it in octal DTR mode. The flash by default boots in a hybrid sector mode. Switch to uniform sector mode on boot. Use the default 20 dummy cycles for a read fast command. The SFDP programming on some older versions of the flash was incorrect. Fixes for that are included in the fixup hooks. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 8 ++ drivers/mtd/spi/spi-nor-core.c | 187 +++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 3 + include/linux/mtd/spi-nor.h | 13 +++ 4 files changed, 211 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index b46035aee4a..98c0b234780 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -167,6 +167,14 @@ config SPI_FLASH_SPANSION help Add support for various Spansion SPI flash chips (S25FLxxx) +config SPI_FLASH_S28HS512T + bool "Cypress S28HS512T chip support" + depends on SPI_FLASH_SPANSION + help + Add support for the Cypress S28HS512T chip. This is a separate config + because the fixup hooks for this flash add extra size overhead. Boards + that don't use the flash can disable this to save space. + config SPI_FLASH_STMICRO bool "STMicro SPI flash support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f2354fea7f8..3a1060b04b2 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2965,6 +2965,189 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return nor->setup(nor, info, params); } +#ifdef CONFIG_SPI_FLASH_S28HS512T +/** + * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes. + * @nor: pointer to a 'struct spi_nor' + * + * This also sets the memory access latency cycles to 24 to allow the flash to + * run at up to 200MHz. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 buf; + u8 addr_width = 3; + int ret; + + /* Use 24 dummy cycles for memory array reads. */ + ret = write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), + SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, + "failed to set default memory latency value: %d\n", + ret); + return ret; + } + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + + nor->read_dummy = 24; + + /* Set the octal and DTR enable bits. */ + ret = write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), + SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Failed to enable octal DTR mode\n"); + return ret; + } + + return 0; +} + +static int s28hs512t_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Factory default configuration: 32 x 4 KiB sectors at bottom. */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_S28_SE_4K, + 0, SZ_128K); +} + +static int s28hs512t_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + struct spi_mem_op op; + u8 buf; + u8 addr_width = 3; + int ret; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + + /* + * Check CFR3V to check if non-uniform sector mode is selected. If it + * is, set the erase hook to the non-uniform erase procedure. + */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), + SPI_MEM_OP_ADDR(addr_width, + SPINOR_REG_CYPRESS_CFR3V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, &buf, 1)); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT)) + nor->erase = s28hs512t_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s28hs512t_default_init(struct spi_nor *nor) +{ + nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; + nor->setup = s28hs512t_setup; +} + +static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* + * On older versions of the flash the xSPI Profile 1.0 table has the + * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. + */ + if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) + params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = + SPINOR_OP_CYPRESS_RD_FAST; + + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; + + /* This flash is also missing the 4-byte Page Program opcode bit. */ + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], + SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); + /* + * Since xSPI Page Program opcode is backward compatible with + * Legacy SPI, use Legacy SPI opcode there as well. + */ + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], + SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); + + /* + * The xSPI Profile 1.0 table advertises the number of additional + * address bytes needed for Read Status Register command as 0 but the + * actual value for that is 4. + */ + params->rdsr_addr_nbytes = 4; +} + +static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + struct spi_mem_op op; + u8 buf; + u8 addr_width = 3; + int ret; + + /* + * The BFPT table advertises a 512B page size but the page size is + * actually configurable (with the default being 256B). Read from + * CFR3V[4] and set the correct size. + */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), + SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR3V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, &buf, 1)); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ) + params->page_size = 512; + else + params->page_size = 256; + + /* + * The BFPT advertises that it supports 4k erases, and the datasheet + * says the same. But 4k erases did not work when testing. So, use 256k + * erases for now. + */ + nor->erase_opcode = SPINOR_OP_SE_4B; + nor->mtd.erasesize = 0x40000; + + return 0; +} + +static struct spi_nor_fixups s28hs512t_fixups = { + .default_init = s28hs512t_default_init, + .post_sfdp = s28hs512t_post_sfdp_fixup, + .post_bfpt = s28hs512t_post_bfpt_fixup, +}; +#endif /* CONFIG_SPI_FLASH_S28HS512T */ + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -3108,6 +3291,10 @@ int spi_nor_remove(struct spi_nor *nor) void spi_nor_set_fixups(struct spi_nor *nor) { +#ifdef CONFIG_SPI_FLASH_S28HS512T + if (!strcmp(nor->info->name, "s28hs512t")) + nor->fixups = &s28hs512t_fixups; +#endif } int spi_nor_scan(struct spi_nor *nor) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 8d2b73b6764..bbed88a4b73 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -223,6 +223,9 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, +#ifdef CONFIG_SPI_FLASH_S28HS512T + { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, +#endif #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ /* SST -- large erase sizes are "overlays", "sectors" are 4K */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 29ce1751567..6ece401b376 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -157,6 +157,19 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* For Cypress flash. */ +#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ +#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ +#define SPINOR_OP_S28_SE_4K 0x21 +#define SPINOR_REG_CYPRESS_CFR2V 0x00800003 +#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR3V 0x00800004 +#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ +#define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */ +#define SPINOR_REG_CYPRESS_CFR5V 0x00800006 +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 +#define SPINOR_OP_CYPRESS_RD_FAST 0xee + /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK GENMASK(23, 16) #define SNOR_PROTO_INST_SHIFT 16 From f6adec1af4b2f5d3012480c6cdce7743b74a6156 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:29 +0530 Subject: [PATCH 231/250] mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode Since this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/Kconfig | 8 ++++ drivers/mtd/spi/spi-nor-core.c | 87 ++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 4 +- include/linux/mtd/spi-nor.h | 6 +++ 4 files changed, 104 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 98c0b234780..1b2ef37e92d 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -180,6 +180,14 @@ config SPI_FLASH_STMICRO help Add support for various STMicro SPI flash chips (M25Pxxx and N25Qxxx) +config SPI_FLASH_MT35XU + bool "Micron MT35XU chip support" + depends on SPI_FLASH_STMICRO + help + Add support for the Micron MT35XU chip. This is a separate config + because the fixup hooks for this flash add extra size overhead. Boards + that don't use the flash can disable this to save space. + config SPI_FLASH_SST bool "SST SPI flash support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3a1060b04b2..8dd44c0f1e1 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3148,6 +3148,88 @@ static struct spi_nor_fixups s28hs512t_fixups = { }; #endif /* CONFIG_SPI_FLASH_S28HS512T */ +#ifdef CONFIG_SPI_FLASH_MT35XU +static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 buf; + u8 addr_width = 3; + int ret; + + /* Set dummy cycles for Fast Read to the default of 20. */ + ret = write_enable(nor); + if (ret) + return ret; + + buf = 20; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), + SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + + nor->read_dummy = 20; + + ret = write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_MT_OCT_DTR; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), + SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_err(nor->dev, "Failed to enable octal DTR mode\n"); + return ret; + } + + return 0; +} + +static void mt35xu512aba_default_init(struct spi_nor *nor) +{ + nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable; +} + +static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* Set the Fast Read settings. */ + params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, SPINOR_OP_MT_DTR_RD, + SNOR_PROTO_8_8_8_DTR); + + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; + + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; + params->rdsr_dummy = 8; + params->rdsr_addr_nbytes = 0; + + /* + * The BFPT quad enable field is set to a reserved value so the quad + * enable function is ignored by spi_nor_parse_bfpt(). Make sure we + * disable it. + */ + params->quad_enable = NULL; +} + +static struct spi_nor_fixups mt35xu512aba_fixups = { + .default_init = mt35xu512aba_default_init, + .post_sfdp = mt35xu512aba_post_sfdp_fixup, +}; +#endif /* CONFIG_SPI_FLASH_MT35XU */ + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -3295,6 +3377,11 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (!strcmp(nor->info->name, "s28hs512t")) nor->fixups = &s28hs512t_fixups; #endif + +#ifdef CONFIG_SPI_FLASH_MT35XU + if (!strcmp(nor->info->name, "mt35xu512aba")) + nor->fixups = &mt35xu512aba_fixups; +#endif } int spi_nor_scan(struct spi_nor *nor) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index bbed88a4b73..59f2d3e4d6f 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -193,7 +193,9 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, - { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, +#ifdef CONFIG_SPI_FLASH_MT35XU + { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, +#endif /* CONFIG_SPI_FLASH_MT35XU */ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 6ece401b376..d68e48fd949 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -126,6 +126,12 @@ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ +#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */ +#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */ +#define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */ +#define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */ +#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ From 5e9d2833ed7973722c5ece0bc07052f5d539c680 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 24 Jun 2021 13:36:23 +0200 Subject: [PATCH 232/250] serial: Add additional depencies for PL010 and PL011 drivers Both of these drivers are implemented with and without DM that's why more symbols should be handled. The most problematic one is enabling DEBUG_UART_PL011 based on PL01X_SERIAL(DM based) because debug console has type selection based on it. enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? TYPE_PL011 : TYPE_PL010; Without it pl01x_generic_setbrg() is configuring different registers. Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6d1c4530ddf..9f82467c4e3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -332,7 +332,7 @@ config DEBUG_UART_APBUART config DEBUG_UART_PL010 bool "pl010" - depends on PL01X_SERIAL + depends on PL01X_SERIAL || PL010_SERIAL help Select this to enable a debug UART using the pl01x driver with the PL010 UART type. You will need to provide parameters to make this @@ -341,7 +341,7 @@ config DEBUG_UART_PL010 config DEBUG_UART_PL011 bool "pl011" - depends on PL011_SERIAL + depends on PL01X_SERIAL || PL011_SERIAL help Select this to enable a debug UART using the pl01x driver with the PL011 UART type. You will need to provide parameters to make this From da1af52f751993cc34abf423497f48c713d633a2 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 25 Jun 2021 20:19:11 +0900 Subject: [PATCH 233/250] serial: zynq: Add support for serial parameters This adds serial parameters that include stop bit mode, parity mode, and character length. Mark parity and space parity modes are not supported. At the moment, the only path to call setconfig directly is DM testing, however, this affects the size of SPL for DM testing, so it doesn't apply to SPL. Signed-off-by: Kunihiko Hayashi Signed-off-by: Michal Simek --- drivers/serial/serial_zynq.c | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 799d5240473..2f49f594a44 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -28,7 +28,17 @@ #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ +#define ZYNQ_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ +#define ZYNQ_UART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */ +#define ZYNQ_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ + #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ +#define ZYNQ_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ +#define ZYNQ_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ + +#define ZYNQ_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ +#define ZYNQ_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ +#define ZYNQ_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ struct uart_zynq { u32 control; /* 0x0 - Control Register [8:0] */ @@ -137,6 +147,63 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate) return 0; } +#if !defined(CONFIG_SPL_BUILD) +static int zynq_serial_setconfig(struct udevice *dev, uint serial_config) +{ + struct zynq_uart_plat *plat = dev_get_plat(dev); + struct uart_zynq *regs = plat->regs; + u32 val = 0; + + switch (SERIAL_GET_BITS(serial_config)) { + case SERIAL_6_BITS: + val |= ZYNQ_UART_MR_CHARLEN_6_BIT; + break; + case SERIAL_7_BITS: + val |= ZYNQ_UART_MR_CHARLEN_7_BIT; + break; + case SERIAL_8_BITS: + val |= ZYNQ_UART_MR_CHARLEN_8_BIT; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + switch (SERIAL_GET_STOP(serial_config)) { + case SERIAL_ONE_STOP: + val |= ZYNQ_UART_MR_STOPMODE_1_BIT; + break; + case SERIAL_ONE_HALF_STOP: + val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT; + break; + case SERIAL_TWO_STOP: + val |= ZYNQ_UART_MR_STOPMODE_2_BIT; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + switch (SERIAL_GET_PARITY(serial_config)) { + case SERIAL_PAR_NONE: + val |= ZYNQ_UART_MR_PARITY_NONE; + break; + case SERIAL_PAR_ODD: + val |= ZYNQ_UART_MR_PARITY_ODD; + break; + case SERIAL_PAR_EVEN: + val |= ZYNQ_UART_MR_PARITY_EVEN; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + writel(val, ®s->mode); + + return 0; +} +#else +#define zynq_serial_setconfig NULL +#endif + static int zynq_serial_probe(struct udevice *dev) { struct zynq_uart_plat *plat = dev_get_plat(dev); @@ -198,6 +265,7 @@ static const struct dm_serial_ops zynq_serial_ops = { .pending = zynq_serial_pending, .getc = zynq_serial_getc, .setbrg = zynq_serial_setbrg, + .setconfig = zynq_serial_setconfig, }; static const struct udevice_id zynq_serial_ids[] = { From 215f2064c365ffc2b9fad65248fee7bcf70f92b1 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 24 Jun 2021 00:34:40 -0600 Subject: [PATCH 234/250] net: xilinx: axi_emac: Cleanup of of_to_plat() There are lot of accesses to priv data in of_to_plat(), which is incorrect. Create a platform data structure and use it in of_to_plat(), then copy all platform data to priv data in probe. Signed-off-by: Ashok Reddy Soma Reviewed-by: Ramon Fried Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 47 ++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 2ce6271afe8..cfc60824756 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -87,6 +87,16 @@ struct axidma_reg { u32 tail_hi; /* TAILDESC high 32 bit */ }; +/* Platform data structures */ +struct axidma_plat { + struct eth_pdata eth_pdata; + struct axidma_reg *dmatx; + struct axidma_reg *dmarx; + int phyaddr; + u8 eth_hasnobuf; + int phy_of_handle; +}; + /* Private driver structures */ struct axidma_priv { struct axidma_reg *dmatx; @@ -690,9 +700,20 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, static int axi_emac_probe(struct udevice *dev) { + struct axidma_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; struct axidma_priv *priv = dev_get_priv(dev); int ret; + priv->iobase = (struct axi_regs *)pdata->iobase; + priv->dmatx = plat->dmatx; + /* RX channel offset is 0x30 */ + priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); + priv->eth_hasnobuf = plat->eth_hasnobuf; + priv->phyaddr = plat->phyaddr; + priv->phy_of_handle = plat->phy_of_handle; + priv->interface = pdata->phy_interface; + priv->bus = mdio_alloc(); priv->bus->read = axiemac_miiphy_read; priv->bus->write = axiemac_miiphy_write; @@ -729,14 +750,13 @@ static const struct eth_ops axi_emac_ops = { static int axi_emac_of_to_plat(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_plat(dev); - struct axidma_priv *priv = dev_get_priv(dev); + struct axidma_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; int node = dev_of_offset(dev); int offset = 0; const char *phy_mode; pdata->iobase = dev_read_addr(dev); - priv->iobase = (struct axi_regs *)pdata->iobase; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "axistream-connected"); @@ -744,21 +764,19 @@ static int axi_emac_of_to_plat(struct udevice *dev) printf("%s: axistream is not found\n", __func__); return -EINVAL; } - priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, + plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, offset, "reg"); - if (!priv->dmatx) { + if (!plat->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; } - /* RX channel offset is 0x30 */ - priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); - priv->phyaddr = -1; + plat->phyaddr = -1; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); if (offset > 0) { - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); - priv->phy_of_handle = offset; + plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + plat->phy_of_handle = offset; } phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); @@ -768,13 +786,12 @@ static int axi_emac_of_to_plat(struct udevice *dev) printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } - priv->interface = pdata->phy_interface; - priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, + plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,eth-hasnobuf"); - printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, - priv->phyaddr, phy_string_for_interface(priv->interface)); + printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, + plat->phyaddr, phy_string_for_interface(pdata->phy_interface)); return 0; } @@ -793,5 +810,5 @@ U_BOOT_DRIVER(axi_emac) = { .remove = axi_emac_remove, .ops = &axi_emac_ops, .priv_auto = sizeof(struct axidma_priv), - .plat_auto = sizeof(struct eth_pdata), + .plat_auto = sizeof(struct axidma_plat), }; From 53b2af18ca732993494c8de3a05a3a30e7a28559 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 24 Jun 2021 00:34:41 -0600 Subject: [PATCH 235/250] net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet Add support for 10G/25G (XXV) high speed ethernet. This Makes use of the exiting AXI DMA, similar to 1G. Signed-off-by: Alessandro Temil Signed-off-by: Ashok Reddy Soma Reviewed-by: Ramon Fried Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 164 ++++++++++++++++++++++++---------- 1 file changed, 119 insertions(+), 45 deletions(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index cfc60824756..2ec76d0f52d 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2021 Waymo LLC * Copyright (C) 2011 Michal Simek * Copyright (C) 2011 PetaLogix * Copyright (C) 2010 Xilinx, Inc. All rights reserved. @@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR; #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ -#define DMAALIGN 128 +/* Bitmasks for XXV Ethernet MAC */ +#define XXV_TC_TX_MASK 0x00000001 +#define XXV_TC_FCS_MASK 0x00000002 +#define XXV_RCW1_RX_MASK 0x00000001 +#define XXV_RCW1_FCS_MASK 0x00000002 + +#define DMAALIGN 128 +#define XXV_MIN_PKT_SIZE 60 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); +static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN))); + +enum emac_variant { + EMAC_1G = 0, + EMAC_10G_25G = 1, +}; /* Reflect dma offsets */ struct axidma_reg { @@ -95,6 +109,7 @@ struct axidma_plat { int phyaddr; u8 eth_hasnobuf; int phy_of_handle; + enum emac_variant mactype; }; /* Private driver structures */ @@ -108,6 +123,7 @@ struct axidma_priv { struct mii_dev *bus; u8 eth_hasnobuf; int phy_of_handle; + enum emac_variant mactype; }; /* BD descriptors */ @@ -154,6 +170,14 @@ struct axi_regs { u32 uaw1; /* 0x704: Unicast address word 1 */ }; +struct xxv_axi_regs { + u32 gt_reset; /* 0x0 */ + u32 reserved[2]; + u32 tc; /* 0xC: Tx Configuration */ + u32 reserved2; + u32 rcw1; /* 0x14: Rx Configuration Word 1 */ +}; + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -385,6 +409,18 @@ static void axiemac_stop(struct udevice *dev) debug("axiemac: Halted\n"); } +static int xxv_axi_ethernet_init(struct axidma_priv *priv) +{ + struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; + + writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1); + writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc); + writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); + writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); + + return 0; +} + static int axi_ethernet_init(struct axidma_priv *priv) { struct axi_regs *regs = priv->iobase; @@ -440,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev) struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; + if (priv->mactype != EMAC_1G) + return 0; + /* Set the MAC address */ int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); @@ -477,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv) static int axiemac_start(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); - struct axi_regs *regs = priv->iobase; u32 temp; debug("axiemac: Init started\n"); @@ -490,8 +528,13 @@ static int axiemac_start(struct udevice *dev) axi_dma_init(priv); /* Initialize AxiEthernet hardware. */ - if (axi_ethernet_init(priv)) - return -1; + if (priv->mactype == EMAC_1G) { + if (axi_ethernet_init(priv)) + return -1; + } else { + if (xxv_axi_ethernet_init(priv)) + return -1; + } /* Disable all RX interrupts before RxBD space setup */ temp = readl(&priv->dmarx->control); @@ -525,15 +568,25 @@ static int axiemac_start(struct udevice *dev) /* Rx BD is ready - start */ axienet_dma_write(&rx_bd, &priv->dmarx->tail); - /* Enable TX */ - writel(XAE_TC_TX_MASK, ®s->tc); - /* Enable RX */ - writel(XAE_RCW1_RX_MASK, ®s->rcw1); + if (priv->mactype == EMAC_1G) { + struct axi_regs *regs = priv->iobase; + /* Enable TX */ + writel(XAE_TC_TX_MASK, ®s->tc); + /* Enable RX */ + writel(XAE_RCW1_RX_MASK, ®s->rcw1); - /* PHY setup */ - if (!setup_phy(dev)) { - axiemac_stop(dev); - return -1; + /* PHY setup */ + if (!setup_phy(dev)) { + axiemac_stop(dev); + return -1; + } + } else { + struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; + /* Enable TX */ + writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); + + /* Enable RX */ + writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); } debug("axiemac: Init complete\n"); @@ -548,6 +601,14 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) if (len > PKTSIZE_ALIGN) len = PKTSIZE_ALIGN; + /* If size is less than min packet size, pad to min size */ + if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) { + memset(txminframe, 0, XXV_MIN_PKT_SIZE); + memcpy(txminframe, ptr, len); + len = XXV_MIN_PKT_SIZE; + ptr = txminframe; + } + /* Flush packet to main memory to be trasfered by DMA */ flush_cache((phys_addr_t)ptr, len); @@ -632,7 +693,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) temp = readl(&priv->dmarx->control); temp &= ~XAXIDMA_IRQ_ALL_MASK; writel(temp, &priv->dmarx->control); - if (!priv->eth_hasnobuf) + if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G) length = rx_bd.app4 & 0xFFFF; /* max length mask */ else length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; @@ -709,21 +770,25 @@ static int axi_emac_probe(struct udevice *dev) priv->dmatx = plat->dmatx; /* RX channel offset is 0x30 */ priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); - priv->eth_hasnobuf = plat->eth_hasnobuf; - priv->phyaddr = plat->phyaddr; - priv->phy_of_handle = plat->phy_of_handle; - priv->interface = pdata->phy_interface; + priv->mactype = plat->mactype; - priv->bus = mdio_alloc(); - priv->bus->read = axiemac_miiphy_read; - priv->bus->write = axiemac_miiphy_write; - priv->bus->priv = priv; + if (priv->mactype == EMAC_1G) { + priv->eth_hasnobuf = plat->eth_hasnobuf; + priv->phyaddr = plat->phyaddr; + priv->phy_of_handle = plat->phy_of_handle; + priv->interface = pdata->phy_interface; - ret = mdio_register_seq(priv->bus, dev_seq(dev)); - if (ret) - return ret; + priv->bus = mdio_alloc(); + priv->bus->read = axiemac_miiphy_read; + priv->bus->write = axiemac_miiphy_write; + priv->bus->priv = priv; - axiemac_phy_init(dev); + ret = mdio_register_seq(priv->bus, dev_seq(dev)); + if (ret) + return ret; + + axiemac_phy_init(dev); + } return 0; } @@ -732,9 +797,11 @@ static int axi_emac_remove(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); - free(priv->phydev); - mdio_unregister(priv->bus); - mdio_free(priv->bus); + if (priv->mactype == EMAC_1G) { + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + } return 0; } @@ -757,6 +824,7 @@ static int axi_emac_of_to_plat(struct udevice *dev) const char *phy_mode; pdata->iobase = dev_read_addr(dev); + plat->mactype = dev_get_driver_data(dev); offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "axistream-connected"); @@ -771,25 +839,30 @@ static int axi_emac_of_to_plat(struct udevice *dev) return -EINVAL; } - plat->phyaddr = -1; + if (plat->mactype == EMAC_1G) { + plat->phyaddr = -1; - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); - if (offset > 0) { - plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); - plat->phy_of_handle = offset; + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + if (offset > 0) { + plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, + "reg", -1); + plat->phy_of_handle = offset; + } + + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + printf("%s: Invalid PHY interface '%s'\n", __func__, + phy_mode); + return -EINVAL; + } + + plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, + "xlnx,eth-hasnobuf"); } - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); - if (phy_mode) - pdata->phy_interface = phy_get_interface_by_name(phy_mode); - if (pdata->phy_interface == -1) { - printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); - return -EINVAL; - } - - plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, - "xlnx,eth-hasnobuf"); - printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, plat->phyaddr, phy_string_for_interface(pdata->phy_interface)); @@ -797,7 +870,8 @@ static int axi_emac_of_to_plat(struct udevice *dev) } static const struct udevice_id axi_emac_ids[] = { - { .compatible = "xlnx,axi-ethernet-1.00.a" }, + { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G }, + { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G }, { } }; From 436978b1d8900b66ad168c55a94a3f5f92d7da3c Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Mon, 21 Jun 2021 10:11:27 +0530 Subject: [PATCH 236/250] arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for zc1751-xm017-dc3 board. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index a9bac1dec03..344323ab7f9 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -11,6 +11,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include / { model = "ZynqMP zc1751-xm017-dc3 RevA"; @@ -37,6 +38,18 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + clock_si5338_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_si5338_3: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; }; &fpd_dma_chan1 { @@ -166,6 +179,13 @@ }; }; +&psgtr { + status = "okay"; + /* usb3, sata */ + clocks = <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref2", "ref3"; +}; + &rtc { status = "okay"; }; @@ -181,6 +201,8 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 2 PHY_TYPE_SATA 0 3>; }; &sdhci1 { /* emmc with some settings */ @@ -205,6 +227,8 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 0 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; @@ -217,5 +241,7 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; maximum-speed = "super-speed"; }; From c32bfe0cd9bb0d72cbce990b8676367c6236a621 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:00:56 +0900 Subject: [PATCH 237/250] mtd: spi-nor: Add Cypress manufacturer ID This patch adds Cypress manufacturer ID (34h) definition. Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki --- include/linux/mtd/spi-nor.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d68e48fd949..95ea6eb27a6 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -27,6 +27,7 @@ #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ +#define SNOR_MFR_CYPRESS 0x34 /* * Note on opcode nomenclature: some opcodes have a format like From c95a914aed7d8025b3877b04272aecf4e1b56ea4 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:00:57 +0900 Subject: [PATCH 238/250] mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable sector architecture. By default, the 512Mb and 1Gb, single-die package parts are configured to non-uniform that 4KB sectors overlaid on bottom address. To support this, an erase hook makes overlaid sectors appear as uniform sectors. The 2Gb, dual-die package parts are configured to uniform by default. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-ids.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 59f2d3e4d6f..1af1c864868 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -225,6 +225,22 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_S28HS512T { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, #endif From 2d20f344858265722452d06fe7a5f86ca736b86d Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:00:58 +0900 Subject: [PATCH 239/250] mtd: spi-nor-core: Add support for Read/Write Any Register Some of Spansion/Cypress chips support Read/Write Any Register commands. These commands are mainly used to write volatile registers and access to the registers in second and subsequent die for multi-die package parts. The Read Any Register instruction (65h) is followed by register address and dummy cycles, then the selected register byte is returned. The Write Any Register instruction (71h) is followed by register address and register byte to write. Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 25 +++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8dd44c0f1e1..9e85f7d73e0 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -315,6 +315,31 @@ static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) return spi_nor_read_write_reg(nor, &op, buf); } +#ifdef CONFIG_SPI_FLASH_SPANSION +static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, + u8 *val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_DUMMY(dummy / 8, 1), + SPI_MEM_OP_DATA_IN(1, NULL, 1)); + + return spi_nor_read_write_reg(nor, &op, val); +} + +static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, NULL, 1)); + + return spi_nor_read_write_reg(nor, &op, &val); +} +#endif + static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u_char *buf) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 95ea6eb27a6..5bb06882ea5 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -123,6 +123,8 @@ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_RDAR 0x65 /* Read any register */ +#define SPINOR_OP_WRAR 0x71 /* Write any register */ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ From a4aa9b7522dc67745795c1e2a76115a616da00ea Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:00:59 +0900 Subject: [PATCH 240/250] mtd: spi-nor-core: Add support for volatile QE bit Some of Spansion/Cypress chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. This patch adds a function to set Quad Enable bit in CFR1 volatile. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 55 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 56 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9e85f7d73e0..2b72d65b0ab 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1711,6 +1711,61 @@ static int macronix_quad_enable(struct spi_nor *nor) } #endif +#ifdef CONFIG_SPI_FLASH_SPANSION +/** + * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register. + * @nor: pointer to a 'struct spi_nor' + * @addr_base: base address of register (can be >0 in multi-die parts) + * @dummy: number of dummy cycles for register read + * + * It is recommended to update volatile registers in the field application due + * to a risk of the non-volatile registers corruption by power interrupt. This + * function sets Quad Enable bit in CFR1 volatile. + * + * Return: 0 on success, -errno otherwise. + */ +static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base, + u8 dummy) +{ + u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V; + + u8 cr; + int ret; + + /* Check current Quad Enable bit value. */ + ret = spansion_read_any_reg(nor, addr, dummy, &cr); + if (ret < 0) { + dev_dbg(nor->dev, + "error while reading configuration register\n"); + return -EINVAL; + } + + if (cr & CR_QUAD_EN_SPAN) + return 0; + + cr |= CR_QUAD_EN_SPAN; + + write_enable(nor); + + ret = spansion_write_any_reg(nor, addr, cr); + + if (ret < 0) { + dev_dbg(nor->dev, + "error while writing configuration register\n"); + return -EINVAL; + } + + /* Read back and check it. */ + ret = spansion_read_any_reg(nor, addr, dummy, &cr); + if (ret || !(cr & CR_QUAD_EN_SPAN)) { + dev_dbg(nor->dev, "Spansion Quad bit not set\n"); + return -EINVAL; + } + + return 0; +} +#endif + #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /* * Write status Register and configuration register with 2 bytes diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 5bb06882ea5..81df05fe841 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -125,6 +125,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_CFR1V 0x00800002 /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ From 24b1e2c690fb953a3a981a282e37de5a0f1a98b1 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:01:00 +0900 Subject: [PATCH 241/250] mtd: spi-nor-core: Add the ->ready() hook For dual/quad die package devices from Spansion/Cypress, the device's status needs to be checked by reading status registers in all dies, by using Read Any Register command. To support this, a Flash specific hook that can overwrite the legacy status check is needed. Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 10 +++++++++- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2b72d65b0ab..d953c7e44fe 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -713,7 +713,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) return fsr & FSR_READY; } -static int spi_nor_ready(struct spi_nor *nor) +static int spi_nor_default_ready(struct spi_nor *nor) { int sr, fsr; @@ -726,6 +726,14 @@ static int spi_nor_ready(struct spi_nor *nor) return sr && fsr; } +static int spi_nor_ready(struct spi_nor *nor) +{ + if (nor->ready) + return nor->ready(nor); + + return spi_nor_default_ready(nor); +} + /* * Service routine to read status register until ready, or timeout occurs. * Returns non-zero if error. diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 81df05fe841..e579ff2c7e5 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -504,6 +504,7 @@ struct spi_flash { * completely locked * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode. + * @ready: [FLASH-SPECIFIC] check if the flash is ready * @priv: the private data */ struct spi_nor { @@ -552,6 +553,7 @@ struct spi_nor { int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*quad_enable)(struct spi_nor *nor); int (*octal_dtr_enable)(struct spi_nor *nor); + int (*ready)(struct spi_nor *nor); void *priv; /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ From d2d79895da1b80275fe0ffd84d697519c73c924d Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:01:01 +0900 Subject: [PATCH 242/250] mtd: spi-nor-core: Read status by Read Any Register The spansion_sr_ready() reads status register 1 by Read Any Register commnad. This function is called from Flash specific hook with die address and dummy cycles to support multi-die package parts from Spansion/Cypress. Signed-off-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 29 +++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d953c7e44fe..7f1ed1bb366 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -669,6 +669,35 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, } } +#ifdef CONFIG_SPI_FLASH_SPANSION +/* + * Read status register 1 by using Read Any Register command to support multi + * die package parts. + */ +static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy) +{ + u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V; + u8 sr; + int ret; + + ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr); + if (ret < 0) + return ret; + + if (sr & (SR_E_ERR | SR_P_ERR)) { + if (sr & SR_E_ERR) + dev_dbg(nor->dev, "Erase Error occurred\n"); + else + dev_dbg(nor->dev, "Programming Error occurred\n"); + + nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); + return -EIO; + } + + return !(sr & SR_WIP); +} +#endif + static int spi_nor_sr_ready(struct spi_nor *nor) { int sr = read_sr(nor); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e579ff2c7e5..b9d66458a06 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -125,6 +125,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_STR1V 0x00800000 #define SPINOR_REG_ADDR_CFR1V 0x00800002 /* Used for Micron flashes only. */ From 72151ad10f8dcc3c86084259b227a7d70cc79473 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:01:02 +0900 Subject: [PATCH 243/250] mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode. Cypress chips support B8h to disable 4-byte addressing mode instead of SPINOR_OP_EX4B(E9h). This patch defines new opcode and updates set_4byte() to support enable/disable 4-byte addressing mode for Cypress chips. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 3 +++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 7f1ed1bb366..94dfa97110a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -662,6 +662,9 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, } return status; + case SNOR_MFR_CYPRESS: + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS; + return nor->write_reg(nor, cmd, NULL, 0); default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b9d66458a06..6df82bde942 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -123,6 +123,7 @@ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ #define SPINOR_REG_ADDR_STR1V 0x00800000 From 1c3dd193b5ba76da9d5b2b422d04605321a91c94 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:01:03 +0900 Subject: [PATCH 244/250] mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t The nor->ready() and spansion_sr_ready() introduced earlier in this series are used for multi-die package parts. The nor->quad_enable() sets the volatile QE bit on each die. The nor->erase() is hooked if the device is not configured to uniform sectors, assuming it has 32 x 4KB sectors overlaid on bottom address. Other configurations, top and split, are not supported at this point. Will submit additional patches to support it as needed. The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 144 ++++++++++++++++++++++++++++++++- include/linux/mtd/spi-nor.h | 3 + 2 files changed, 146 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 94dfa97110a..99e2f16349a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -952,7 +952,7 @@ erase_err: return ret; } -#ifdef CONFIG_SPI_FLASH_S28HS512T +#ifdef CONFIG_SPI_FLASH_SPANSION /** * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress * chips @@ -3085,6 +3085,134 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return nor->setup(nor, info, params); } +#ifdef CONFIG_SPI_FLASH_SPANSION +static int s25hx_t_mdp_ready(struct spi_nor *nor) +{ + u32 addr; + int ret; + + for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { + ret = spansion_sr_ready(nor, addr, 0); + if (!ret) + return ret; + } + + return 1; +} + +static int s25hx_t_quad_enable(struct spi_nor *nor) +{ + u32 addr; + int ret; + + for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { + ret = spansion_quad_enable_volatile(nor, addr, 0); + if (ret) + return ret; + } + + return 0; +} + +static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 32 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, + SZ_128K); +} + +static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + +#ifdef CONFIG_SPI_FLASH_BAR + return -ENOTSUPP; /* Bank Address Register is not supported */ +#endif + /* + * Read CFR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25hx_t_erase_non_uniform; + + /* + * For the multi-die package parts, the ready() hook is needed to check + * all dies' status via read any register. + */ + if (nor->mtd.size > SZ_128M) + nor->ready = s25hx_t_mdp_ready; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25hx_t_default_init(struct spi_nor *nor) +{ + nor->setup = s25hx_t_setup; +} + +static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + int ret; + u32 addr; + u8 cfr3v; + + /* erase size in case it is set to 4K from BFPT */ + nor->erase_opcode = SPINOR_OP_SE_4B; + nor->mtd.erasesize = nor->info->sector_size; + + ret = set_4byte(nor, nor->info, 1); + if (ret) + return ret; + nor->addr_width = 4; + + /* + * The page_size is set to 512B from BFPT, but it actually depends on + * the configuration register. Look up the CFR3V and determine the + * page_size. For multi-die package parts, use 512B only when the all + * dies are configured to 512B buffer. + */ + for (addr = 0; addr < params->size; addr += SZ_128M) { + ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V, + 0, &cfr3v); + if (ret) + return ret; + + if (!(cfr3v & CFR3V_PGMBUF)) { + params->page_size = 256; + return 0; + } + } + params->page_size = 512; + + return 0; +} + +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_FAST_4B (0Ch) requires mode cycles*/ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25hx_t_quad_enable; +} + +static struct spi_nor_fixups s25hx_t_fixups = { + .default_init = s25hx_t_default_init, + .post_bfpt = s25hx_t_post_bfpt_fixup, + .post_sfdp = s25hx_t_post_sfdp_fixup, +}; +#endif + #ifdef CONFIG_SPI_FLASH_S28HS512T /** * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes. @@ -3493,6 +3621,20 @@ int spi_nor_remove(struct spi_nor *nor) void spi_nor_set_fixups(struct spi_nor *nor) { +#ifdef CONFIG_SPI_FLASH_SPANSION + if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) { + switch (nor->info->id[1]) { + case 0x2a: /* S25HL (QSPI, 3.3V) */ + case 0x2b: /* S25HS (QSPI, 1.8V) */ + nor->fixups = &s25hx_t_fixups; + break; + + default: + break; + } + } +#endif + #ifdef CONFIG_SPI_FLASH_S28HS512T if (!strcmp(nor->info->name, "s28hs512t")) nor->fixups = &s28hs512t_fixups; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 6df82bde942..7ddc4ba2bf2 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -128,6 +128,9 @@ #define SPINOR_OP_WRAR 0x71 /* Write any register */ #define SPINOR_REG_ADDR_STR1V 0x00800000 #define SPINOR_REG_ADDR_CFR1V 0x00800002 +#define SPINOR_REG_ADDR_CFR3V 0x00800004 +#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ +#define CFR3V_PGMBUF BIT(4) /* Program buffer size */ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ From 5b8ec59e2a219185127fcaa640c2f5d5aba3acd6 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Tue, 29 Jun 2021 15:01:04 +0900 Subject: [PATCH 245/250] mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny. Signed-off-by: Takahiro Kuwano Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-tiny.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 70061f1a617..68152ce3b4b 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -583,6 +583,12 @@ static int spi_nor_init_params(struct spi_nor *nor, spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1); +#ifdef CONFIG_SPI_FLASH_SPANSION + if (JEDEC_MFR(info) == SNOR_MFR_CYPRESS && + (info->id[1] == 0x2a || info->id[1] == 0x2b)) + /* 0x2a: S25HL (QSPI, 3.3V), 0x2b: S25HS (QSPI, 1.8V) */ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; +#endif } if (info->flags & SPI_NOR_QUAD_READ) { From 6e257c69fb6fc72f345586bb8309371b09757618 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 28 Jun 2021 11:18:43 +0200 Subject: [PATCH 246/250] arm64: zynqmp: Enable WDT command Enable watchdog command to be able to work with watchdogs. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index dc5778fb470..d7239835c6a 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -54,6 +54,7 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y From 76bf8f3e44813bb6f5e57860dbfe51aa27ea5e91 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 28 Jun 2021 13:44:16 +0200 Subject: [PATCH 247/250] watchdog: cadence: Add expire_now method It is working in a way that only minimal timeout is setup to reach expiration just right after it is setup. Please make sure that PMUFW is compiled with ENABLE_EM flag. On U-Boot prompt you can test it like: ZynqMP> wdt dev watchdog@fd4d0000 ZynqMP> wdt list watchdog@fd4d0000 (cdns_wdt) ZynqMP> wdt dev dev: watchdog@fd4d0000 ZynqMP> wdt expire (And reset should happen here) Signed-off-by: Michal Simek --- drivers/watchdog/cdns_wdt.c | 41 ++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 966d010e40d..6dfdd31c8b8 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -214,6 +214,45 @@ static int cdns_wdt_stop(struct udevice *dev) return 0; } +/** + * cdns_wdt_expire_now - Expire the watchdog. + * + * @dev: Watchdog device + * @flags: Driver flags + * + * Access WDT and configure with minimal counter value to expire ASAP. + * Expiration issues system reset. When DEBUG is enabled count should be + * bigger to at least see debug message. + * + * Return: Always 0 + */ +static int cdns_wdt_expire_now(struct udevice *dev, ulong flags) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + u32 data, count = 0; + +#if defined(DEBUG) + count = 0x40; /* Increase the value if you need more time */ + debug("%s: Expire wdt%u\n", __func__, dev_seq(dev)); +#endif + + cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL); + + count = (count << 2) & CDNS_WDT_CCR_CRV_MASK; + + /* Write counter access key first to be able write to register */ + data = count | CDNS_WDT_REGISTER_ACCESS_KEY; + cdns_wdt_writereg(&priv->regs->ccr, data); + + data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTEN_MASK | + CDNS_WDT_ZMR_ZKEY_VAL; + + cdns_wdt_writereg(&priv->regs->zmr, data); + cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); + + return 0; +} + /** * cdns_wdt_probe - Probe call for the device. * @@ -247,7 +286,7 @@ static const struct wdt_ops cdns_wdt_ops = { .start = cdns_wdt_start, .reset = cdns_wdt_reset, .stop = cdns_wdt_stop, - /* There is no bit/reg/support in IP for expire_now functionality */ + .expire_now = cdns_wdt_expire_now, }; static const struct udevice_id cdns_wdt_ids[] = { From 45576273e9209309238f332c85a6fef955c49b59 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 13 May 2021 07:13:25 -0600 Subject: [PATCH 248/250] xilinx: zynqmp: Add support for 67dr silicon Add zynqmp 67dr silicon to zynqmp device id table. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 7177c5a5a89..1748fec2e4d 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -185,6 +185,11 @@ static const struct { .device = 49, .variants = ZYNQMP_VARIANT_DR, }, + { + .id = 0x046d0093, + .device = 67, + .variants = ZYNQMP_VARIANT_DR, + }, }; static const struct { From ef0f4e834c6634b4ef5ae6117c74c58db4e7c1c0 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 18 May 2021 11:19:46 +0200 Subject: [PATCH 249/250] build_bug.h: add wrapper for _Static_assert [Linux commit 6bab69c65013bed5fce9f101a64a84d0385b3946] BUILD_BUG_ON() is a little annoying, since it cannot be used outside function scope. So one cannot put assertions about the sizeof() a struct next to the struct definition, but has to hide that in some more or less arbitrary function. Since gcc 4.6 (which is now also the required minimum), there is support for the C11 _Static_assert in all C modes, including gnu89. So add a simple wrapper for that. _Static_assert() requires a message argument, which is usually quite redundant (and I believe that bug got fixed at least in newer C++ standards), but we can easily work around that with a little macro magic, making it optional. For example, adding static_assert(sizeof(struct printf_spec) == 8); in vsprintf.c and modifying that struct to violate it, one gets ./include/linux/build_bug.h:78:41: error: static assertion failed: "sizeof(struct printf_spec) == 8" #define __static_assert(expr, msg, ...) _Static_assert(expr, "" msg "") godbolt.org suggests that _Static_assert() has been support by clang since at least 3.0.0. Signed-off-by: Rasmus Villemoes Reviewed-by: Simon Glass --- include/linux/build_bug.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index b7d22d60008..9c7088bafa4 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -79,6 +79,25 @@ */ #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") +/** + * static_assert - check integer constant expression at build time + * + * static_assert() is a wrapper for the C11 _Static_assert, with a + * little macro magic to make the message optional (defaulting to the + * stringification of the tested expression). + * + * Contrary to BUILD_BUG_ON(), static_assert() can be used at global + * scope, but requires the expression to be an integer constant + * expression (i.e., it is not enough that __builtin_constant_p() is + * true for expr). + * + * Also note that BUILD_BUG_ON() fails the build if the condition is + * true, while static_assert() fails the build if the expression is + * false. + */ +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg) + #endif /* __CHECKER__ */ #endif /* _LINUX_BUILD_BUG_H */ From ee3a46a437315cbbbc746890c2cf8eea5dd7f1e7 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 18 May 2021 11:19:47 +0200 Subject: [PATCH 250/250] global-data.h: add build-time sanity check of sizeof(struct global_data) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The layout and contents of struct global_data depends on a lot of CONFIG_* preprocessor macros, not all of which are entirely converted to Kconfig - not to mention weird games played here and there. This can result in one translation unit using one definition of struct global_data while the actual layout is another. That can be very hard to debug. But we already have a mechanism that can help catch such bugs at build time, namely the asm-offsets machinery which is necessary anyway to provide assembly code with the necessary constants. So make sure that every C translation unit that include global_data.h actually sees the same size of struct global_data as that which was seen by the asm-offsets.c TU. It is likely that this patch will break the build of some boards. For example, without the patch from Matt Merhar (https://lists.denx.de/pipermail/u-boot/2021-May/450135.html) or some other fix, this breaks P2041RDB_defconfig: CC arch/powerpc/lib/traps.o AS arch/powerpc/cpu/mpc85xx/start.o In file included from include/asm-generic/global_data.h:26, from ./arch/powerpc/include/asm/global_data.h:109, from include/init.h:21, from arch/powerpc/lib/traps.c:7: include/linux/build_bug.h:99:41: error: static assertion failed: "sizeof(struct global_data) == GD_SIZE" 99 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) | ^~~~~~~~~~~~~~ include/linux/build_bug.h:98:34: note: in expansion of macro ‘__static_assert’ 98 | #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) | ^~~~~~~~~~~~~~~ include/asm-generic/global_data.h:470:1: note: in expansion of macro ‘static_assert’ 470 | static_assert(sizeof(struct global_data) == GD_SIZE); | ^~~~~~~~~~~~~ make[1]: *** [scripts/Makefile.build:266: arch/powerpc/lib/traps.o] Error 1 make: *** [Makefile:1753: arch/powerpc/lib] Error 2 make: *** Waiting for unfinished jobs.... Signed-off-by: Rasmus Villemoes Reviewed-by: Simon Glass --- include/asm-generic/global_data.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e278d4c9413..5fed4db23f1 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -23,6 +23,8 @@ #include #include #include +#include +#include struct acpi_ctx; struct driver_rt; @@ -464,6 +466,9 @@ struct global_data { char *smbios_version; #endif }; +#ifndef DO_DEPS_ONLY +static_assert(sizeof(struct global_data) == GD_SIZE); +#endif /** * gd_board_type() - retrieve board type