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[INKA4x0] NG hardware: SDRAM support
Add support for three new DDR chips that may be present on a NG INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT. Cleanup board/inka4x0/mt48lc16m16a2-75.h file. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
This commit is contained in:
Marian Balakowicz
parent
f23cb34c36
commit
5fb6d7191e
32
board/inka4x0/hyb25d512160bf-5.h
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32
board/inka4x0/hyb25d512160bf-5.h
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@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2007 Semihalf
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* Written by Marian Balakowicz <m8@semihalf.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define SDRAM_DDR 1 /* is DDR */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714F0F00
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#define SDRAM_CONFIG1 0x73711930
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#define SDRAM_CONFIG2 0x46770000
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#define SDRAM_TAPDELAY 0x10000000
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@ -31,10 +31,18 @@
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#include <mpc5xxx.h>
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#include <pci.h>
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#if defined(CONFIG_MPC5200_DDR)
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#if defined(CONFIG_DDR_MT46V16M16)
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#include "mt46v16m16-75.h"
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#else
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#elif defined(CONFIG_SDR_MT48LC16M16A2)
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#include "mt48lc16m16a2-75.h"
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#elif defined(CONFIG_DDR_MT46V32M16)
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#include "mt46v32m16.h"
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#elif defined(CONFIG_DDR_HYB25D512160BF)
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#include "hyb25d512160bf.h"
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#elif defined(CONFIG_DDR_K4H511638C)
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#include "k4h511638c.h"
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#else
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#error "INKA4x0 SDRAM: invalid chip type specified!"
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#endif
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#ifndef CFG_RAMBOOT
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32
board/inka4x0/k4h511638c.h
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32
board/inka4x0/k4h511638c.h
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@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2007 Semihalf
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* Written by Marian Balakowicz <m8@semihalf.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define SDRAM_DDR 1 /* is DDR */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714F0F00
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#define SDRAM_CONFIG1 0x73722930
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#define SDRAM_CONFIG2 0x46770000
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#define SDRAM_TAPDELAY 0x10000000
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@ -23,15 +23,10 @@
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#define SDRAM_DDR 1 /* is DDR */
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#if defined(CONFIG_MPC5200)
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714f0f00
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#define SDRAM_CONTROL 0x714F0F00
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#define SDRAM_CONFIG1 0x73722930
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#define SDRAM_CONFIG2 0x47770000
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#define SDRAM_TAPDELAY 0x10000000
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#else
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#error CONFIG_MPC5200 not defined
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#endif
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32
board/inka4x0/mt46v32m16-75.h
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32
board/inka4x0/mt46v32m16-75.h
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@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2007 Semihalf
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* Written by Marian Balakowicz <m8@semihalf.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define SDRAM_DDR 1 /* is DDR */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714F0F00
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#define SDRAM_CONFIG1 0x73711930
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#define SDRAM_CONFIG2 0x46770000
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#define SDRAM_TAPDELAY 0x10000000
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@ -21,27 +21,10 @@
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* MA 02111-1307 USA
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*/
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#define SDRAM_DDR 1 /* is SDR */
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#define SDRAM_DDR 0 /* is SDR */
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#if defined(CONFIG_MPC5200)
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x00CD0000
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/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
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#define SDRAM_CONTROL 0x504F0000
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#define SDRAM_CONFIG1 0xD2322800
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/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
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/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
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#define SDRAM_CONFIG2 0x8AD70000
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/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
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#elif defined(CONFIG_MGT5100)
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/* Settings for XLB = 66 MHz */
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#define SDRAM_MODE 0x008D0000
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#define SDRAM_CONTROL 0x504F0000
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#define SDRAM_CONFIG1 0xC2222600
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#define SDRAM_CONFIG2 0x88B70004
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#define SDRAM_ADDRSEL 0x02000000
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#else
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#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
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#endif
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@ -183,7 +183,14 @@
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#define CONFIG_MPC5200_DDR
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/*
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* SDRAM controller configuration
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*/
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#undef CONFIG_SDR_MT48LC16M16A2
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#undef CONFIG_DDR_MT46V16M16
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#undef CONFIG_DDR_MT46V32M16
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#undef CONFIG_DDR_HYB25D512160BF
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#define CONFIG_DDR_K4H511638C
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/* Use ON-Chip SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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