mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-12-02 17:13:28 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot

Browse Source 
Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic 2021-10-21 13:57:38 +02:00
commit 5fac11e6d5
631 changed files with 10852 additions and 5820 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.azure-pipelines.yml
View File

@ -2,7 +2,7 @@ variables:
windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@ -183,7 +183,7 @@ jobs:
TEST_PY_BD: "sandbox"
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-12"
OVERRIDE: "-O clang-13"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"

4
.gitlab-ci.yml
View File

@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021
image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021
# We run some tests in different order, to catch some failures quicker.
stages:
@ -190,7 +190,7 @@ sandbox test.py:
sandbox with clang test.py:
variables:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-12"
OVERRIDE: "-O clang-13"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:

2
MAINTAINERS
View File

@ -756,6 +756,7 @@ F: include/fdt*
F: include/linux/libfdt*
F: cmd/fdt.c
F: common/fdt_support.c
F: scripts/dtc-version.sh
FREEBSD
M: Rafal Jaworowski <raj@semihalf.com>
@ -1026,6 +1027,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
F: drivers/sysreset/sysreset_sbi.c
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c

32
Makefile
View File

@ -299,9 +299,7 @@ KBUILD_HOSTLDLIBS := $(HOST_LFS_LIBS) $(HOSTLDLIBS)
# have older compilers as their default, so we make it explicit for
# these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
CSTD_FLAG := -std=gnu11
ifeq ($(HOSTOS),linux)
KBUILD_HOSTCFLAGS += $(CSTD_FLAG)
endif
ifeq ($(HOSTOS),cygwin)
KBUILD_HOSTCFLAGS += -ansi
@ -415,7 +413,13 @@ PERL = perl
PYTHON ?= python
PYTHON2 = python2
PYTHON3 ?= python3
DTC ?= $(objtree)/scripts/dtc/dtc
# The devicetree compiler and pylibfdt are automatically built unless DTC is
# provided. If DTC is provided, it is assumed the pylibfdt is available too.
DTC_INTREE := $(objtree)/scripts/dtc/dtc
DTC ?= $(DTC_INTREE)
DTC_MIN_VERSION := 010406
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@ -1951,9 +1955,29 @@ endif
endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
$(Q)$(MAKE) $(build)=scripts/dtc
$(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
$(MAKE) $(build)=scripts/dtc; \
else \
if ! $(DTC) -v >/dev/null; then \
echo '*** Failed to check dtc version: $(DTC)'; \
false; \
else \
if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
false; \
else \
if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
false; \
fi; \
fi; \
fi; \
fi; \
fi
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@

2
arch/arc/lib/bootm.c
View File

@ -63,7 +63,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
} else {

2
arch/arm/Kconfig
View File

@ -636,7 +636,6 @@ config ARCH_BCMSTB
select DM
select GPIO_EXTRA_HEADER
select OF_CONTROL
select OF_PRIOR_STAGE
imply CMD_DM
help
This enables support for Broadcom ARM-based set-top box
@ -1028,6 +1027,7 @@ config ARCH_SUNXI
select DM
select DM_ETH
select DM_GPIO
select DM_I2C if I2C
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI

6
arch/arm/cpu/armv7/stv0991/timer.c
View File

@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
@ -110,5 +110,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
return CONFIG_STV0991_HZ;
return CONFIG_SYS_HZ;
}

3
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -54,7 +54,8 @@ int ls_gic_rd_tables_init(void *blob)
lpi_base.start = addr;
lpi_base.end = addr + size - 1;
ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL,
0, NULL, 0);
if (ret) {
debug("%s: failed to add reserved memory\n", __func__);
return ret;

19
arch/arm/dts/Makefile
View File

@ -158,30 +158,36 @@ dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-axg-s400.dtb \
meson-axg-jethome-jethub-j100.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
meson-gxl-s905x-p212.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxl-s905w-jethome-jethub-j80.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-libretech-cc-v2.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxl-s905x-p212.dtb \
meson-gxm-khadas-vim2.dtb \
meson-gxm-s912-libretech-pc.dtb \
meson-gxm-wetek-core2.dtb \
meson-axg-s400.dtb \
meson-g12a-u200.dtb \
meson-g12a-radxa-zero.dtb \
meson-g12a-sei510.dtb \
meson-g12a-u200.dtb \
meson-g12b-a311d-khadas-vim3.dtb \
meson-g12b-gtking.dtb \
meson-g12b-gtking-pro.dtb \
meson-g12b-gsking-x.dtb \
meson-g12b-odroid-n2.dtb \
meson-g12b-odroid-n2-plus.dtb \
meson-g12b-a311d-khadas-vim3.dtb \
meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
meson-sm1-odroid-hc4.dtb \
meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
@ -632,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-libretech-all-h5-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
sun50i-h5-nanopi-r1s-h5.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \

10
arch/arm/dts/am33xx-clocks.dtsi
View File

@ -167,7 +167,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0490>, <0x045c>, <0x0468>;
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@ -207,7 +207,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>;
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@ -223,7 +223,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>;
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@ -247,7 +247,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@ -264,7 +264,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>;
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {

12
arch/arm/dts/am43xx-clocks.dtsi
View File

@ -199,7 +199,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@ -245,7 +245,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
@ -263,7 +263,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>;
reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
@ -281,7 +281,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
@ -300,7 +300,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>;
reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
@ -583,7 +583,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck {

6
arch/arm/dts/armada-37xx.dtsi
View File

@ -335,14 +335,14 @@
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
* with size a power of two. Use one 64 KiB window for
* with size a power of two. Use one 1 MiB window for
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
ranges = <0x82000000 0 0xe8000000
0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
0x81000000 0 0xefff0000
0 0xefff0000 0 0x10000>; /* Port 0 IO*/
0x81000000 0 0xeff00000
0 0xeff00000 0 0x100000>; /* Port 0 IO*/
};
};
};

36
arch/arm/dts/armada-8040-puzzle-m801.dts
View File

@ -243,6 +243,9 @@
&cp1_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_smi_pins>;
cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
@ -292,33 +295,24 @@
/*
* MPP Bus:
* [0-5] TDM
* [6,7] CP1_UART 0
* [8] CP1 10G SFP LOS
* [9] CP1 10G PHY RESET
* [10] CP1 10G SFP TX Disable
* [11] CP1 10G SFP Mode
* [12] SPI1 CS1n
* [13] SPI1 MISO (TDM and SPI ROM shared)
* [14] SPI1 CS0n
* [15] SPI1 MOSI (TDM and SPI ROM shared)
* [16] SPI1 CLK (TDM and SPI ROM shared)
* [24] CP1 2.5G SFP TX Disable
* [26] CP0 10G SFP TX Fault
* [27] CP0 10G SFP Mode
* [28] CP0 10G SFP LOS
* [29] CP0 10G SFP TX Disable
* [30] USB Over current indication
* [31] 10G Port 0 phy reset
* [27-28] SMI
* [29-30] CP1 MSS I2C
* [6-26, 31] GPIO
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8
0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
cp1_smi_pins: cp1-smi-pins {
marvell,pins = < 27 28 >;
marvell,function = <8>;
};
};
&ap_spi0 {

27
arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi Normal file
View File

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2021
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
*
* U-Boot bits of the IOT2050 Advanced PG2 variants
* (downgrade of usb0 to USB 2.0 mode)
*/
&serdes0 {
status = "disabled";
};
&dwc3_0 {
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
/delete-property/ phys;
/delete-property/ phy-names;
};
&usb0 {
maximum-speed = "high-speed";
/delete-property/ snps,dis-u1-entry-quirk;
/delete-property/ snps,dis-u2-entry-quirk;
};

4
arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
View File

@ -44,8 +44,10 @@
phy-names = "usb3-phy";
};
&usb0_phy {
&usb0 {
maximum-speed = "super-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"

2
arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
View File

@ -35,7 +35,7 @@
&cbass_main {
u-boot,dm-spl;
main-navss {
main_navss: bus@30800000 {
u-boot,dm-spl;
};
};

361
arch/arm/dts/meson-axg-jethome-jethub-j100.dts Normal file
View File

@ -0,0 +1,361 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
* Copyright (c) 2020 JetHome
* Author: Aleksandr Kazantsev <ak@tvip.ru>
* Author: Alexey Shevelkin <ash@tvip.ru>
* Author: Vyacheslav Bocharov <adeep@lexina.in>
*/
/dts-v1/;
#include "meson-axg.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";
model = "JetHome JetHub J100";
aliases {
serial0 = &uart_AO; /* Console */
serial1 = &uart_AO_B; /* External UART (Wireless Module) */
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* 1024MB RAM */
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
reserved-memory {
linux,cma {
size = <0x0 0x400000>;
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "VCC5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_5v>;
regulator-always-on;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
usb_pwr: regulator-usb_pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
regulator-always-on;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&scpi_sensors 0>;
trips {
cpu_passive: cpu-passive {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_hot: cpu-hot {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "hot";
};
cpu_critical: cpu-critical {
temperature = <100000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
};
cpu_cooling_maps: cooling-maps {
map0 {
trip = <&cpu_passive>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_hot>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
onewire {
compatible = "w1-gpio";
gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>;
#gpio-cells = <1>;
};
};
&efuse {
sn: sn@32 {
reg = <0x32 0x20>;
};
eth_mac: eth_mac@0 {
reg = <0x0 0x6>;
};
bt_mac: bt_mac@6 {
reg = <0x6 0x6>;
};
wifi_mac: wifi_mac@c {
reg = <0xc 0x6>;
};
bid: bid@12 {
reg = <0x12 0x20>;
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rmii_x_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rmii";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
/* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */
eth_phy0: ethernet-phy@0 {
/* compatible = "ethernet-phy-id0243.0c54";*/
max-speed = <100>;
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>;
};
};
};
/* Internal I2C bus (on CPU module) */
&i2c1 {
status = "okay";
pinctrl-0 = <&i2c1_z_pins>;
pinctrl-names = "default";
/* RTC */
pcf8563: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";
};
};
/* Peripheral I2C bus (on motherboard) */
&i2c_AO {
status = "okay";
pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
pinctrl-names = "default";
};
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
pinctrl-names = "default";
};
/* wifi module */
&sd_emmc_b {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr104;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* emmc storage */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* UART Bluetooth */
&uart_B {
status = "okay";
pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
};
};
/* UART Console */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
/* UART Wireless module */
&uart_AO_B {
status = "okay";
pinctrl-0 = <&uart_ao_b_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
phy-supply = <&usb_pwr>;
};
&spicc1 {
status = "okay";
pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>;
pinctrl-names = "default";
};
&gpio {
gpio-line-names =
"", "", "", "", "", // 0 - 4
"", "", "", "", "", // 5 - 9
"UserButton", "", "", "", "", // 10 - 14
"", "", "", "", "", // 15 - 19
"", "", "", "", "", // 20 - 24
"", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29
"Output1", "", "", "", "", // 30 - 34
"", "ZigBeeBOOT", "", "", "", // 35 - 39
"", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44
"Input2", "Input1", "", "", "", // 45 - 49
"", "", "", "", "", // 50 - 54
"", "", "", "", "", // 55 - 59
"", "", "", "", "", // 60 - 64
"", "", "", "", "", // 65 - 69
"", "", "", "", "", // 70 - 74
"", "", "", "", "", // 75 - 79
"", "", "", "", "", // 80 - 84
"", ""; // 85-86
};
&cpu0 {
#cooling-cells = <2>;
};
&cpu1 {
#cooling-cells = <2>;
};
&cpu2 {
#cooling-cells = <2>;
};
&cpu3 {
#cooling-cells = <2>;
};

8
arch/arm/dts/meson-axg-s400-u-boot.dtsi
View File

@ -3,8 +3,6 @@
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
#include "meson-axg-u-boot.dtsi"
/* wifi module */
&sd_emmc_b {
status = "disabled";
@ -15,12 +13,6 @@
status = "okay";
};
&usb {
status = "okay";
dr_mode = "otg";
vbus-supply = <&usb_pwr>;
};
&usb2_phy1 {
phy-supply = <&vcc_5v>;
};

16
arch/arm/dts/meson-axg-s400.dts
View File

@ -441,6 +441,16 @@
status = "okay";
};
&pcieA {
reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcieB {
reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
@ -584,3 +594,9 @@
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
dr_mode = "otg";
vbus-supply = <&usb_pwr>;
};

62
arch/arm/dts/meson-axg-u-boot.dtsi
View File

@ -1,62 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/ {
soc {
usb: usb@ffe09080 {
compatible = "amlogic,meson-gxl-usb-ctrl";
reg = <0x0 0xffe09080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>;
dr_mode = "otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy1";
dwc2: usb@ff400000 {
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
reg = <0x0 0xff400000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1>;
clock-names = "otg";
phys = <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
};
dwc3: usb@ff500000 {
compatible = "snps,dwc3";
reg = <0x0 0xff500000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
};
};
};
&apb {
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x9020 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
status = "okay";
};
};

181
arch/arm/dts/meson-axg.dtsi
View File

@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
#include <dt-bindings/power/meson-axg-power.h>
/ {
compatible = "amlogic,meson-axg";
@ -171,6 +172,98 @@
#size-cells = <2>;
ranges;
pcieA: pcie@f9800000 {
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
reg = <0x0 0xf9800000 0x0 0x400000>,
<0x0 0xff646000 0x0 0x2000>,
<0x0 0xf9f00000 0x0 0x100000>;
reg-names = "elbi", "cfg", "config";
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
clock-names = "general", "pclk", "port";
resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
reset-names = "port", "apb";
num-lanes = <1>;
phys = <&pcie_phy>;
phy-names = "pcie";
status = "disabled";
};
pcieB: pcie@fa000000 {
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
reg = <0x0 0xfa000000 0x0 0x400000>,
<0x0 0xff648000 0x0 0x2000>,
<0x0 0xfa400000 0x0 0x100000>;
reg-names = "elbi", "cfg", "config";
interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
clock-names = "general", "pclk", "port";
resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
reset-names = "port", "apb";
num-lanes = <1>;
phys = <&pcie_phy>;
phy-names = "pcie";
status = "disabled";
};
usb: usb@ffe09080 {
compatible = "amlogic,meson-axg-usb-ctrl";
reg = <0x0 0xffe09080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>;
dr_mode = "otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy1";
dwc2: usb@ff400000 {
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
reg = <0x0 0xff400000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1>;
clock-names = "otg";
phys = <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
};
dwc3: usb@ff500000 {
compatible = "snps,dwc3";
reg = <0x0 0xff500000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",
@ -187,9 +280,19 @@
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
status = "disabled";
};
pcie_phy: phy@ff644000 {
compatible = "amlogic,axg-pcie-phy";
reg = <0x0 0xff644000 0x0 0x1c>;
resets = <&reset RESET_PCIE_PHY>;
phys = <&mipi_pcie_analog_dphy>;
phy-names = "analog";
#phy-cells = <0>;
};
pdm: audio-controller@ff632000 {
compatible = "amlogic,axg-pdm";
reg = <0x0 0xff632000 0x0 0x34>;
@ -1117,6 +1220,52 @@
clocks = <&xtal>;
clock-names = "xtal";
};
pwrc: power-controller {
compatible = "amlogic,meson-axg-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&sysctrl_AO>;
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
reset-names = "viu", "venc", "vcbus",
"vencl", "vid_lock";
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
/*
* VPU clocking is provided by two identical clock paths
* VPU_0 and VPU_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
* Same for VAPB but with a final gate after the glitch free mux.
*/
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU>, /* Glitch free mux */
<&clkc CLKID_VAPB_0_SEL>,
<&clkc CLKID_VAPB_0>,
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VPU_0>,
<&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VAPB_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<250000000>,
<0>, /* Do Nothing */
<0>, /* Do Nothing */
<250000000>,
<0>; /* Do Nothing */
};
mipi_pcie_analog_dphy: phy {
compatible = "amlogic,axg-mipi-pcie-analog-phy";
#phy-cells = <0>;
status = "disabled";
};
};
};
@ -1129,6 +1278,19 @@
#mbox-cells = <1>;
};
mipi_dphy: phy@ff640000 {
compatible = "amlogic,axg-mipi-dphy";
reg = <0x0 0xff640000 0x0 0x100>;
clocks = <&clkc CLKID_MIPI_DSI_PHY>;
clock-names = "pclk";
resets = <&reset RESET_MIPI_PHY>;
reset-names = "phy";
phys = <&mipi_pcie_analog_dphy>;
phy-names = "analog";
#phy-cells = <0>;
status = "disabled";
};
audio: bus@ff642000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
@ -1563,6 +1725,14 @@
};
};
ge2d: ge2d@ff940000 {
compatible = "amlogic,axg-ge2d";
reg = <0x0 0xff940000 0x0 0x10000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_VAPB>;
resets = <&reset RESET_GE2D>;
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
@ -1701,6 +1871,7 @@
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
fifo-size = <128>;
};
};
@ -1734,6 +1905,16 @@
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x9020 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
};
};
sram: sram@fffc0000 {

7
arch/arm/dts/meson-g12-common-u-boot.dtsi
View File

@ -5,6 +5,13 @@
*/
/ {
/* Keep HW order from U-boot */
aliases {
/delete-property/ mmc0;
/delete-property/ mmc1;
/delete-property/ mmc2;
};
soc {
u-boot,dm-pre-reloc;
};

31
arch/arm/dts/meson-g12-common.dtsi
View File

@ -17,6 +17,12 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
mmc0 = &sd_emmc_b; /* SD card */
mmc1 = &sd_emmc_c; /* eMMC */
mmc2 = &sd_emmc_a; /* SDIO */
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
@ -122,9 +128,9 @@
pcie: pcie@fc000000 {
compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
reg = <0x0 0xfc000000 0x0 0x400000
0x0 0xff648000 0x0 0x2000
0x0 0xfc400000 0x0 0x200000>;
reg = <0x0 0xfc000000 0x0 0x400000>,
<0x0 0xff648000 0x0 0x2000>,
<0x0 0xfc400000 0x0 0x200000>;
reg-names = "elbi", "cfg", "config";
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
@ -134,8 +140,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
<0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
clocks = <&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_COMB
@ -209,7 +215,7 @@
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
compatible = "amlogic,meson-g12a-dwmac",
"snps,dwmac-3.70a",
"snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000>,
@ -282,6 +288,8 @@
hwrng: rng@218 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x218 0x0 0x4>;
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
};
@ -2001,7 +2009,7 @@
};
};
vrtc: rtc@0a8 {
vrtc: rtc@a8 {
compatible = "amlogic,meson-vrtc";
reg = <0x0 0x000a8 0x0 0x4>;
};
@ -2179,6 +2187,12 @@
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
};
watchdog: watchdog@f0d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x0 0xf0d0 0x0 0x10>;
clocks = <&xtal>;
};
spicc0: spi@13000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x44>;
@ -2303,6 +2317,7 @@
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
fifo-size = <128>;
};
};
@ -2380,7 +2395,7 @@
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_u2_susphy_quirk;
snps,quirk-frame-length-adjustment;
snps,quirk-frame-length-adjustment = <0x20>;
snps,parkmode-disable-ss-quirk;
};
};

7
arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-g12-common-u-boot.dtsi"

405
arch/arm/dts/meson-g12a-radxa-zero.dts Normal file
View File

@ -0,0 +1,405 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 BayLibre SAS. All rights reserved.
*/
/dts-v1/;
#include "meson-g12a.dtsi"
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "radxa,zero", "amlogic,g12a";
model = "Radxa Zero";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
cvbs-connector {
status = "disabled";
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
ao_5v: regulator-ao_5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
hdmi_pw: regulator-hdmi_pw {
compatible = "regulator-fixed";
regulator-name = "HDMI_PW";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&ao_5v>;
regulator-always-on;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&ao_5v>;
regulator-always-on;
};
vddcpu: regulator-vddcpu {
compatible = "pwm-regulator";
regulator-name = "VDDCPU";
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&ao_5v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-boot-on;
regulator-always-on;
};
sound {
compatible = "amlogic,axg-sound-card";
model = "RADXA-ZERO";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
};
&arb {
status = "okay";
};
&cec_AO {
pinctrl-0 = <&cec_ao_a_h_pins>;
pinctrl-names = "default";
status = "disabled";
hdmi-phandle = <&hdmi_tx>;
};
&cecb_AO {
pinctrl-0 = <&cec_ao_b_h_pins>;
pinctrl-names = "default";
status = "okay";
hdmi-phandle = <&hdmi_tx>;
};
&clkc_audio {
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
hdmi-supply = <&hdmi_pw>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "disabled";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin1";
status = "okay";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin0";
};
&saradc {
status = "okay";
vref-supply = <&vddao_1v8>;
};
/* SDIO */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr50;
max-frequency = <100000000>;
non-removable;
disable-wp;
/* WiFi firmware requires power to be kept while in suspend */
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddao_1v8>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddao_3v3>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
};
&tdmif_b {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;
clock-names = "lpo";
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
dr_mode = "host";
};

2
arch/arm/dts/meson-g12a-sei510.dts
View File

@ -181,7 +181,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-SEI510";
model = "SEI510";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",

7
arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-g12-common-u-boot.dtsi"

133
arch/arm/dts/meson-g12b-gsking-x.dts Normal file
View File

@ -0,0 +1,133 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
*/
/dts-v1/;
#include "meson-g12b-w400.dtsi"
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GS-King X";
aliases {
rtc0 = &rtc;
rtc1 = &vrtc;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
power-button {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "amlogic,axg-sound-card";
model = "GSKING-X";
audio-aux-devs = <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1",
"TDMOUT_A IN 1", "FRDDR_B OUT 1",
"TDMOUT_A IN 2", "FRDDR_C OUT 1",
"TDM_A Playback", "TDMOUT_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
};
};
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
};
&arb {
status = "okay";
};
&clkc_audio {
status = "okay";
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
wakeup-source;
};
};
&tdmif_a {
status = "okay";
};
&tdmout_a {
status = "okay";
};
&tohdmitx {
status = "okay";
};

23
arch/arm/dts/meson-g12b-gtking-pro.dts
View File

@ -11,9 +11,14 @@
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "azw,gtking", "amlogic,g12b";
compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GT-King Pro";
aliases {
rtc0 = &rtc;
rtc1 = &vrtc;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
@ -30,7 +35,7 @@
leds {
compatible = "gpio-leds";
white {
led-white {
label = "power:white";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -39,7 +44,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12B-GTKING-PRO";
model = "GTKING-PRO";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
@ -112,6 +117,18 @@
status = "okay";
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
wakeup-source;
};
};
&tdmif_b {
status = "okay";
};

22
arch/arm/dts/meson-g12b-gtking.dts
View File

@ -11,9 +11,14 @@
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "azw,gtking", "amlogic,g12b";
compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
model = "Beelink GT-King";
aliases {
rtc0 = &rtc;
rtc1 = &vrtc;
};
spdif_dit: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
@ -23,7 +28,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12B-GTKING";
model = "GTKING";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
@ -122,6 +127,19 @@
status = "okay";
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
wakeup-source;
};
};
&spdifout {
pinctrl-0 = <&spdif_out_h_pins>;
pinctrl-names = "default";

2
arch/arm/dts/meson-g12b-odroid-n2-plus.dts
View File

@ -19,7 +19,7 @@
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1040000>;
pwms = <&pwm_AO_cd 1 1500 0>;
pwms = <&pwm_ab 0 1500 0>;
};
&vddcpu_b {

74
arch/arm/dts/meson-g12b-odroid-n2.dtsi
View File

@ -13,6 +13,8 @@
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
rtc0 = &rtc;
rtc1 = &vrtc;
};
dioo2133: audio-amplifier-0 {
@ -40,7 +42,7 @@
leds {
compatible = "gpio-leds";
blue {
led-blue {
label = "n2:blue";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@ -211,7 +213,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12B-ODROID-N2";
model = "ODROID-N2";
audio-widgets = "Line", "Lineout";
audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
<&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
@ -408,12 +410,12 @@
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
@ -444,13 +446,58 @@
};
&gpio {
gpio-line-names =
/* GPIOZ */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* GPIOH */
"", "", "", "", "", "", "", "",
"",
/* BOOT */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* GPIOC */
"", "", "", "", "", "", "", "",
/* GPIOA */
"PIN_44", /* GPIOA_0 */
"PIN_46", /* GPIOA_1 */
"PIN_45", /* GPIOA_2 */
"PIN_47", /* GPIOA_3 */
"PIN_26", /* GPIOA_4 */
"", "", "", "", "", "",
"PIN_42", /* GPIOA_11 */
"PIN_32", /* GPIOA_12 */
"PIN_7", /* GPIOA_13 */
"PIN_27", /* GPIOA_14 */
"PIN_28", /* GPIOA_15 */
/* GPIOX */
"PIN_16", /* GPIOX_0 */
"PIN_18", /* GPIOX_1 */
"PIN_22", /* GPIOX_2 */
"PIN_11", /* GPIOX_3 */
"PIN_13", /* GPIOX_4 */
"PIN_33", /* GPIOX_5 */
"PIN_35", /* GPIOX_6 */
"PIN_15", /* GPIOX_7 */
"PIN_19", /* GPIOX_8 */
"PIN_21", /* GPIOX_9 */
"PIN_24", /* GPIOX_10 */
"PIN_23", /* GPIOX_11 */
"PIN_8", /* GPIOX_12 */
"PIN_10", /* GPIOX_13 */
"PIN_29", /* GPIOX_14 */
"PIN_31", /* GPIOX_15 */
"PIN_12", /* GPIOX_16 */
"PIN_3", /* GPIOX_17 */
"PIN_5", /* GPIOX_18 */
"PIN_36"; /* GPIOX_19 */
/*
* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
hog-0 {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
@ -478,6 +525,18 @@
linux,rc-map-name = "rc-odroid";
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
wakeup-source;
};
};
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
@ -494,6 +553,11 @@
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vddao_1v8>;
};
/* SD card */
&sd_emmc_b {
status = "okay";

2
arch/arm/dts/meson-g12b-w400.dtsi
View File

@ -264,7 +264,7 @@
max-speed = <1000>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;

4
arch/arm/dts/meson-g12b.dtsi
View File

@ -135,3 +135,7 @@
};
};
};
&mali {
dma-coherent;
};

2
arch/arm/dts/meson-gx-libretech-pc.dtsi
View File

@ -186,7 +186,7 @@
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S9XX-PC";
model = "LIBRETECH-PC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Speaker", "7J4-14 LEFT",
"Speaker", "7J4-11 RIGHT";

2
arch/arm/dts/meson-gx-p23x-q20x.dtsi
View File

@ -121,7 +121,7 @@
sound {
compatible = "amlogic,gx-sound-card";
model = "GX-P230-Q200";
model = "P230-Q200";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLP",

7
arch/arm/dts/meson-gx-u-boot.dtsi
View File

@ -5,6 +5,13 @@
*/
/ {
/* Keep HW order from U-boot */
aliases {
/delete-property/ mmc0;
/delete-property/ mmc1;
/delete-property/ mmc2;
};
soc {
u-boot,dm-pre-reloc;
};

7
arch/arm/dts/meson-gx.dtsi
View File

@ -20,6 +20,12 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
mmc0 = &sd_emmc_b; /* SD card */
mmc1 = &sd_emmc_c; /* eMMC */
mmc2 = &sd_emmc_a; /* SDIO */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -295,6 +301,7 @@
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
fifo-size = <128>;
};
uart_B: serial@84dc {

42
arch/arm/dts/meson-gxbb-nanopi-k2.dts
View File

@ -7,6 +7,7 @@
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
@ -130,6 +131,45 @@
};
};
};
sound {
compatible = "amlogic,gx-sound-card";
model = "NANOPI-K2";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
};
};
&aiu {
status = "okay";
};
&cec_AO {
@ -165,7 +205,7 @@
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;

44
arch/arm/dts/meson-gxbb-odroidc2.dts
View File

@ -9,6 +9,7 @@
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
@ -172,6 +173,45 @@
};
};
};
sound {
compatible = "amlogic,gx-sound-card";
model = "ODROID-C2";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
};
};
&aiu {
status = "okay";
};
&cec_AO {
@ -200,7 +240,7 @@
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
@ -217,7 +257,7 @@
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
hog-0 {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;

2
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
View File

@ -118,7 +118,7 @@
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S805X-AC";
model = "LIBRETECH-AC";
audio-widgets = "Speaker", "9J5-3 LEFT",
"Speaker", "9J5-2 RIGHT";
audio-routing = "9J5-3 LEFT", "ACODEC LOLN",

241
arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts Normal file
View File

@ -0,0 +1,241 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
* Copyright (c) 2020 JetHome
* Author: Aleksandr Kazantsev <ak@tvip.ru>
* Author: Alexey Shevelkin <ash@tvip.ru>
* Author: Vyacheslav Bocharov <adeep@lexina.in>
*/
/dts-v1/;
#include "meson-gxl.dtsi"
/ {
compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
model = "JetHome JetHub J80";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
reserved-memory {
linux,cma {
size = <0x0 0x1000000>;
};
};
aliases {
serial0 = &uart_AO; /* Console */
serial1 = &uart_A; /* Bluetooth */
serial2 = &uart_AO_B; /* Wireless module 1 */
serial3 = &uart_C; /* Wireless module 2 */
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
&efuse {
bt_mac: bt_mac@6 {
reg = <0x6 0x6>;
};
wifi_mac: wifi_mac@C {
reg = <0xc 0x6>;
};
};
&sn {
reg = <0x32 0x20>;
};
&eth_mac {
reg = <0x0 0x6>;
};
&bid {
reg = <0x12 0x20>;
};
&usb {
status = "okay";
dr_mode = "host";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
non-removable;
disable-wp;
/* WiFi firmware requires power to be kept while in suspend */
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* Console UART */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
/* S905W only has access to its internal PHY */
&ethmac {
status = "okay";
phy-mode = "rmii";
phy-handle = <&internal_phy>;
};
&internal_phy {
status = "okay";
pinctrl-0 = <&eth_link_led_pins>, <&eth_act_led_pins>;
pinctrl-names = "default";
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
};
&uart_C {
status = "okay";
pinctrl-0 = <&uart_c_pins>;
pinctrl-names = "default";
};
&uart_AO_B {
status = "okay";
pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
};
&i2c_B {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c_b_pins>;
pcf8563: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";
};
};

50
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
View File

@ -5,9 +5,9 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905x-p212.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
@ -42,10 +42,10 @@
};
};
pwmleds {
led-controller {
compatible = "pwm-leds";
power {
led-1 {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
@ -63,6 +63,45 @@
};
};
};
sound {
compatible = "amlogic,gx-sound-card";
model = "KHADAS-VIM";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
};
};
&aiu {
status = "okay";
};
&cec_AO {
@ -97,8 +136,7 @@
pinctrl-names = "default";
rtc: rtc@51 {
/* has to be enabled manually when a battery is connected: */
status = "disabled";
status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;

6
arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
View File

@ -84,7 +84,6 @@
regulator-always-on;
};
vcck: regulator-vcck {
compatible = "regulator-fixed";
regulator-name = "VCCK";
@ -124,7 +123,6 @@
regulator-always-on;
};
vddio_card: regulator-vddio-card {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
@ -161,7 +159,7 @@
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S905X-CC-V2";
model = "LIBRETECH-CC-V2";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
@ -195,7 +193,6 @@
};
};
&aiu {
status = "okay";
};
@ -207,7 +204,6 @@
hdmi-phandle = <&hdmi_tx>;
};
&ethmac {
status = "okay";
};

2
arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
View File

@ -135,7 +135,7 @@
sound {
compatible = "amlogic,gx-sound-card";
model = "GXL-LIBRETECH-S905X-CC";
model = "LIBRETECH-CC";
audio-aux-devs = <&dio2133>;
audio-widgets = "Line", "Lineout";
audio-routing = "AU2 INL", "ACODEC LOLN",

55
arch/arm/dts/meson-gxm-khadas-vim2.dts
View File

@ -7,9 +7,9 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxm.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
@ -81,10 +81,10 @@
};
};
pwmleds {
led-controller {
compatible = "pwm-leds";
power {
led-1 {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
@ -145,6 +145,45 @@
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sound {
compatible = "amlogic,gx-sound-card";
model = "KHADAS-VIM2";
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
};
};
&aiu {
status = "okay";
};
&cec_AO {
@ -154,7 +193,6 @@
hdmi-phandle = <&hdmi_tx>;
};
&cpu_cooling_maps {
map0 {
cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
@ -194,7 +232,7 @@
reg = <0>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
@ -228,8 +266,7 @@
pinctrl-names = "default";
rtc: rtc@51 {
/* has to be enabled manually when a battery is connected: */
status = "disabled";
status = "okay";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
@ -341,7 +378,7 @@
#size-cells = <1>;
compatible = "winbond,w25q16", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <3000000>;
spi-max-frequency = <104000000>;
};
};

2
arch/arm/dts/meson-gxm-wetek-core2.dts
View File

@ -22,7 +22,7 @@
leds {
compatible = "gpio-leds";
blue {
led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;

20
arch/arm/dts/meson-gxm.dtsi
View File

@ -42,11 +42,28 @@
};
};
cpu0: cpu@0 {
capacity-dmips-mhz = <1024>;
};
cpu1: cpu@1 {
capacity-dmips-mhz = <1024>;
};
cpu2: cpu@2 {
capacity-dmips-mhz = <1024>;
};
cpu3: cpu@3 {
capacity-dmips-mhz = <1024>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@ -57,6 +74,7 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@ -67,6 +85,7 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@ -77,6 +96,7 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;

73
arch/arm/dts/meson-khadas-vim3.dtsi
View File

@ -6,6 +6,7 @@
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
@ -13,6 +14,8 @@
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
rtc0 = &rtc;
rtc1 = &vrtc;
};
chosen {
@ -41,13 +44,15 @@
compatible = "gpio-leds";
led-white {
label = "vim3:white:sys";
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-red {
label = "vim3:red";
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>;
};
};
@ -165,12 +170,17 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12B-KHADAS-VIM3";
audio-aux-devs = <&tdmout_a>;
model = "KHADAS-VIM3";
audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
"TDM_A Playback", "TDMOUT_A OUT";
"TDM_A Playback", "TDMOUT_A OUT",
"TDMIN_A IN 0", "TDM_A Capture",
"TDMIN_A IN 3", "TDM_A Loopback",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
@ -193,8 +203,20 @@
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&toddr_a>;
};
dai-link-4 {
sound-dai = <&toddr_b>;
};
dai-link-5 {
sound-dai = <&toddr_c>;
};
/* 8ch hdmi interface */
dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
@ -209,7 +231,7 @@
};
/* hdmi glue */
dai-link-4 {
dai-link-7 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
@ -278,12 +300,12 @@
};
&ethmac {
pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-mode = "rgmii";
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-mode = "rgmii";
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
};
&frddr_a {
@ -330,7 +352,7 @@
#gpio-cells = <2>;
};
rtc@51 {
rtc: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
@ -349,9 +371,9 @@
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
};
&saradc {
@ -445,15 +467,30 @@
};
};
&tdmif_a {
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmout_a {
status = "okay";
};
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&tohdmitx {
status = "okay";
};

13
arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-sm1-u-boot.dtsi"
&ethmac {
snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
};

646
arch/arm/dts/meson-sm1-bananapi-m5.dts Normal file
View File

@ -0,0 +1,646 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 BayLibre SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/dts-v1/;
#include "meson-sm1.dtsi"
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-toacodec.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "bananapi,bpi-m5", "amlogic,sm1";
model = "Banana Pi BPI-M5";
adc_keys {
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
key {
label = "SW3";
linux,code = <BTN_3>;
press-threshold-microvolt = <1700000>;
};
};
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* TOFIX: handle CVBS_DET on SARADC channel 0 */
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
gpio-keys {
compatible = "gpio-keys";
key {
label = "SW1";
linux,code = <BTN_1>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
leds {
compatible = "gpio-leds";
green {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
};
blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
emmc_1v8: regulator-emmc_1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
dc_in: regulator-dc_in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
vddio_c: regulator-vddio_c {
compatible = "regulator-gpio";
regulator-name = "VDDIO_C";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
gpios-states = <1>;
states = <1800000 0>,
<3300000 1>;
};
tflash_vdd: regulator-tflash_vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_in>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-always-on;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_in>;
regulator-always-on;
};
vddcpu: regulator-vddcpu {
/*
* SY8120B1ABC DC/DC Regulator.
*/
compatible = "pwm-regulator";
regulator-name = "VDDCPU";
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-boot-on;
regulator-always-on;
};
/* USB Hub Power Enable */
vl_pwr_en: regulator-vl_pwr_en {
compatible = "regulator-fixed";
regulator-name = "VL_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_in>;
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "amlogic,axg-sound-card";
model = "BPI-M5";
audio-widgets = "Line", "Lineout";
audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
<&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT",
"TDMOUT_C IN 0", "FRDDR_A OUT 2",
"TDMOUT_C IN 1", "FRDDR_B OUT 2",
"TDMOUT_C IN 2", "FRDDR_C OUT 2",
"TDM_C Playback", "TDMOUT_C OUT",
"TDMIN_A IN 4", "TDM_B Loopback",
"TDMIN_B IN 4", "TDM_B Loopback",
"TDMIN_C IN 4", "TDM_B Loopback",
"TDMIN_A IN 5", "TDM_C Loopback",
"TDMIN_B IN 5", "TDM_C Loopback",
"TDMIN_C IN 5", "TDM_C Loopback",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT",
"TODDR_A IN 1", "TDMIN_B OUT",
"TODDR_B IN 1", "TDMIN_B OUT",
"TODDR_C IN 1", "TDMIN_B OUT",
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
"Lineout", "ACODEC LOLP",
"Lineout", "ACODEC LORP";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
dai-link-3 {
sound-dai = <&toddr_a>;
};
dai-link-4 {
sound-dai = <&toddr_b>;
};
dai-link-5 {
sound-dai = <&toddr_c>;
};
/* 8ch hdmi interface */
dai-link-6 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec-0 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
codec-1 {
sound-dai = <&toacodec TOACODEC_IN_B>;
};
};
/* i2s jack output interface */
dai-link-7 {
sound-dai = <&tdmif_c>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
mclk-fs = <256>;
codec-0 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
};
codec-1 {
sound-dai = <&toacodec TOACODEC_IN_C>;
};
};
/* hdmi glue */
dai-link-8 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
/* acodec glue */
dai-link-9 {
sound-dai = <&toacodec TOACODEC_OUT>;
codec {
sound-dai = <&acodec>;
};
};
};
};
&acodec {
AVDD-supply = <&vddao_1v8>;
status = "okay";
};
&arb {
status = "okay";
};
&clkc_audio {
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
};
};
&ethmac {
pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-mode = "rgmii-txid";
phy-handle = <&external_phy>;
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&gpio {
gpio-line-names =
/* GPIOZ */
"ETH_MDIO", /* GPIOZ_0 */
"ETH_MDC", /* GPIOZ_1 */
"ETH_RXCLK", /* GPIOZ_2 */
"ETH_RX_DV", /* GPIOZ_3 */
"ETH_RXD0", /* GPIOZ_4 */
"ETH_RXD1", /* GPIOZ_5 */
"ETH_RXD2", /* GPIOZ_6 */
"ETH_RXD3", /* GPIOZ_7 */
"ETH_TXCLK", /* GPIOZ_8 */
"ETH_TXEN", /* GPIOZ_9 */
"ETH_TXD0", /* GPIOZ_10 */
"ETH_TXD1", /* GPIOZ_11 */
"ETH_TXD2", /* GPIOZ_12 */
"ETH_TXD3", /* GPIOZ_13 */
"ETH_INTR", /* GPIOZ_14 */
"ETH_NRST", /* GPIOZ_15 */
/* GPIOH */
"HDMI_SDA", /* GPIOH_0 */
"HDMI_SCL", /* GPIOH_1 */
"HDMI_HPD", /* GPIOH_2 */
"HDMI_CEC", /* GPIOH_3 */
"VL-RST_N", /* GPIOH_4 */
"CON1-P36", /* GPIOH_5 */
"VL-PWREN", /* GPIOH_6 */
"WiFi_3V3_1V8", /* GPIOH_7 */
"TFLASH_VDD_EN", /* GPIOH_8 */
/* BOOT */
"eMMC_D0", /* BOOT_0 */
"eMMC_D1", /* BOOT_1 */
"eMMC_D2", /* BOOT_2 */
"eMMC_D3", /* BOOT_3 */
"eMMC_D4", /* BOOT_4 */
"eMMC_D5", /* BOOT_5 */
"eMMC_D6", /* BOOT_6 */
"eMMC_D7", /* BOOT_7 */
"eMMC_CLK", /* BOOT_8 */
"",
"eMMC_CMD", /* BOOT_10 */
"",
"eMMC_RST#", /* BOOT_12 */
"eMMC_DS", /* BOOT_13 */
/* GPIOC */
"SD_D0_B", /* GPIOC_0 */
"SD_D1_B", /* GPIOC_1 */
"SD_D2_B", /* GPIOC_2 */
"SD_D3_B", /* GPIOC_3 */
"SD_CLK_B", /* GPIOC_4 */
"SD_CMD_B", /* GPIOC_5 */
"CARD_EN_DET", /* GPIOC_6 */
"",
/* GPIOA */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "",
"CON1-P27", /* GPIOA_14 */
"CON1-P28", /* GPIOA_15 */
/* GPIOX */
"CON1-P16", /* GPIOX_0 */
"CON1-P18", /* GPIOX_1 */
"CON1-P22", /* GPIOX_2 */
"CON1-P11", /* GPIOX_3 */
"CON1-P13", /* GPIOX_4 */
"CON1-P07", /* GPIOX_5 */
"CON1-P33", /* GPIOX_6 */
"CON1-P15", /* GPIOX_7 */
"CON1-P19", /* GPIOX_8 */
"CON1-P21", /* GPIOX_9 */
"CON1-P24", /* GPIOX_10 */
"CON1-P23", /* GPIOX_11 */
"CON1-P08", /* GPIOX_12 */
"CON1-P10", /* GPIOX_13 */
"CON1-P29", /* GPIOX_14 */
"CON1-P31", /* GPIOX_15 */
"CON1-P26", /* GPIOX_16 */
"CON1-P03", /* GPIOX_17 */
"CON1-P05", /* GPIOX_18 */
"CON1-P32"; /* GPIOX_19 */
/*
* WARNING: The USB Hub on the BPI-M5 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&gpio_ao {
gpio-line-names =
/* GPIOAO */
"DEBUG TX", /* GPIOAO_0 */
"DEBUG RX", /* GPIOAO_1 */
"SYS_LED2", /* GPIOAO_2 */
"UPDATE_KEY", /* GPIOAO_3 */
"CON1-P40", /* GPIOAO_4 */
"IR_IN", /* GPIOAO_5 */
"TF_3V3N_1V8_EN", /* GPIOAO_6 */
"CON1-P35", /* GPIOAO_7 */
"CON1-P12", /* GPIOAO_8 */
"CON1-P37", /* GPIOAO_9 */
"CON1-P38", /* GPIOAO_10 */
"SYS_LED", /* GPIOAO_11 */
/* GPIOE */
"VDDEE_PWM", /* GPIOE_0 */
"VDDCPU_PWM", /* GPIOE_1 */
"TF_PWR_EN"; /* GPIOE_2 */
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
hdmi-supply = <&dc_in>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin1";
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vddao_1v8>;
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
/* TOFIX: SD card is barely usable in SDR modes */
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&vddio_c>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&emmc_1v8>;
};
&tdmif_b {
status = "okay";
};
&tdmif_c {
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmin_b {
status = "okay";
};
&tdmin_c {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&tdmout_c {
status = "okay";
};
&toacodec {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
};
&usb2_phy0 {
phy-supply = <&dc_in>;
};
&usb2_phy1 {
/* Enable the hub which is connected to this port */
phy-supply = <&vl_pwr_en>;
};

20
arch/arm/dts/meson-sm1-khadas-vim3l.dts
View File

@ -32,6 +32,19 @@
regulator-boot-on;
regulator-always-on;
};
sound {
model = "G12B-KHADAS-VIM3L";
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
"TDM_A Playback", "TDMOUT_A OUT",
"TDMIN_A IN 0", "TDM_A Capture",
"TDMIN_A IN 13", "TDM_A Loopback",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT";
};
};
&cpu0 {
@ -89,13 +102,12 @@
status = "okay";
};
&sd_emmc_a {
sd-uhs-sdr50;
};
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/
&sd_emmc_a {
sd-uhs-sdr50;
};

448
arch/arm/dts/meson-sm1-odroid-c4.dts
View File

@ -5,34 +5,12 @@
/dts-v1/;
#include "meson-sm1.dtsi"
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
#include "meson-sm1-odroid.dtsi"
/ {
compatible = "hardkernel,odroid-c4", "amlogic,sm1";
model = "Hardkernel ODROID-C4";
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
@ -45,324 +23,19 @@
};
};
tflash_vdd: regulator-tflash_vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
tf_io: gpio-regulator-tf_io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0>,
<1800000 1>;
};
flash_1v8: regulator-flash_1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
vddcpu: regulator-vddcpu {
/*
* MP8756GD Regulator.
*/
compatible = "pwm-regulator";
regulator-name = "VDDCPU";
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-boot-on;
regulator-always-on;
};
hub_5v: regulator-hub_5v {
compatible = "regulator-fixed";
regulator-name = "HUB_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
/* Connected to the Hub CHIPENABLE, LOW sets low power state */
gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_pwr_en: regulator-usb_pwr_en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
/* Connected to the microUSB port power enable */
gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
sound {
compatible = "amlogic,axg-sound-card";
model = "SM1-ODROID-C4";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
/* hdmi glue */
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
model = "ODROID-C4";
};
};
&arb {
status = "okay";
};
&clkc_audio {
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
};
};
&ethmac {
pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-mode = "rgmii";
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&gpio {
gpio-line-names =
/* GPIOZ */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* GPIOH */
"", "", "", "", "",
"PIN_36", /* GPIOH_5 */
"PIN_26", /* GPIOH_6 */
"PIN_32", /* GPIOH_7 */
"",
/* BOOT */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* GPIOC */
"", "", "", "", "", "", "", "",
/* GPIOA */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "",
"PIN_27", /* GPIOA_14 */
"PIN_28", /* GPIOA_15 */
/* GPIOX */
"PIN_16", /* GPIOX_0 */
"PIN_18", /* GPIOX_1 */
"PIN_22", /* GPIOX_2 */
"PIN_11", /* GPIOX_3 */
"PIN_13", /* GPIOX_4 */
"PIN_7", /* GPIOX_5 */
"PIN_33", /* GPIOX_6 */
"PIN_15", /* GPIOX_7 */
"PIN_19", /* GPIOX_8 */
"PIN_21", /* GPIOX_9 */
"PIN_24", /* GPIOX_10 */
"PIN_23", /* GPIOX_11 */
"PIN_8", /* GPIOX_12 */
"PIN_10", /* GPIOX_13 */
"PIN_29", /* GPIOX_14 */
"PIN_31", /* GPIOX_15 */
"PIN_12", /* GPIOX_16 */
"PIN_3", /* GPIOX_17 */
"PIN_5", /* GPIOX_18 */
"PIN_35"; /* GPIOX_19 */
/*
* WARNING: The USB Hub on the Odroid-C4 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
hog-0 {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
@ -370,121 +43,6 @@
};
};
&gpio_ao {
gpio-line-names =
/* GPIOAO */
"", "", "", "",
"PIN_47", /* GPIOAO_4 */
"", "",
"PIN_45", /* GPIOAO_7 */
"PIN_46", /* GPIOAO_8 */
"PIN_44", /* GPIOAO_9 */
"PIN_42", /* GPIOAO_10 */
"",
/* GPIOE */
"", "", "";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
hdmi-supply = <&vcc_5v>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
linux,rc-map-name = "rc-odroid";
};
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin1";
status = "okay";
};
&saradc {
status = "okay";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&tf_io>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&flash_1v8>;
};
&tdmif_b {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
vbus-supply = <&usb_pwr_en>;
};
&usb2_phy0 {
phy-supply = <&vcc_5v>;
};
&usb2_phy1 {
/* Enable the hub which is connected to this port */
phy-supply = <&hub_5v>;
};

23
arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi Normal file
View File

@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-sm1-u-boot.dtsi"
&ethmac {
snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
};
/* SARADC is needed for proper board variant detection */
&saradc {
status = "okay";
vref-supply = <&vddao_1v8>;
};
&tflash_vdd {
gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
};

140
arch/arm/dts/meson-sm1-odroid-hc4.dts Normal file
View File

@ -0,0 +1,140 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
*/
/dts-v1/;
#include "meson-sm1-odroid.dtsi"
/ {
compatible = "hardkernel,odroid-hc4", "amlogic,sm1";
model = "Hardkernel ODROID-HC4";
aliases {
rtc0 = &rtc;
rtc1 = &vrtc;
};
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
cooling-min-state = <0>;
cooling-max-state = <3>;
cooling-levels = <0 120 170 220>;
pwms = <&pwm_cd 1 40000 0>;
};
leds {
compatible = "gpio-leds";
led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
panic-indicator;
};
led-red {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
/* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
p12v_0: regulator-p12v_0 {
compatible = "regulator-fixed";
regulator-name = "P12V_0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&main_12v>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-always-on;
};
/* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
p12v_1: regulator-p12v_1 {
compatible = "regulator-fixed";
regulator-name = "P12V_1";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&main_12v>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-always-on;
};
sound {
model = "ODROID-HC4";
};
};
&cpu_thermal {
cooling-maps {
map {
trip = <&cpu_passive>;
cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&ir {
linux,rc-map-name = "rc-odroid";
};
&i2c2 {
status = "okay";
pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
status = "okay";
compatible = "nxp,pcf8563";
reg = <0x51>;
wakeup-source;
};
};
&pcie {
status = "okay";
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
};
&pwm_cd {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pwm_d_x6_pins>;
};
&sd_emmc_c {
status = "disabled";
};
&spifc {
status = "okay";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
};
};
&usb {
phys = <&usb2_phy1>;
phy-names = "usb2-phy1";
};
&usb2_phy0 {
status = "disabled";
};

449
arch/arm/dts/meson-sm1-odroid.dtsi Normal file
View File

@ -0,0 +1,449 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
*/
#include "meson-sm1.dtsi"
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
tflash_vdd: regulator-tflash_vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-always-on;
};
tf_io: gpio-regulator-tf_io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_5v>;
enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
gpios-states = <0>;
states = <3300000 0>,
<1800000 1>;
};
flash_1v8: regulator-flash_1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
vddcpu: regulator-vddcpu {
/*
* MP8756GD Regulator.
*/
compatible = "pwm-regulator";
regulator-name = "VDDCPU";
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-boot-on;
regulator-always-on;
};
usb_pwr_en: regulator-usb_pwr_en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
/* Connected to the microUSB port power enable */
gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
sound {
compatible = "amlogic,axg-sound-card";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
/* hdmi glue */
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
};
&arb {
status = "okay";
};
&clkc_audio {
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
};
};
&ethmac {
pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-mode = "rgmii";
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&gpio {
gpio-line-names =
/* GPIOZ */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* GPIOH */
"", "", "", "", "",
"PIN_36", /* GPIOH_5 */
"PIN_26", /* GPIOH_6 */
"PIN_32", /* GPIOH_7 */
"",
/* BOOT */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* GPIOC */
"", "", "", "", "", "", "", "",
/* GPIOA */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "",
"PIN_27", /* GPIOA_14 */
"PIN_28", /* GPIOA_15 */
/* GPIOX */
"PIN_16", /* GPIOX_0 */
"PIN_18", /* GPIOX_1 */
"PIN_22", /* GPIOX_2 */
"PIN_11", /* GPIOX_3 */
"PIN_13", /* GPIOX_4 */
"PIN_7", /* GPIOX_5 */
"PIN_33", /* GPIOX_6 */
"PIN_15", /* GPIOX_7 */
"PIN_19", /* GPIOX_8 */
"PIN_21", /* GPIOX_9 */
"PIN_24", /* GPIOX_10 */
"PIN_23", /* GPIOX_11 */
"PIN_8", /* GPIOX_12 */
"PIN_10", /* GPIOX_13 */
"PIN_29", /* GPIOX_14 */
"PIN_31", /* GPIOX_15 */
"PIN_12", /* GPIOX_16 */
"PIN_3", /* GPIOX_17 */
"PIN_5", /* GPIOX_18 */
"PIN_35"; /* GPIOX_19 */
};
&gpio_ao {
gpio-line-names =
/* GPIOAO */
"", "", "", "",
"PIN_47", /* GPIOAO_4 */
"", "",
"PIN_45", /* GPIOAO_7 */
"PIN_46", /* GPIOAO_8 */
"PIN_44", /* GPIOAO_9 */
"PIN_42", /* GPIOAO_10 */
"",
/* GPIOE */
"", "", "";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
hdmi-supply = <&vcc_5v>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin1";
status = "okay";
};
&saradc {
status = "okay";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&tf_io>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&flash_1v8>;
};
&tdmif_b {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
vbus-supply = <&usb_pwr_en>;
};
&usb2_phy0 {
phy-supply = <&vcc_5v>;
};

10
arch/arm/dts/meson-sm1-sei610.dts
View File

@ -101,20 +101,20 @@
};
};
leds {
led-controller-1 {
compatible = "gpio-leds";
led-bluetooth {
led-1 {
label = "sei610:blue:bt";
gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
default-state = "off";
};
};
pwmleds {
led-controller-2 {
compatible = "pwm-leds";
power {
led-2 {
label = "sei610:red:power";
pwms = <&pwm_AO_ab 0 30518 0>;
max-brightness = <255>;
@ -220,7 +220,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "SM1-SEI610";
model = "SEI610";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",

12
arch/arm/dts/meson-sm1.dtsi
View File

@ -130,7 +130,7 @@
opp-microvolt = <790000>;
};
opp-1512000000 {
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <800000>;
};
@ -401,6 +401,16 @@
status = "disabled";
};
toacodec: audio-controller@740 {
compatible = "amlogic,sm1-toacodec",
"amlogic,g12a-toacodec";
reg = <0x0 0x740 0x0 0x4>;
#sound-dai-cells = <1>;
sound-name-prefix = "TOACODEC";
resets = <&clkc_audio AUD_RESET_TOACODEC>;
status = "disabled";
};
tohdmitx: audio-controller@744 {
compatible = "amlogic,sm1-tohdmitx",
"amlogic,g12a-tohdmitx";

4
arch/arm/dts/px30.dtsi
View File

@ -967,7 +967,7 @@
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
pinctrl-names = "default";
pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
@ -1953,7 +1953,7 @@
<1 RK_PA1 3 &pcfg_pull_none>;
};
sfc_cs: sfc-cs {
sfc_cs0: sfc-cs0 {
rockchip,pins =
<1 RK_PA4 3 &pcfg_pull_none>;
};

12
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
View File

@ -18,8 +18,18 @@
};
};
/* U-Boot clk driver for px30 cannot set GPU_CLK */
&cru {
u-boot,dm-pre-reloc;
assigned-clocks = <&cru PLL_NPLL>,
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
<&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
assigned-clock-rates = <1188000000>,
<200000000>, <200000000>,
<150000000>, <150000000>,
<100000000>, <17000000>;
};
&dmc {
@ -70,7 +80,7 @@
u-boot,dm-pre-reloc;
};
&spi_flash {
&{/sfc@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};

8
arch/arm/dts/rk3326-odroid-go2.dts
View File

@ -618,18 +618,18 @@
};
&sfc {
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
status = "okay";
spi_flash: xt25f128b@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
spi-tx-bus-width = <1>;
};
};

8
arch/arm/dts/sama5d2.dtsi
View File

@ -671,6 +671,14 @@
status = "disabled";
};
pwm0: pwm@f802c000 {
compatible = "atmel,sama5d2-pwm";
reg = <0xf802c000 0x4000>;
clocks = <&pwm_clk>;
#pwm-cells = <3>;
status = "disabled";
};
rstc@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;

4
arch/arm/dts/stm32f746.dtsi
View File

@ -313,6 +313,7 @@
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -325,6 +326,7 @@
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -337,6 +339,7 @@
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -349,6 +352,7 @@
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};

4
arch/arm/dts/stm32h743.dtsi
View File

@ -124,6 +124,7 @@
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -136,6 +137,7 @@
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -148,6 +150,7 @@
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -395,6 +398,7 @@
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
i2c-analog-filter;
status = "disabled";
};

195
arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts Normal file
View File

@ -0,0 +1,195 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
*
* Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
* Copyright (C) 2017 Antony Antony <antony@phenome.org>
* Copyright (C) 2016 ARM Ltd.
*/
/dts-v1/;
#include "sun50i-h5.dtsi"
#include "sun50i-h5-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "FriendlyARM NanoPi R1S H5";
compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
ethernet1 = &rtl8189etv;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-2 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
};
};
r-gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
status = "okay";
};
vdd_cpux: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "vdd-cpux";
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <50>; /* 4ms */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
gpios-states = <0x1>;
states = <1100000 0x0>, <1300000 0x1>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
post-power-on-delay-ms = <200>;
};
};
&cpu0 {
cpu-supply = <&vdd_cpux>;
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii-id";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&i2c0 {
status = "okay";
eeprom@51 {
compatible = "microchip,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
rtl8189etv: sdio_wifi@1 {
reg = <1>;
};
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pa_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
/* USB Type-A port's VBUS is always on */
usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};

12
arch/arm/include/asm/arch-am33xx/clock.h
View File

@ -78,6 +78,18 @@
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
/* CM_SSC_DELTAM_DPLL */
#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0)
#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18
#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18)
/* CM_SSC_MODFREQ_DPLL */
#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0
#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0)
#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7
#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8)
struct dpll_params {
u32 m;
u32 n;

8
arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
View File

@ -11,7 +11,7 @@
#include <asm/arch/sys_proto.h>
/* CONFIG_REG_0 */
/* CFG REG_0 */
#define CFG_REG_0_OFFSET 0xC
#define CFG_REG_ROM_READ_SHIFT 1
#define CFG_REG_ROM_READ_MASK (1 << 1)
@ -22,18 +22,18 @@
#define CFG_REG_ROM_READ_START (1 << 1)
#define CFG_REG_ROM_READ_END (0 << 1)
/* CONFIG_REG_2 */
/* CFG REG_2 */
#define CFG_REG_2_OFFSET 0x14
#define CFG_REG_REFCLK_PERIOD_SHIFT 0
#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
#define CFG_REG_REFCLK_PERIOD 0x2EF
/* CONFIG_REG_8 */
/* CFG REG_8 */
#define CFG_REG_8_OFFSET 0x2C
#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
/* CONFIG_REG_3/4 */
/* CFG REG_3/4 */
#define CFG_REG_3_OFFSET 0x18
#define CFG_REG_4_OFFSET 0x1C
#define CFG_REG_DLY_CNT_SHIFT 16

2
arch/arm/include/asm/arch-rockchip/cru_rk3568.h
View File

@ -14,7 +14,7 @@
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1000 * MHz)
#define PPLL_HZ (100 * MHz)
#define PPLL_HZ (200 * MHz)
/* RK3568 pll id */
enum rk3568_pll_id {

4
arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
View File

@ -36,7 +36,7 @@ struct gpt_regs *const gpt1_regs_ptr =
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
#define CONFIG_STV0991_HZ 1000
#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif

20
arch/arm/include/asm/arch-sunxi/gpio.h
View File

@ -93,20 +93,10 @@ struct sunxi_gpio_reg {
#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
/* GPIO bank sizes */
#define SUNXI_GPIO_A_NR 32
#define SUNXI_GPIO_B_NR 32
#define SUNXI_GPIO_C_NR 32
#define SUNXI_GPIO_D_NR 32
#define SUNXI_GPIO_E_NR 32
#define SUNXI_GPIO_F_NR 32
#define SUNXI_GPIO_G_NR 32
#define SUNXI_GPIO_H_NR 32
#define SUNXI_GPIO_I_NR 32
#define SUNXI_GPIO_L_NR 32
#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIOS_PER_BANK 32
#define SUNXI_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + 0)
((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
enum sunxi_gpio_number {
SUNXI_GPIO_A_START = 0,
@ -148,8 +138,6 @@ enum sunxi_gpio_number {
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
#define SUN6I_GPA_SDC2 5
#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2
@ -173,12 +161,10 @@ enum sunxi_gpio_number {
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
@ -242,9 +228,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
int sunxi_name_to_gpio_bank(const char *name);
int sunxi_name_to_gpio(const char *name);
#define name_to_gpio(name) sunxi_name_to_gpio(name)
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
int axp_gpio_init(void);

10
arch/arm/include/asm/arch-tegra/board.h
View File

@ -30,4 +30,14 @@ void pin_mux_nand(void); /* overridable NAND pinmux setup */
void pin_mux_mmc(void); /* overridable mmc pinmux setup */
void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
/*
* Helpers for various standard DT update mechanisms.
*/
#if defined(CONFIG_ARM64)
void ft_mac_address_setup(void *fdt);
void ft_carveout_setup(void *fdt, const char *const *nodes,
unsigned int count);
#endif
#endif

4
arch/arm/lib/bootm.c
View File

@ -199,7 +199,7 @@ static void boot_prep_linux(bootm_headers_t *images)
{
char *commandline = env_get("bootargs");
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
@ -356,7 +356,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
announce_and_cleanup(fake);
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
r2 = (unsigned long)images->ft_addr;
else
r2 = gd->bd->bi_boot_params;

2
arch/arm/mach-imx/hab.c
View File

@ -591,7 +591,7 @@ static ulong get_image_ivt_offset(ulong img_addr)
return (image_get_image_size((image_header_t *)img_addr)
+ 0x1000 - 1) & ~(0x1000 - 1);
#endif
#if IMAGE_ENABLE_FIT
#if CONFIG_IS_ENABLED(FIT)
case IMAGE_FORMAT_FIT:
return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
#endif

7
arch/arm/mach-kirkwood/include/mach/config.h
View File

@ -62,13 +62,6 @@
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */
/*
* USB/EHCI
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */
/*
* IDE Support on SATA ports
*/

1
arch/arm/mach-meson/board-info.c
View File

@ -64,6 +64,7 @@ static const struct meson_gx_package_id {
{ "A113X", 0x25, 0x37, 0xff },
{ "A113D", 0x25, 0x22, 0xff },
{ "S905D2", 0x28, 0x10, 0xf0 },
{ "S905Y2", 0x28, 0x30, 0xf0 },
{ "S905X2", 0x28, 0x40, 0xf0 },
{ "A311D", 0x29, 0x10, 0xf0 },
{ "S922X", 0x29, 0x40, 0xf0 },

1
arch/arm/mach-mvebu/Kconfig
View File

@ -11,6 +11,7 @@ config ARMADA_32BIT
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
select SPL_SKIP_LOWLEVEL_INIT
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
select TRANSLATION_OFFSET

297
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
View File

@ -21,35 +21,12 @@ __weak void board_pex_config(void)
int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
{
u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
temp_reg, addr, dev_id, ctrl_mode;
enum serdes_type serdes_type;
u32 idx;
u32 idx, tmp;
DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
/* configuration for PEX only */
if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
(serdes_type != PEX2) && (serdes_type != PEX3))
continue;
if ((serdes_type != PEX0) &&
((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
/* for PEX by4 - relevant for the first port only */
continue;
}
pex_idx = serdes_type - PEX0;
tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
tmp &= ~(0xf << 20);
tmp |= (0x4 << 20);
reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
}
tmp = reg_read(SOC_CTRL_REG);
tmp = reg_read(SOC_CONTROL_REG1);
tmp &= ~0x03;
for (idx = 0; idx < count; idx++) {
@ -79,277 +56,9 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
}
}
reg_write(SOC_CTRL_REG, tmp);
/* Support gen1/gen2 */
DEBUG_INIT_FULL_S("Support gen1/gen2\n");
reg_write(SOC_CONTROL_REG1, tmp);
board_pex_config();
next_busno = 0;
mdelay(150);
for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
DEBUG_INIT_FULL_S(" serdes_type=0x");
DEBUG_INIT_FULL_D(serdes_type, 8);
DEBUG_INIT_FULL_S("\n");
DEBUG_INIT_FULL_S(" idx=0x");
DEBUG_INIT_FULL_D(idx, 8);
DEBUG_INIT_FULL_S("\n");
/* Configuration for PEX only */
if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
(serdes_type != PEX2) && (serdes_type != PEX3))
continue;
if ((serdes_type != PEX0) &&
((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
/* for PEX by4 - relevant for the first port only */
continue;
}
pex_idx = serdes_type - PEX0;
tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
first_busno = next_busno;
if ((tmp & 0x7f) != 0x7e) {
DEBUG_INIT_S("PCIe, Idx ");
DEBUG_INIT_D(pex_idx, 1);
DEBUG_INIT_S(": detected no link\n");
continue;
}
next_busno++;
temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
(pex_idx, PEX_LINK_CAPABILITY_REG)));
temp_pex_reg &= 0xf;
if (temp_pex_reg != 0x2)
continue;
temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
pex_idx,
PEX_LINK_CTRL_STAT_REG)) &
0xf0000) >> 16;
/* Check if the link established is GEN1 */
DEBUG_INIT_FULL_S
("Checking if the link established is gen1\n");
if (temp_reg != 0x1)
continue;
pex_local_bus_num_set(pex_idx, first_busno);
pex_local_dev_num_set(pex_idx, 1);
DEBUG_INIT_FULL_S("PCIe, Idx ");
DEBUG_INIT_FULL_D(pex_idx, 1);
DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
/* link is Gen1, check the EP capability */
addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
if (addr == 0xff) {
DEBUG_INIT_FULL_C
("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
pex_idx, 1);
continue;
}
while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
& 0xff) != 0x10) {
addr = (pex_config_read(pex_idx, first_busno, 0,
0, addr) & 0xff00) >> 8;
}
/* Check for Gen2 and above */
if ((pex_config_read(pex_idx, first_busno, 0, 0,
addr + 0xc) & 0xf) < 0x2) {
DEBUG_INIT_S("PCIe, Idx ");
DEBUG_INIT_D(pex_idx, 1);
DEBUG_INIT_S(": remains Gen1\n");
continue;
}
tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
tmp &= ~(BIT(0) | BIT(1));
tmp |= BIT(1);
tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
tmp = reg_read(PEX_CTRL_REG(pex_idx));
DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
tmp |= BIT(10);
reg_write(PEX_CTRL_REG(pex_idx), tmp);
DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
/*
* We need to wait 10ms before reading the PEX_DBG_STATUS_REG
* in order not to read the status of the former state
*/
mdelay(10);
DEBUG_INIT_S("PCIe, Idx ");
DEBUG_INIT_D(pex_idx, 1);
DEBUG_INIT_S
(": Link upgraded to Gen2 based on client capabilities\n");
}
/* Update pex DEVICE ID */
ctrl_mode = sys_env_model_get();
for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
/* configuration for PEX only */
if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
(serdes_type != PEX2) && (serdes_type != PEX3))
continue;
if ((serdes_type != PEX0) &&
((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
/* for PEX by4 - relevant for the first port only */
continue;
}
pex_idx = serdes_type - PEX0;
dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
(pex_idx, PEX_DEVICE_AND_VENDOR_ID));
dev_id &= 0xffff;
dev_id |= ((ctrl_mode << 16) & 0xffff0000);
reg_write(PEX_CFG_DIRECT_ACCESS
(pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
}
DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
return MV_OK;
}
int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
{
u32 pex_status;
DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
if (bus_num >= MAX_PEX_BUSSES) {
DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
bus_num, 4);
return MV_BAD_PARAM;
}
pex_status = reg_read(PEX_STATUS_REG(pex_if));
pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
pex_status |=
(bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
reg_write(PEX_STATUS_REG(pex_if), pex_status);
return MV_OK;
}
int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
{
u32 pex_status;
DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
pex_status = reg_read(PEX_STATUS_REG(pex_if));
pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
pex_status |=
(dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
reg_write(PEX_STATUS_REG(pex_if), pex_status);
return MV_OK;
}
/*
* pex_config_read - Read from configuration space
*
* DESCRIPTION:
* This function performs a 32 bit read from PEX configuration space.
* It supports both type 0 and type 1 of Configuration Transactions
* (local and over bridge). In order to read from local bus segment, use
* bus number retrieved from pex_local_bus_num_get(). Other bus numbers
* will result configuration transaction of type 1 (over bridge).
*
* INPUT:
* pex_if - PEX interface number.
* bus - PEX segment bus number.
* dev - PEX device number.
* func - Function number.
* reg_offs - Register offset.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit register data, 0xffffffff on error
*/
u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
{
u32 pex_data = 0;
u32 local_dev, local_bus;
u32 pex_status;
pex_status = reg_read(PEX_STATUS_REG(pex_if));
local_dev =
((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
local_bus =
((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
/*
* In PCI Express we have only one device number
* and this number is the first number we encounter
* else that the local_dev
* spec pex define return on config read/write on any device
*/
if (bus == local_bus) {
if (local_dev == 0) {
/*
* if local dev is 0 then the first number we encounter
* after 0 is 1
*/
if ((dev != 1) && (dev != local_dev))
return MV_ERROR;
} else {
/*
* if local dev is not 0 then the first number we
* encounter is 0
*/
if ((dev != 0) && (dev != local_dev))
return MV_ERROR;
}
}
/* Creating PEX address to be passed */
pex_data = (bus << PXCAR_BUS_NUM_OFFS);
pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
/* Legacy register space */
pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
/* Extended register space */
pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
pex_data |= PXCAR_CONFIG_EN;
/* Write the address to the PEX configuration address register */
reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
/*
* In order to let the PEX controller absorbed the address
* of the read transaction we perform a validity check that
* the address was written
*/
if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
return MV_ERROR;
/* Cleaning Master Abort */
reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
PXSAC_MABORT);
/* Read the Data returned in the PEX Data register */
pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
return pex_data;
}

68
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
View File

@ -6,35 +6,13 @@
#ifndef _CTRL_PEX_H
#define _CTRL_PEX_H
#include <pci.h>
#include "high_speed_env_spec.h"
/* Sample at Reset */
#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
/* Direct access to PEX0 Root Port's PCIe Capability structure */
#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
/* PCI Express Control and Status Registers */
#define MAX_PEX_BUSSES 256
#define MISC_REGS_OFFSET 0x18200
#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
(0x40000 + ((if) - 1) * 0x4000) : \
0x80000)
#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if))
#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64)
#define PEX_LINK_CAPABILITY_REG 0x6c
#define PEX_LINK_CTRL_STAT_REG 0x70
#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
/* PEX_CAPABILITIES_REG fields */
/* SOC_CONTROL_REG1 fields */
#define PCIE0_ENABLE_OFFS 0
#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
#define PCIE1_ENABLE_OFFS 1
@ -44,45 +22,7 @@
#define PCIE3_ENABLE_OFFS 3
#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
/* Controller revision info */
#define PEX_DEVICE_AND_VENDOR_ID 0x000
#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
/* PCI Express Configuration Address Register */
#define PXCAR_REG_NUM_OFFS 2
#define PXCAR_REG_NUM_MAX 0x3f
#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \
PXCAR_REG_NUM_OFFS)
#define PXCAR_FUNC_NUM_OFFS 8
#define PXCAR_FUNC_NUM_MAX 0x7
#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \
PXCAR_FUNC_NUM_OFFS)
#define PXCAR_DEVICE_NUM_OFFS 11
#define PXCAR_DEVICE_NUM_MAX 0x1f
#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \
PXCAR_DEVICE_NUM_OFFS)
#define PXCAR_BUS_NUM_OFFS 16
#define PXCAR_BUS_NUM_MAX 0xff
#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \
PXCAR_BUS_NUM_OFFS)
#define PXCAR_EXT_REG_NUM_OFFS 24
#define PXCAR_EXT_REG_NUM_MAX 0xf
#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8)
#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc)
#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS)
#define PXCAR_CONFIG_EN BIT(31)
#define PEX_STATUS_AND_COMMAND 0x004
#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */
int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
void board_pex_config(void);
#endif

42
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
View File

@ -1712,7 +1712,7 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
(serdes_mode == PEX_END_POINT_X1);
pex_idx = serdes_type - PEX0;
if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
if (serdes_type == PEX0) {
/* For PEX by 4, init only the PEX 0 */
reg_data = reg_read(SOC_CONTROL_REG1);
if (is_pex_by1 == 1)
@ -1721,32 +1721,20 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
reg_data &= ~0x4000;
reg_write(SOC_CONTROL_REG1, reg_data);
reg_data =
reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
0x6c));
reg_data &= ~0x3f0;
if (is_pex_by1 == 1)
reg_data |= 0x10;
else
reg_data |= 0x40;
reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
reg_data);
reg_data =
reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
0x6c));
reg_data &= ~0xf;
reg_data |= 0x2;
reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
reg_data);
reg_data =
reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
0x70));
reg_data &= ~0x40;
reg_data |= 0x40;
reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
reg_data);
/*
* Set Maximum Link Width to X1 or X4 in Root
* Port's PCIe Link Capability register.
* This register is read-only but if is not set
* correctly then access to PCI config space of
* endpoint card behind this Root Port does not
* work.
*/
reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET +
PCI_EXP_LNKCAP);
reg_data &= ~PCI_EXP_LNKCAP_MLW;
reg_data |= (is_pex_by1 ? 1 : 4) << 4;
reg_write(PEX0_RP_PCIE_CFG_OFFSET +
PCI_EXP_LNKCAP, reg_data);
}
CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));

79
arch/arm/mach-sunxi/Kconfig
View File

@ -88,17 +88,6 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE
feature.
endif
config SUN6I_P2WI
bool "Allwinner sun6i internal P2WI controller"
help
If you say yes to this option, support will be included for the
P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
SOCs.
The P2WI looks like an SMBus controller (which supports only byte
accesses), except that it only supports one slave device.
This interface is used to connect to specific PMIC devices (like the
AXP221).
config SUN6I_PRCM
bool
help
@ -106,19 +95,13 @@ config SUN6I_PRCM
in A31 SoC.
config AXP_PMIC_BUS
bool "Sunxi AXP PMIC bus access helpers"
bool
select DM_PMIC if DM_I2C
select PMIC_AXP if DM_I2C
help
Select this PMIC bus access helpers for Sunxi platform PRCM or other
AXP family PMIC devices.
config SUN8I_RSB
bool "Allwinner sunXi Reduced Serial Bus Driver"
help
Say y here to enable support for Allwinner's Reduced Serial Bus
(RSB) support. This controller is responsible for communicating
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
@ -182,7 +165,6 @@ endif
config MACH_SUNXI_H3_H5
bool
select DM_I2C
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_DRAM_DW
@ -232,10 +214,11 @@ config MACH_SUN6I
select ARCH_SUPPORT_PSCI
select DRAM_SUN6I
select PHY_SUN4I_USB
select SUN6I_P2WI
select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SYS_I2C_SUN6I_P2WI
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN7I
@ -260,8 +243,10 @@ config MACH_SUN8I_A23
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A23
select PHY_SUN4I_USB
select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
@ -273,8 +258,10 @@ config MACH_SUN8I_A33
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A33
select PHY_SUN4I_USB
select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SYS_I2C_SUN8I_RSB
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
imply CONS_INDEX_5 if !DM_SERIAL
@ -283,10 +270,12 @@ config MACH_SUN8I_A83T
select CPU_V7A
select DRAM_SUN8I_A83T
select PHY_SUN4I_USB
select SPL_I2C
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select MMC_SUNXI_HAS_MODE_SWITCH
select SUPPORT_SPL
select SYS_I2C_SUN8I_RSB
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
@ -327,16 +316,15 @@ config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7A
select DRAM_SUN9I
select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUN8I_RSB
select SUPPORT_SPL
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SPI
select DM_I2C
select DM_SPI if SPI
select DM_SPI_FLASH
select PHY_SUN4I_USB
@ -377,7 +365,6 @@ endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
select SUN8I_RSB
select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
@ -677,24 +664,11 @@ config MMC3_CD_PIN
---help---
See MMC0_CD_PIN help text.
config MMC1_PINS
string "Pins for mmc1"
default ""
config MMC1_PINS_PH
bool "Pins for mmc1 are on Port H"
depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
---help---
Set the pins used for mmc1, when applicable. This takes a string in the
format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
config MMC2_PINS
string "Pins for mmc2"
default ""
---help---
See MMC1_PINS help text.
config MMC3_PINS
string "Pins for mmc3"
default ""
---help---
See MMC1_PINS help text.
Select this option for boards where mmc1 uses the Port H pinmux.
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
@ -807,6 +781,7 @@ endif
config AXP_GPIO
bool "Enable support for gpio-s on axp PMICs"
depends on AXP_PMIC_BUS
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
@ -932,27 +907,17 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO_SUNXI
select CMD_I2C
select DM_I2C_GPIO
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
config VIDEO_LCD_PANEL_I2C_SDA
string "LCD panel i2c interface SDA pin"
config VIDEO_LCD_PANEL_I2C_NAME
string "LCD panel i2c interface node name"
depends on VIDEO_LCD_PANEL_I2C
default "PG12"
default "i2c@0"
---help---
Set the SDA pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_LCD_PANEL_I2C_SCL
string "LCD panel i2c interface SCL pin"
depends on VIDEO_LCD_PANEL_I2C
default "PG10"
---help---
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Set the device tree node name for the LCD i2c interface.
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig

2
arch/arm/mach-sunxi/Makefile
View File

@ -11,10 +11,8 @@ obj-y += clock.o
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
obj-$(CONFIG_SUN6I_P2WI) += p2wi.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
obj-$(CONFIG_SUN8I_RSB) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o

3
arch/arm/mach-sunxi/board.c
View File

@ -21,7 +21,6 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
@ -339,7 +338,7 @@ void board_init_f(ulong dummy)
spl_init();
preloader_console_init();
#ifdef CONFIG_SPL_I2C
#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif

1
arch/arm/mach-sunxi/clock.c
View File

@ -10,7 +10,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/gtbus.h>
#include <asm/arch/sys_proto.h>

1
arch/arm/mach-sunxi/clock_sun4i.c
View File

@ -12,7 +12,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_SPL_BUILD

117
arch/arm/mach-sunxi/p2wi.c
View File

@ -1,117 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Sunxi A31 Power Management Unit
*
* (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
* http://linux-sunxi.org
*
* Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
*
* (C) Copyright 2006-2013
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Berg Xing <bergxing@allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
*/
#include <common.h>
#include <errno.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/p2wi.h>
#include <asm/arch/prcm.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
void p2wi_init(void)
{
struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
/* Enable p2wi and PIO clk, and de-assert their resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
writel(P2WI_CTRL_RESET, &p2wi->ctrl);
sdelay(0x100);
writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
&p2wi->cc);
}
int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
{
struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
unsigned long tmo = timer_get_us() + 1000000;
writel(P2WI_PM_DEV_ADDR(slave_addr) |
P2WI_PM_CTRL_ADDR(ctrl_reg) |
P2WI_PM_INIT_DATA(init_data) |
P2WI_PM_INIT_SEND,
&p2wi->pm);
while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
if (timer_get_us() > tmo)
return -ETIME;
}
return 0;
}
static int p2wi_await_trans(void)
{
struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
unsigned long tmo = timer_get_us() + 1000000;
int ret;
u8 reg;
while (1) {
reg = readl(&p2wi->status);
if (reg & P2WI_STAT_TRANS_ERR) {
ret = -EIO;
break;
}
if (reg & P2WI_STAT_TRANS_DONE) {
ret = 0;
break;
}
if (timer_get_us() > tmo) {
ret = -ETIME;
break;
}
}
writel(reg, &p2wi->status); /* Clear status bits */
return ret;
}
int p2wi_read(const u8 addr, u8 *data)
{
struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
int ret;
writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
writel(P2WI_DATA_NUM_BYTES(1) |
P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
ret = p2wi_await_trans();
*data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
return ret;
}
int p2wi_write(const u8 addr, u8 data)
{
struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
return p2wi_await_trans();
}

107
arch/arm/mach-sunxi/pmic_bus.c
View File

@ -8,10 +8,13 @@
* axp223 uses the rsb bus, these functions abstract this.
*/
#include <axp_pmic.h>
#include <common.h>
#include <dm.h>
#include <asm/arch/p2wi.h>
#include <asm/arch/rsb.h>
#include <i2c.h>
#include <power/pmic.h>
#include <asm/arch/pmic_bus.h>
#define AXP152_I2C_ADDR 0x30
@ -21,80 +24,80 @@
#define AXP305_I2C_ADDR 0x36
#define AXP221_CHIP_ADDR 0x68
#define AXP221_CTRL_ADDR 0x3e
#define AXP221_INIT_DATA 0x3e
/* AXP818 device and runtime addresses are same as AXP223 */
#define AXP223_DEVICE_ADDR 0x3a3
#define AXP223_RUNTIME_ADDR 0x2d
#if CONFIG_IS_ENABLED(PMIC_AXP)
static struct udevice *pmic;
#else
static int pmic_i2c_address(void)
{
if (IS_ENABLED(CONFIG_AXP152_POWER))
return AXP152_I2C_ADDR;
if (IS_ENABLED(CONFIG_AXP305_POWER))
return AXP305_I2C_ADDR;
/* Other AXP2xx and AXP8xx variants */
return AXP209_I2C_ADDR;
}
#endif
int pmic_bus_init(void)
{
/* This cannot be 0 because it is used in SPL before BSS is ready */
static int needs_init = 1;
__maybe_unused int ret;
int ret = 0;
if (!needs_init)
return 0;
#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
AXP221_INIT_DATA);
# elif defined CONFIG_MACH_SUN8I_R40
/* Nothing. R40 uses the AXP221s in I2C mode */
ret = 0;
# else
ret = rsb_init();
if (ret)
return ret;
#if CONFIG_IS_ENABLED(PMIC_AXP)
ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic),
&pmic);
#else
if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) {
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR,
AXP_PMIC_MODE_REG,
AXP_PMIC_MODE_P2WI);
} else if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) {
ret = rsb_init();
if (ret)
return ret;
ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
# endif
if (ret)
return ret;
ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR,
AXP_PMIC_PRI_RUNTIME_ADDR);
}
#endif
needs_init = 0;
return 0;
needs_init = ret;
return ret;
}
int pmic_bus_read(u8 reg, u8 *data)
{
#ifdef CONFIG_AXP152_POWER
return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
#elif defined CONFIG_AXP209_POWER
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
#elif defined CONFIG_AXP305_POWER
return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1);
#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
# elif defined CONFIG_MACH_SUN8I_R40
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
# else
return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
# endif
#if CONFIG_IS_ENABLED(PMIC_AXP)
return pmic_read(pmic, reg, data, 1);
#else
if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
return p2wi_read(reg, data);
if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
#endif
}
int pmic_bus_write(u8 reg, u8 data)
{
#ifdef CONFIG_AXP152_POWER
return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
#elif defined CONFIG_AXP209_POWER
return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
#elif defined CONFIG_AXP305_POWER
return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1);
#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
# elif defined CONFIG_MACH_SUN8I_R40
return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
# else
return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
# endif
#if CONFIG_IS_ENABLED(PMIC_AXP)
return pmic_write(pmic, reg, &data, 1);
#else
if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI))
return p2wi_write(reg, data);
if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
#endif
}

175
arch/arm/mach-sunxi/rsb.c
View File

@ -1,175 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
*
* Based on allwinner u-boot sources rsb code which is:
* (C) Copyright 2007-2013
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* lixiang <lixiang@allwinnertech.com>
*/
#include <common.h>
#include <errno.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>
static int rsb_set_device_mode(void);
static void rsb_cfg_io(void)
{
#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
#elif defined CONFIG_MACH_SUN9I
sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
#else
#error unsupported MACH_SUNXI
#endif
}
static void rsb_set_clk(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
u32 div = 0;
u32 cd_odly = 0;
/* Source is Hosc24M, set RSB clk to 3Mhz */
div = 24000000 / 3000000 / 2 - 1;
cd_odly = div >> 1;
if (!cd_odly)
cd_odly = 1;
writel((cd_odly << 8) | div, &rsb->ccr);
}
int rsb_init(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
/* Enable RSB and PIO clk, and de-assert their resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
/* Setup external pins */
rsb_cfg_io();
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
return rsb_set_device_mode();
}
static int rsb_await_trans(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 1000000;
u32 stat;
int ret;
while (1) {
stat = readl(&rsb->stat);
if (stat & RSB_STAT_LBSY_INT) {
ret = -EBUSY;
break;
}
if (stat & RSB_STAT_TERR_INT) {
ret = -EIO;
break;
}
if (stat & RSB_STAT_TOVER_INT) {
ret = 0;
break;
}
if (timer_get_us() > tmo) {
ret = -ETIME;
break;
}
}
writel(stat, &rsb->stat); /* Clear status bits */
return ret;
}
static int rsb_set_device_mode(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 1000000;
writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
&rsb->dmcr);
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
if (timer_get_us() > tmo)
return -ETIME;
}
return rsb_await_trans();
}
static int rsb_do_trans(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
return rsb_await_trans();
}
int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
return rsb_do_trans();
}
int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
writel(reg_addr, &rsb->addr);
writel(data, &rsb->data);
writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
return rsb_do_trans();
}
int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
int ret;
writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
writel(reg_addr, &rsb->addr);
writel(RSB_CMD_BYTE_READ, &rsb->cmd);
ret = rsb_do_trans();
if (ret)
return ret;
*data = readl(&rsb->data) & 0xff;
return 0;
}

147
arch/arm/mach-tegra/dt-setup.c
View File

@ -4,6 +4,9 @@
*/
#include <common.h>
#include <fdtdec.h>
#include <stdlib.h>
#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/gpu.h>
/*
@ -31,3 +34,147 @@ int ft_system_setup(void *blob, struct bd_info *bd)
return 0;
}
#if defined(CONFIG_ARM64)
void ft_mac_address_setup(void *fdt)
{
const void *cboot_fdt = (const void *)cboot_boot_x0;
uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
const char *path;
int offset, err;
err = cboot_get_ethaddr(cboot_fdt, local_mac);
if (err < 0)
memset(local_mac, 0, ETH_ALEN);
path = fdt_get_alias(fdt, "ethernet");
if (!path)
return;
debug("ethernet alias found: %s\n", path);
offset = fdt_path_offset(fdt, path);
if (offset < 0) {
printf("ethernet alias points to absent node %s\n", path);
return;
}
if (is_valid_ethaddr(local_mac)) {
err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
ETH_ALEN);
if (!err)
debug("Local MAC address set: %pM\n", local_mac);
}
if (eth_env_get_enetaddr("ethaddr", mac)) {
if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
err = fdt_setprop(fdt, offset, "mac-address", mac,
ETH_ALEN);
if (!err)
debug("MAC address set: %pM\n", mac);
}
}
}
static int ft_copy_carveout(void *dst, const void *src, const char *node)
{
const char *names = "memory-region-names";
struct fdt_memory carveout;
unsigned int index = 0;
int err, offset, len;
const void *prop;
while (true) {
const char **compatibles = NULL;
unsigned int num_compatibles;
unsigned long flags;
char *copy = NULL;
const char *name;
err = fdtdec_get_carveout(src, node, "memory-region", index,
&carveout, &name, &compatibles,
&num_compatibles, &flags);
if (err < 0) {
if (err != -FDT_ERR_NOTFOUND)
printf("failed to get carveout for %s: %d\n",
node, err);
else
break;
return err;
}
if (name) {
const char *ptr = strchr(name, '@');
if (ptr) {
copy = strndup(name, ptr - name);
name = copy;
}
} else {
name = "carveout";
}
err = fdtdec_set_carveout(dst, node, "memory-region", index,
&carveout, name, compatibles,
num_compatibles, flags);
if (err < 0) {
printf("failed to set carveout for %s: %d\n", node,
err);
return err;
}
if (copy)
free(copy);
index++;
}
offset = fdt_path_offset(src, node);
if (offset < 0) {
debug("failed to find source offset for %s: %s\n", node,
fdt_strerror(err));
return err;
}
prop = fdt_getprop(src, offset, names, &len);
if (prop) {
offset = fdt_path_offset(dst, node);
if (offset < 0) {
debug("failed to find destination offset for %s: %s\n",
node, fdt_strerror(err));
return err;
}
err = fdt_setprop(dst, offset, "memory-region-names", prop,
len);
if (err < 0) {
debug("failed to copy \"%s\" property: %s\n", names,
fdt_strerror(err));
return err;
}
}
return 0;
}
void ft_carveout_setup(void *fdt, const char * const *nodes, unsigned int count)
{
const void *cboot_fdt = (const void *)cboot_boot_x0;
unsigned int i;
int err;
for (i = 0; i < count; i++) {
printf("copying carveout for %s...\n", nodes[i]);
err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
if (err < 0) {
if (err != -FDT_ERR_NOTFOUND)
printf("failed to copy carveout for %s: %d\n",
nodes[i], err);
continue;
}
}
}
#endif

2
arch/microblaze/lib/bootm.c
View File

@ -75,7 +75,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
static void boot_prep_linux(bootm_headers_t *images)
{
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");

1
arch/mips/mach-ath79/Kconfig
View File

@ -20,6 +20,7 @@ config SOC_AR934X
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select USB_EHCI_IS_TDI if USB_EHCI_HCD
help
This supports QCA/Atheros ar934x family SOCs.

4
arch/nds32/lib/bootm.c
View File

@ -69,7 +69,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
@ -110,7 +110,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
#endif
}
cleanup_before_linux();
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
theKernel(0, machid, (unsigned long)images->ft_addr);
else
theKernel(0, machid, bd->bi_boot_params);

42
arch/riscv/cpu/ax25/cpu.c
View File

@ -9,6 +9,22 @@
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
#include <asm/csr.h>
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MARCHID 0xf12
#define V5_MCACHE_CTL_IC_EN_OFFSET 0
#define V5_MCACHE_CTL_DC_EN_OFFSET 1
#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
/*
* cleanup_before_linux() is called just before we call linux
@ -27,3 +43,29 @@ int cleanup_before_linux(void)
return 0;
}
void harts_early_init(void)
{
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/*
* Check DC_COHEN_EN, if cannot write to mcache_ctl,
* we assume this bitmap not support L2 CM
*/
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
/* Wait for DC_COHSTA bit be set */
while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
}
}
}

16
arch/riscv/cpu/cpu.c
View File

@ -6,6 +6,7 @@
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <dm/lists.h>
#include <init.h>
#include <log.h>
#include <asm/encoding.h>
@ -16,9 +17,6 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
#ifdef CONFIG_OF_PRIOR_STAGE
phys_addr_t prior_stage_fdt_address __section(".data");
#endif
#ifndef CONFIG_XIP
u32 hart_lottery __section(".data") = 0;
@ -138,7 +136,17 @@ int arch_cpu_init_dm(void)
int arch_early_init_r(void)
{
return riscv_cpu_probe();
int ret;
ret = riscv_cpu_probe();
if (ret)
return ret;
if (IS_ENABLED(CONFIG_SYSRESET_SBI))
device_bind_driver(gd->dm_root, "sbi-sysreset",
"sbi-sysreset", NULL);
return 0;
}
/**

5
arch/riscv/cpu/start.S
View File

@ -142,11 +142,6 @@ call_harts_early_init:
bnez tp, secondary_hart_loop
#endif
#ifdef CONFIG_OF_PRIOR_STAGE
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
#endif
jal board_init_f_init_reserve
SREG s1, GD_FIRMWARE_FDT_ADDR(gp)

6
arch/riscv/dts/binman.dtsi
View File

@ -48,7 +48,7 @@
};
};
#ifndef CONFIG_OF_PRIOR_STAGE
#ifndef CONFIG_OF_BOARD
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
@ -60,7 +60,7 @@
configurations {
default = "conf-1";
#ifndef CONFIG_OF_PRIOR_STAGE
#ifndef CONFIG_OF_BOARD
@conf-SEQ {
#else
conf-1 {
@ -68,7 +68,7 @@
description = "NAME";
firmware = "opensbi";
loadables = "uboot";
#ifndef CONFIG_OF_PRIOR_STAGE
#ifndef CONFIG_OF_BOARD
fdt = "fdt-SEQ";
#endif
};

16
arch/riscv/include/asm/io.h
View File

@ -44,15 +44,15 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
#define __arch_getb(a) (*(unsigned char *)(a))
#define __arch_getw(a) (*(unsigned short *)(a))
#define __arch_getl(a) (*(unsigned int *)(a))
#define __arch_getq(a) (*(unsigned long long *)(a))
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_getq(a) (*(volatile unsigned long long *)(a))
#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)

40
arch/riscv/include/asm/sbi.h
View File

@ -12,7 +12,6 @@
#include <linux/types.h>
enum sbi_ext_id {
#ifdef CONFIG_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@ -22,11 +21,12 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
};
enum sbi_ext_base_fid {
@ -51,6 +51,41 @@ enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
};
enum sbi_ext_hsm_fid {
SBI_EXT_HSM_HART_START = 0,
SBI_EXT_HSM_HART_STOP,
SBI_EXT_HSM_HART_STATUS,
SBI_EXT_HSM_HART_SUSPEND,
};
enum sbi_hsm_hart_status {
SBI_HSM_HART_STATUS_STARTED = 0,
SBI_HSM_HART_STATUS_STOPPED,
SBI_HSM_HART_STATUS_START_PENDING,
SBI_HSM_HART_STATUS_STOP_PENDING,
SBI_HSM_HART_STATUS_SUSPEND_PENDING,
SBI_HSM_HART_STATUS_RESUME_PENDING,
};
enum sbi_ext_srst_fid {
SBI_EXT_SRST_RESET = 0,
};
enum sbi_srst_reset_type {
SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
SBI_SRST_RESET_TYPE_COLD_REBOOT,
SBI_SRST_RESET_TYPE_WARM_REBOOT,
};
enum sbi_srst_reset_reason {
SBI_SRST_RESET_REASON_NONE = 0,
SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#ifdef CONFIG_SBI_V01
@ -118,5 +153,6 @@ void sbi_set_timer(uint64_t stime_value);
long sbi_get_spec_version(void);
int sbi_get_impl_id(void);
int sbi_probe_extension(int ext);
void sbi_srst_reset(unsigned long type, unsigned long reason);
#endif

4
arch/riscv/lib/bootm.c
View File

@ -64,7 +64,7 @@ static void announce_and_cleanup(int fake)
static void boot_prep_linux(bootm_headers_t *images)
{
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
@ -96,7 +96,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
announce_and_cleanup(fake);
if (!fake) {
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
(ulong)images->ft_addr, 0, 0);

7
arch/riscv/lib/fdt_fixup.c
View File

@ -31,7 +31,6 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
fdt_addr_t addr;
fdt_size_t size;
int offset, node, err, rmem_offset;
bool nomap = true;
char basename[32] = {0};
int bname_len;
int max_len = sizeof(basename);
@ -76,14 +75,12 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
pmp_mem.start = addr;
pmp_mem.end = addr + size - 1;
err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
&phandle, false);
NULL, 0, &phandle, 0);
if (err < 0 && err != -FDT_ERR_EXISTS) {
log_err("failed to add reserved memory: %d\n", err);
return err;
}
if (!fdt_getprop(src, node, "no-map", NULL))
nomap = false;
if (nomap) {
if (fdt_getprop(src, node, "no-map", NULL)) {
rmem_offset = fdt_node_offset_by_phandle(dst, phandle);
fdt_setprop_empty(dst, rmem_offset, "no-map");
}

12
arch/riscv/lib/sbi.c
View File

@ -108,6 +108,18 @@ int sbi_probe_extension(int extid)
return -ENOTSUPP;
}
/**
* sbi_srst_reset() - invoke system reset extension
*
* @type: type of reset
* @reason: reason for reset
*/
void sbi_srst_reset(unsigned long type, unsigned long reason)
{
sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
0, 0, 0, 0);
}
#ifdef CONFIG_SBI_V01
/**

Some files were not shown because too many files have changed in this diff Show More