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powerpc: p1022ds: add TPL for p1022ds nand boot
TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Ying Zhang
York Sun
parent
3aa29de0b0
commit
5d97fe2a04
@ -100,21 +100,37 @@ void board_init_r(gd_t *gd, ulong dest_addr)
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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#ifndef CONFIG_SPL_NAND_BOOT
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env_init();
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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#endif
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/* relocate environment function pointers etc. */
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->env_valid = 1;
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#else
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env_relocate();
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#endif
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i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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gd->ram_size = initdram(0);
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#ifdef CONFIG_SPL_NAND_BOOT
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puts("Tertiary program loader running in sram...");
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#else
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puts("Second program loader running in sram...\n");
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_SPI_BOOT)
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spi_boot();
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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@ -12,51 +12,6 @@
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#include <asm/fsl_ddr_sdram.h>
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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void sdram_init(void)
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{
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volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
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#endif
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
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/* Set, but do not enable the memory */
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
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&ddr->sdram_cfg);
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in_be32(&ddr->sdram_cfg);
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udelay(500);
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/* Let the controller go */
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
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in_be32(&ddr->sdram_cfg);
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set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
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}
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const static u32 sysclk_tbl[] = {
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66666000, 7499900, 83332500, 8999900,
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99999000, 11111000, 12499800, 13333200
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@ -68,6 +23,10 @@ void board_init_f(ulong bootflag)
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u32 plat_ratio, sys_clk, bus_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
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set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
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set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
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#endif
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/* for FPGA */
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
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@ -83,9 +42,6 @@ void board_init_f(ulong bootflag)
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puts("\nNAND boot... ");
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/* Initialize the DDR3 */
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sdram_init();
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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@ -96,6 +52,7 @@ void board_init_f(ulong bootflag)
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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puts("\nSecond program loader running in sram...");
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nand_boot();
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}
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@ -23,6 +23,7 @@ COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
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COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
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COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
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COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
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COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o
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else # not spl
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@ -34,7 +34,11 @@ static void nand_wait(void)
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}
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}
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#ifdef CONFIG_TPL_BUILD
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int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
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#else
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static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
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#endif
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{
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fsl_lbc_t *regs = LBC_BASE_ADDR;
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uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
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@ -113,6 +117,15 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
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return 0;
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}
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/*
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* Defines a static function nand_load_image() here, because non-static makes
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* the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
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*/
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#ifndef CONFIG_TPL_BUILD
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#define nand_spl_load_image(offs, uboot_size, vdst) \
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nand_load_image(offs, uboot_size, vdst)
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#endif
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/*
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* The main entry for NAND booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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@ -124,17 +137,17 @@ void nand_boot(void)
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
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CONFIG_SYS_NAND_U_BOOT_SIZE,
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(void *)CONFIG_SYS_NAND_U_BOOT_DST);
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nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
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CONFIG_SYS_NAND_U_BOOT_SIZE,
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(void *)CONFIG_SYS_NAND_U_BOOT_DST);
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#ifdef CONFIG_NAND_ENV_DST
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nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST);
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST);
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#ifdef CONFIG_ENV_OFFSET_REDUND
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nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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#endif
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#endif
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@ -78,22 +78,43 @@
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#ifdef CONFIG_NAND
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#define CONFIG_SPL
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#define CONFIG_TPL
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SPL_NAND_BOOT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xfffff000
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#define CONFIG_SPL_MAX_SIZE 4096
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 4096
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
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#endif
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_TPL_PAD_TO 0x20000
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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/* High Level Configuration Options */
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@ -267,11 +288,11 @@
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
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#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
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/* NAND flash config */
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@ -348,6 +369,25 @@
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
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#elif defined(CONFIG_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
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#else
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
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#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
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#endif
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#endif
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#endif
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@ -596,9 +636,14 @@
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#elif defined(CONFIG_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
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#else
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#endif
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET (1024 * 1024)
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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