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ppc4xx: Adapt DLVision 10G to new FPGA firmware
Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
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8aa50540e4
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5cb4100f58
@ -110,6 +110,11 @@ int board_early_init_f(void)
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
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u16 *reflection_target = &fpga->reflection_low;
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#else
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u16 *reflection_target = &fpga->reflection_high;
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#endif
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/*
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* wait for fpga out of reset
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*/
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@ -117,9 +122,11 @@ int board_early_init_f(void)
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while (1) {
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out_le16(&fpga->reflection_low,
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REFLECTION_TESTPATTERN);
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if (in_le16(&fpga->reflection_high) ==
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if (in_le16(reflection_target) ==
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REFLECTION_TESTPATTERN_INV)
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break;
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udelay(100000);
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if (ctr++ > 5) {
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gd->fpga_state[k] |=
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@ -34,6 +34,8 @@
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define LATCH2_MC2_PRESENT_N 0x0080
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#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
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enum {
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UNITTYPE_VIDEO_USER = 0,
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UNITTYPE_MAIN_USER = 1,
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@ -63,6 +65,20 @@ enum {
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RAM_DDR2_64 = 2,
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};
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static unsigned int get_hwver(void)
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{
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u16 latch3 = in_le16((void *)LATCH3_BASE);
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return latch3 & 0x0003;
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}
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static unsigned int get_mc2_present(void)
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{
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u16 latch2 = in_le16((void *)LATCH2_BASE);
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return !(latch2 & LATCH2_MC2_PRESENT_N);
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}
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static void print_fpga_info(unsigned dev)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
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@ -210,7 +226,6 @@ static void print_fpga_info(unsigned dev)
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int checkboard(void)
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{
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char *s = getenv("serial#");
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u16 latch2 = in_le16((void *)LATCH2_BASE);
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printf("Board: ");
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@ -224,7 +239,7 @@ int checkboard(void)
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puts("\n");
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print_fpga_info(0);
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if (!(latch2 & LATCH2_MC2_PRESENT_N))
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if (get_mc2_present())
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print_fpga_info(1);
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return 0;
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@ -234,15 +249,15 @@ int last_stage_init(void)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
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u16 versions = in_le16(&fpga->versions);
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u16 latch2 = in_le16((void *)LATCH2_BASE);
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if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
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return 0;
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if (!get_fpga_state(0))
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if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
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osd_probe(0);
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if (!(latch2 & LATCH2_MC2_PRESENT_N) && !get_fpga_state(1))
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if (get_mc2_present() &&
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(!get_fpga_state(1) || (get_hwver() == HWVER_101)))
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osd_probe(1);
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return 0;
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@ -136,6 +136,8 @@
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#define CONFIG_SYS_LATCH1_RESET 0xffcf
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#define CONFIG_SYS_LATCH1_BOOT 0xffff
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#define CONFIG_SYS_FPGA_NO_RFL_HI
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/*
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* FLASH organization
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*/
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@ -94,13 +94,11 @@ typedef struct ihs_fpga {
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u16 extended_interrupt; /* 0x001c */
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u16 reserved_1[9]; /* 0x001e */
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ihs_i2c_t i2c; /* 0x0030 */
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u16 reserved_2[35]; /* 0x0038 */
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u16 reflection_high; /* 0x007e */
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u16 reserved_3[15]; /* 0x0080 */
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u16 reserved_2[51]; /* 0x0038 */
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u16 videocontrol; /* 0x009e */
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u16 reserved_4[176]; /* 0x00a0 */
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u16 reserved_3[176]; /* 0x00a0 */
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ihs_osd_t osd; /* 0x0200 */
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u16 reserved_5[764]; /* 0x0208 */
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u16 reserved_4[764]; /* 0x0208 */
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u16 videomem; /* 0x0800 */
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} ihs_fpga_t;
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#endif
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