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mmc: remove the MMC_MODE_HC flag

Browse Source 
High capacity support is not a host capability, but a device capability
that is queried via the OCR. The flag in the operating conditions
request argument can just be set unconditionally. This matches the Linux
implementation.

[panto] Hand merged and renumbering MMC_MODE_DDR_52MHz.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
This commit is contained in:
Rob Herring 2015-03-23 17:56:59 -05:00 committed by Pantelis Antoniou
parent bd47c13583
commit 5a20397b00
14 changed files with 12 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/mmc/dw_mmc.c
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@ -388,7 +388,7 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
host->cfg.host_caps |= MMC_MODE_4BIT;
host->cfg.host_caps &= ~MMC_MODE_8BIT;
}
host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

2
drivers/mmc/fsl_esdhc.c
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@ -652,7 +652,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
return -1;
}
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
#endif

1
drivers/mmc/kona_sdhci.c
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@ -121,7 +121,6 @@ int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
host->name = "kona-sdhci";
host->ioaddr = reg_base;
host->quirks = quirks;
host->host_caps = MMC_MODE_HC;
if (init_kona_mmc_core(host)) {
free(host);

7
drivers/mmc/mmc.c
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@ -363,15 +363,12 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
cmd.cmdidx = MMC_CMD_SEND_OP_COND;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
if (use_arg && !mmc_host_is_spi(mmc)) {
cmd.cmdarg =
if (use_arg && !mmc_host_is_spi(mmc))
cmd.cmdarg = OCR_HCS |
(mmc->cfg->voltages &
(mmc->ocr & OCR_VOLTAGE_MASK)) |
(mmc->ocr & OCR_ACCESS_MODE);
if (mmc->cfg->host_caps & MMC_MODE_HC)
cmd.cmdarg |= OCR_HCS;
}
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;

2
drivers/mmc/mvebu_mmc.c
View File

@ -418,7 +418,7 @@ static struct mmc_config mvebu_mmc_cfg = {
.f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
.f_max = MVEBU_MMC_CLOCKRATE_MAX,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
.host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
MMC_MODE_HS_52MHz,
.part_type = PART_TYPE_DOS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,

3
drivers/mmc/mxsmmc.c
View File

@ -405,8 +405,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz

3
drivers/mmc/omap_hsmmc.c
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@ -651,8 +651,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
if (priv_data == NULL)
return -1;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_index) {
case 0:

2
drivers/mmc/s3c_sdi.c
View File

@ -298,7 +298,7 @@ int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
cfg->name = "S3C MMC";
cfg->ops = &s3cmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
cfg->f_min = 400000;
cfg->f_max = get_PCLK() / 2;
cfg->b_max = 0x80;

1
drivers/mmc/s5p_sdhci.c
View File

@ -76,7 +76,6 @@ static int s5p_sdhci_core_init(struct sdhci_host *host)
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
host->host_caps = MMC_MODE_HC;
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;

2
drivers/mmc/sh_mmcif.c
View File

@ -577,7 +577,7 @@ static struct mmc_config sh_mmcif_cfg = {
.name = DRIVER_NAME,
.ops = &sh_mmcif_ops,
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT | MMC_MODE_HC,
MMC_MODE_8BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

2
drivers/mmc/sunxi_mmc.c
View File

@ -449,7 +449,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->f_min = 400000;

2
drivers/mmc/tegra_mmc.c
View File

@ -559,7 +559,7 @@ static int do_mmc_init(int dev_index)
host->cfg.host_caps |= MMC_MODE_8BIT;
if (host->width >= 4)
host->cfg.host_caps |= MMC_MODE_4BIT;
host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* min freq is for card identification, and is the highest

2
drivers/mmc/zynq_sdhci.c
View File

@ -29,8 +29,6 @@ int zynq_sdhci_init(phys_addr_t regbase)
SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->host_caps = MMC_MODE_HC;
add_sdhci(host, 52000000, 52000000 >> 9);
return 0;
}

3
include/mmc.h
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@ -55,8 +55,7 @@
#define MMC_MODE_4BIT (1 << 2)
#define MMC_MODE_8BIT (1 << 3)
#define MMC_MODE_SPI (1 << 4)
#define MMC_MODE_HC (1 << 5)
#define MMC_MODE_DDR_52MHz (1 << 6)
#define MMC_MODE_DDR_52MHz (1 << 5)
#define SD_DATA_4BIT 0x00040000