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net: fec_mxc: Driver cleanups
- Remove exctra space - Add space - Add tab space - Fix single line comments quotes - Fix 'CHECK: Avoid CamelCase' - Fix 'CHECK: Alignment should match open parenthesis' - Fix 'WARNING: line over 80 characters' - Re-arrage header include files Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
Stefano Babic
parent
60752ca86a
commit
567173a610
@ -12,17 +12,18 @@
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#include <dm.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include "fec_mxc.h"
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <linux/compiler.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/imx-common/sys_proto.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -80,11 +81,9 @@ static void swap_packet(uint32_t *packet, int length)
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}
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#endif
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/*
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* MII-interface related functions
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*/
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static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
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uint8_t regAddr)
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/* MII-interface related functions */
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static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
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uint8_t regaddr)
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{
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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@ -96,15 +95,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
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* programming the FEC's MII data register.
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*/
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writel(FEC_IEVENT_MII, ð->ievent);
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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reg = regaddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
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phy | reg, ð->mii_data);
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/*
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* wait for the related interrupt
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*/
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/* wait for the related interrupt */
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start = get_timer(0);
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while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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@ -113,17 +110,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
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}
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}
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/*
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* clear mii interrupt bit
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*/
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/* clear mii interrupt bit */
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writel(FEC_IEVENT_MII, ð->ievent);
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/*
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* it's now safe to read the PHY's register
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*/
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/* it's now safe to read the PHY's register */
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val = (unsigned short)readl(ð->mii_data);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
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regAddr, val);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
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regaddr, val);
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return val;
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}
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@ -154,22 +147,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
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debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
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}
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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
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uint8_t regAddr, uint16_t data)
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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
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uint8_t regaddr, uint16_t data)
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{
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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reg = regaddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
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/*
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* wait for the MII interrupt
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*/
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/* wait for the MII interrupt */
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start = get_timer(0);
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while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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@ -178,26 +169,24 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
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}
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}
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/*
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* clear MII interrupt bit
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*/
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/* clear MII interrupt bit */
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writel(FEC_IEVENT_MII, ð->ievent);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
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regAddr, data);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
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regaddr, data);
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return 0;
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}
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static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
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int regAddr)
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static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
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int regaddr)
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{
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return fec_mdio_read(bus->priv, phyAddr, regAddr);
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return fec_mdio_read(bus->priv, phyaddr, regaddr);
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}
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static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
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int regAddr, u16 data)
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static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
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int regaddr, u16 data)
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{
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return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
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return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
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}
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#ifndef CONFIG_PHYLIB
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@ -218,14 +207,12 @@ static int miiphy_restart_aneg(struct eth_device *dev)
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fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
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udelay(1000);
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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/* Set the auto-negotiation advertisement register bits */
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fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
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LPA_100FULL | LPA_100HALF | LPA_10FULL |
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LPA_10HALF | PHY_ANLPAR_PSB_802_3);
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LPA_100FULL | LPA_100HALF | LPA_10FULL |
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LPA_10HALF | PHY_ANLPAR_PSB_802_3);
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fec_mdio_write(eth, fec->phy_id, MII_BMCR,
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BMCR_ANENABLE | BMCR_ANRESTART);
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BMCR_ANENABLE | BMCR_ANRESTART);
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if (fec->mii_postcall)
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ret = fec->mii_postcall(fec->phy_id);
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@ -242,9 +229,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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struct ethernet_regs *eth = fec->bus->priv;
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/*
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* Wait for AN completion
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*/
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/* Wait for AN completion */
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start = get_timer(0);
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do {
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if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
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@ -255,7 +240,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
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status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
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if (status < 0) {
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printf("%s: Autonegotiation failed. status: %d\n",
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dev->name, status);
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dev->name, status);
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return -1;
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}
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} while (!(status & BMSR_LSTATUS));
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@ -352,15 +337,15 @@ static void fec_tbd_init(struct fec_priv *fec)
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/**
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* Mark the given read buffer descriptor as free
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* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
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* @param[in] pRbd buffer descriptor to mark free again
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* @param[in] prbd buffer descriptor to mark free again
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*/
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static void fec_rbd_clean(int last, struct fec_bd *pRbd)
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static void fec_rbd_clean(int last, struct fec_bd *prbd)
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{
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unsigned short flags = FEC_RBD_EMPTY;
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if (last)
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flags |= FEC_RBD_WRAP;
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writew(flags, &pRbd->status);
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writew(0, &pRbd->data_length);
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writew(flags, &prbd->status);
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writew(0, &prbd->data_length);
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}
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static int fec_get_hwaddr(int dev_id, unsigned char *mac)
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@ -389,37 +374,26 @@ static int fec_set_hwaddr(struct eth_device *dev)
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writel(0, &fec->eth->gaddr1);
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writel(0, &fec->eth->gaddr2);
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/*
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* Set physical address
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*/
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/* Set physical address */
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writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
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&fec->eth->paddr1);
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&fec->eth->paddr1);
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writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
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return 0;
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}
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/*
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* Do initial configuration of the FEC registers
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*/
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/* Do initial configuration of the FEC registers */
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static void fec_reg_setup(struct fec_priv *fec)
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{
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uint32_t rcntrl;
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/*
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* Set interrupt mask register
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*/
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/* Set interrupt mask register */
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writel(0x00000000, &fec->eth->imask);
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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/* Clear FEC-Lite interrupt event register(IEVENT) */
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writel(0xffffffff, &fec->eth->ievent);
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/*
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* Set FEC-Lite receive control register(R_CNTRL):
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*/
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/* Set FEC-Lite receive control register(R_CNTRL): */
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/* Start with frame length = 1518, common for all modes. */
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rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
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@ -471,22 +445,19 @@ static int fec_open(struct eth_device *edev)
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#ifdef FEC_QUIRK_ENET_MAC
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/* Enable ENET HW endian SWAP */
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writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
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&fec->eth->ecntrl);
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&fec->eth->ecntrl);
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/* Enable ENET store and forward mode */
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writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
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&fec->eth->x_wmrk);
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&fec->eth->x_wmrk);
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#endif
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/*
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* Enable FEC-Lite controller
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*/
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/* Enable FEC-Lite controller */
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writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
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&fec->eth->ecntrl);
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&fec->eth->ecntrl);
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#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
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udelay(100);
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/*
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* setup the MII gasket for RMII mode
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*/
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/* setup the MII gasket for RMII mode */
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/* disable the gasket */
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writew(0, &fec->eth->miigsk_enr);
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@ -544,9 +515,7 @@ static int fec_open(struct eth_device *edev)
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#endif
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debug("%s:Speed=%i\n", __func__, speed);
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/*
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* Enable SmartDMA receive task
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*/
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/* Enable SmartDMA receive task */
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fec_rx_task_enable(fec);
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udelay(100000);
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@ -556,7 +525,7 @@ static int fec_open(struct eth_device *edev)
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#ifdef CONFIG_DM_ETH
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static int fecmxc_init(struct udevice *dev)
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#else
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static int fec_init(struct eth_device *dev, bd_t* bd)
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static int fec_init(struct eth_device *dev, bd_t *bd)
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#endif
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{
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#ifdef CONFIG_DM_ETH
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@ -574,9 +543,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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fec_set_hwaddr(dev);
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#endif
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/*
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* Setup transmit descriptors, there are two in total.
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*/
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/* Setup transmit descriptors, there are two in total. */
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fec_tbd_init(fec);
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/* Setup receive descriptors. */
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@ -587,18 +554,14 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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if (fec->xcv_type != SEVENWIRE)
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fec_mii_setspeed(fec->bus->priv);
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/*
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* Set Opcode/Pause Duration Register
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*/
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/* Set Opcode/Pause Duration Register */
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writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
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writel(0x2, &fec->eth->x_wmrk);
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/*
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* Set multicast address filter
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*/
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/* Set multicast address filter */
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writel(0x00000000, &fec->eth->gaddr1);
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writel(0x00000000, &fec->eth->gaddr2);
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/* Do not access reserved register for i.MX6UL */
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if (!is_mx6ul()) {
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/* clear MIB RAM */
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@ -639,22 +602,16 @@ static void fec_halt(struct eth_device *dev)
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#endif
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int counter = 0xffff;
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/*
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* issue graceful stop command to the FEC transmitter if necessary
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*/
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/* issue graceful stop command to the FEC transmitter if necessary */
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writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
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&fec->eth->x_cntrl);
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&fec->eth->x_cntrl);
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debug("eth_halt: wait for stop regs\n");
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/*
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* wait for graceful stop to register
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*/
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/* wait for graceful stop to register */
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while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
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udelay(1);
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/*
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* Disable SmartDMA tasks
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*/
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/* Disable SmartDMA tasks */
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fec_tx_task_disable(fec);
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fec_rx_task_disable(fec);
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@ -663,7 +620,7 @@ static void fec_halt(struct eth_device *dev)
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* Note: this will also reset the BD index counter!
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*/
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writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
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&fec->eth->ecntrl);
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&fec->eth->ecntrl);
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fec->rbd_index = 0;
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fec->tbd_index = 0;
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debug("eth_halt: done\n");
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@ -766,9 +723,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
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*/
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readl(addr + size - 4);
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/*
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* Enable SmartDMA transmit task
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*/
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/* Enable SmartDMA transmit task */
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fec_tx_task_enable(fec);
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/*
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@ -813,8 +768,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
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out:
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debug("fec_send: status 0x%x index %d ret %i\n",
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readw(&fec->tbd_base[fec->tbd_index].status),
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fec->tbd_index, ret);
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readw(&fec->tbd_base[fec->tbd_index].status),
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fec->tbd_index, ret);
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/* for next transmission use the other buffer */
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if (fec->tbd_index)
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fec->tbd_index = 0;
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@ -848,9 +803,7 @@ static int fec_recv(struct eth_device *dev)
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int i;
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ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
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/*
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* Check if any critical events have happened
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*/
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/* Check if any critical events have happened */
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ievent = readl(&fec->eth->ievent);
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writel(ievent, &fec->eth->ievent);
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debug("fec_recv: ievent 0x%lx\n", ievent);
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@ -868,7 +821,7 @@ static int fec_recv(struct eth_device *dev)
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if (ievent & FEC_IEVENT_HBERR) {
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/* Heartbeat error */
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writel(0x00000001 | readl(&fec->eth->x_cntrl),
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&fec->eth->x_cntrl);
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&fec->eth->x_cntrl);
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}
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if (ievent & FEC_IEVENT_GRA) {
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/* Graceful stop complete */
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@ -879,7 +832,7 @@ static int fec_recv(struct eth_device *dev)
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fec_halt(dev);
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#endif
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writel(~0x00000001 & readl(&fec->eth->x_cntrl),
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&fec->eth->x_cntrl);
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&fec->eth->x_cntrl);
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#ifdef CONFIG_DM_ETH
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fecmxc_init(dev);
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#else
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@ -911,22 +864,16 @@ static int fec_recv(struct eth_device *dev)
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if (!(bd_status & FEC_RBD_EMPTY)) {
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if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
|
||||
((readw(&rbd->data_length) - 4) > 14)) {
|
||||
/*
|
||||
* Get buffer address and size
|
||||
*/
|
||||
((readw(&rbd->data_length) - 4) > 14)) {
|
||||
/* Get buffer address and size */
|
||||
addr = readl(&rbd->data_pointer);
|
||||
frame_length = readw(&rbd->data_length) - 4;
|
||||
/*
|
||||
* Invalidate data cache over the buffer
|
||||
*/
|
||||
/* Invalidate data cache over the buffer */
|
||||
end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
|
||||
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
||||
invalidate_dcache_range(addr, end);
|
||||
|
||||
/*
|
||||
* Fill the buffer and pass it to upper layers
|
||||
*/
|
||||
/* Fill the buffer and pass it to upper layers */
|
||||
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
|
||||
swap_packet((uint32_t *)addr, frame_length);
|
||||
#endif
|
||||
@ -954,7 +901,7 @@ static int fec_recv(struct eth_device *dev)
|
||||
&fec->rbd_base[i]);
|
||||
}
|
||||
flush_dcache_range(addr,
|
||||
addr + ARCH_DMA_MINALIGN);
|
||||
addr + ARCH_DMA_MINALIGN);
|
||||
}
|
||||
|
||||
fec_rx_task_enable(fec);
|
||||
@ -1273,7 +1220,8 @@ static int fecmxc_probe(struct udevice *dev)
|
||||
goto err_phy;
|
||||
|
||||
/* Reset chip. */
|
||||
writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl);
|
||||
writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
|
||||
&priv->eth->ecntrl);
|
||||
start = get_timer(0);
|
||||
while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
|
||||
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
|
||||
|
||||
@ -14,21 +14,14 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __FEC_MXC_H
|
||||
#define __FEC_MXC_H
|
||||
|
||||
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
|
||||
|
||||
/**
|
||||
* Layout description of the FEC
|
||||
*/
|
||||
/* Layout description of the FEC */
|
||||
struct ethernet_regs {
|
||||
/* [10:2]addr = 00 */
|
||||
|
||||
/* [10:2]addr = 00 */
|
||||
|
||||
/* Control and status Registers (offset 000-1FF) */
|
||||
|
||||
/* Control and status Registers (offset 000-1FF) */
|
||||
uint32_t res0[1]; /* MBAR_ETH + 0x000 */
|
||||
uint32_t ievent; /* MBAR_ETH + 0x004 */
|
||||
uint32_t imask; /* MBAR_ETH + 0x008 */
|
||||
@ -71,8 +64,7 @@ struct ethernet_regs {
|
||||
uint32_t emrbr; /* MBAR_ETH + 0x188 */
|
||||
uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
|
||||
|
||||
/* MIB COUNTERS (Offset 200-2FF) */
|
||||
|
||||
/* MIB COUNTERS (Offset 200-2FF) */
|
||||
uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
|
||||
uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
|
||||
uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
|
||||
@ -174,7 +166,6 @@ struct ethernet_regs {
|
||||
#define FEC_IMASKT_RL 0x00100000
|
||||
#define FEC_IMASK_UN 0x00080000
|
||||
|
||||
|
||||
#define FEC_RCNTRL_MAX_FL_SHIFT 16
|
||||
#define FEC_RCNTRL_LOOP 0x00000001
|
||||
#define FEC_RCNTRL_DRT 0x00000002
|
||||
@ -233,9 +224,7 @@ struct fec_bd {
|
||||
uint32_t data_pointer; /* payload's buffer address */
|
||||
};
|
||||
|
||||
/**
|
||||
* Supported phy types on this platform
|
||||
*/
|
||||
/* Supported phy types on this platform */
|
||||
enum xceiver_type {
|
||||
SEVENWIRE, /* 7-wire */
|
||||
MII10, /* MII 10Mbps */
|
||||
@ -244,9 +233,7 @@ enum xceiver_type {
|
||||
RGMII, /* RGMII */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i.MX27-FEC private structure
|
||||
*/
|
||||
/* @brief i.MX27-FEC private structure */
|
||||
struct fec_priv {
|
||||
struct ethernet_regs *eth; /* pointer to register'S base */
|
||||
enum xceiver_type xcv_type; /* transceiver type */
|
||||
@ -270,6 +257,8 @@ struct fec_priv {
|
||||
#endif
|
||||
};
|
||||
|
||||
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
|
||||
|
||||
/**
|
||||
* @brief Numbers of buffer descriptors for receiving
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user