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arm: mvebu: a38x: Remove unsupported topologies

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A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support.  Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM.  If this needs to be done, it should be
handled in the board file, not in core code.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Kevin Smith 2015-10-23 17:53:19 +00:00 committed by Luka Perkov
parent 3d4825446e
commit 544acb07ec
11 changed files with 16 additions and 1392 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-mvebu/serdes/a38x/Makefile
View File

@ -5,6 +5,5 @@
obj-$(CONFIG_SPL_BUILD) = ctrl_pex.o
obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o
obj-$(CONFIG_SPL_BUILD) += high_speed_topology_spec-38x.o
obj-$(CONFIG_SPL_BUILD) += seq_exec.o
obj-$(CONFIG_SPL_BUILD) += sys_env_lib.o

1
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
View File

@ -5,7 +5,6 @@
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>

26
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
View File

@ -5,14 +5,12 @@
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "high_speed_env_spec.h"
#include "high_speed_topology_spec.h"
#include "sys_env_lib.h"
#include "ctrl_pex.h"
@ -1364,27 +1362,6 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
return seq_id;
}
/*
* This is the weak default function for the Marvell evaluation or
* development boarrds. Like the DB-88F6820-GP and others.
* Custom boards should define this function in their board
* code (board directory). And overwrite this default function
* with this custom specific code.
*/
__weak int hws_board_topology_load(struct serdes_map *serdes_map_array)
{
u32 board_id = mv_board_id_get();
u32 board_id_index = mv_board_id_index_get(board_id);
DEBUG_INIT_FULL_S("\n### hws_board_topology_load ###\n");
/* getting board topology according to the board id */
DEBUG_INIT_FULL_S("Getting board topology according to the board id\n");
CHECK_STATUS(load_topology_func_arr[board_id_index] (serdes_map_array));
return MV_OK;
}
void print_topology_details(struct serdes_map *serdes_map_array)
{
u32 lane_num;
@ -1448,9 +1425,6 @@ int serdes_phy_config(void)
return MV_FAIL;
}
/* I2C init */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/* Board topology load */
DEBUG_INIT_FULL_S
("ctrl_high_speed_serdes_phy_config: Loading board topology..\n");

1009
arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c
View File

File diff suppressed because it is too large Load Diff

124
arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec.h
View File

@ -1,124 +0,0 @@
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _HIGHSPEED_TOPOLOGY_SPEC_H
#define _HIGHSPEED_TOPOLOGY_SPEC_H
#include "high_speed_env_spec.h"
/* Topology map options for the DB_A38X_BP board */
enum topology_config_db {
DB_CONFIG_SLM1363_C,
DB_CONFIG_SLM1363_D,
DB_CONFIG_SLM1363_E,
DB_CONFIG_SLM1363_F,
DB_CONFIG_SLM1364_D,
DB_CONFIG_SLM1364_E,
DB_CONFIG_SLM1364_F,
DB_CONFIG_DEFAULT,
DB_NO_TOPOLOGY
};
/*
* this enum must be aligned with topology_config_db_381 array,
* every update to this enum requires update to topology_config_db_381
* array
*/
enum topology_config_db381 {
DB_CONFIG_SLM1427, /* enum for db_config_slm1427 */
DB_CONFIG_SLM1426, /* enum for db_config_slm1426 */
DB_381_CONFIG_DEFAULT,
DB_381_NO_TOPOLOGY
};
/* A generic function pointer for loading the board topology map */
typedef int (*load_topology_func_ptr)(struct serdes_map *serdes_map_array);
extern load_topology_func_ptr load_topology_func_arr[];
/*
* topology_config_db_mode_get -
*
* DESCRIPTION: Gets the relevant topology mode (index).
* for load_topology_db use only.
* INPUT: None.
* OUTPUT: None.
* RETURNS: the topology mode
*/
u8 topology_config_db_mode_get(void);
/*
* load_topology_xxx -
*
* DESCRIPTION: Loads the board topology for the XXX board
* INPUT: serdes_map_array - The struct that will contain
* the board topology map
* OUTPUT: The board topology map.
* RETURNS: MV_OK for success
* MV_FAIL for failure (a wrong topology mode was read
* from the board)
*/
/* load_topology_db - Loads the board topology for DB Board */
int load_topology_db(struct serdes_map *serdes_map_array);
/* load_topology_rd - Loads the board topology for RD Board */
int load_topology_rd(struct serdes_map *serdes_map_array);
/* load_topology_rd_nas - Loads the board topology for RD NAS Board */
int load_topology_rd_nas(struct serdes_map *serdes_map_array);
/* load_topology_rd_ap - Loads the board topology for RD Ap Board */
int load_topology_rd_ap(struct serdes_map *serdes_map_array);
/* load_topology_db_ap - Loads the board topology for DB-AP Board */
int load_topology_db_ap(struct serdes_map *serdes_map_array);
/* load_topology_db_gp - Loads the board topology for DB GP Board */
int load_topology_db_gp(struct serdes_map *serdes_map_array);
/* load_topology_db_381 - Loads the board topology for 381 DB-BP Board */
int load_topology_db_381(struct serdes_map *serdes_map_array);
/* load_topology_db_amc - Loads the board topology for DB-AMC Board */
int load_topology_db_amc(struct serdes_map *serdes_map_array);
/*
* hws_update_device_toplogy
* DESCRIPTION: Update the default board topology for specific device Id
* INPUT:
* topology_config_ptr - pointer to the Serdes mapping
* topology_mode - topology mode (index)
* OUTPUT: None
* RRETURNS:
* MV_OK - if updating the board topology success
* MV_BAD_PARAM - if the input parameter is wrong
*/
int hws_update_device_toplogy(struct serdes_map *topology_config_ptr,
enum topology_config_db topology_mode);
/*
* load_topology_rd_sgmii_usb -
*
* DESCRIPTION: For RD board check if lane 4 is USB3 or SGMII
* INPUT: None
* OUTPUT: is_sgmii - return 1 if lane 4 is SGMII
* return 0 if lane 4 is USB.
* RETURNS: MV_OK for success
*/
int load_topology_rd_sgmii_usb(int *is_sgmii);
/*
* load_topology_usb_mode_get -
*
* DESCRIPTION: For DB board check if USB3.0 mode
* INPUT: None
* OUTPUT: twsi_data - return data read from S@R via I2C
* RETURNS: MV_OK for success
*/
int load_topology_usb_mode_get(u8 *twsi_data);
#endif /* _HIGHSPEED_TOPOLOGY_SPEC_H */

1
arch/arm/mach-mvebu/serdes/a38x/seq_exec.c
View File

@ -5,7 +5,6 @@
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>

151
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
View File

@ -5,7 +5,6 @@
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
@ -236,153 +235,3 @@ u32 sys_env_device_id_get(void)
return g_dev_id;
}
#ifdef MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI
/*
* sys_env_get_topology_update_info
* DESCRIPTION: Read TWSI fields to update DDR topology structure
* INPUT: None
* OUTPUT: None, 0 means no topology update
* RETURN:
* Bit mask of changes topology features
*/
#ifdef CONFIG_ARMADA_39X
u32 sys_env_get_topology_update_info(
struct topology_update_info *tui)
{
/* Set 16/32 bit configuration*/
tui->update_width = 1;
tui->width = TOPOLOGY_UPDATE_WIDTH_32BIT;
#ifdef CONFIG_DDR3
if (1 == sys_env_config_get(MV_CONFIG_DDR_BUSWIDTH)) {
/* 16bit */
tui->width = TOPOLOGY_UPDATE_WIDTH_16BIT;
} else {
/* 32bit */
tui->width = TOPOLOGY_UPDATE_WIDTH_32BIT;
}
#endif
/* Set ECC/no ECC bit configuration */
tui->update_ecc = 1;
if (0 == sys_env_config_get(MV_CONFIG_DDR_ECC_EN)) {
/* NO ECC */
tui->ecc = TOPOLOGY_UPDATE_ECC_OFF;
} else {
/* ECC */
tui->ecc = TOPOLOGY_UPDATE_ECC_ON;
}
tui->update_ecc_pup3_mode = 1;
tui->ecc_pup_mode_offset = TOPOLOGY_UPDATE_ECC_OFFSET_PUP4;
return MV_OK;
}
#else /*CONFIG_ARMADA_38X*/
u32 sys_env_get_topology_update_info(
struct topology_update_info *tui)
{
u8 config_val;
u8 ecc_mode[A38X_MV_MAX_MARVELL_BOARD_ID -
A38X_MARVELL_BOARD_ID_BASE][5] = TOPOLOGY_UPDATE;
u8 board_id = mv_board_id_get();
int ret;
board_id = mv_board_id_index_get(board_id);
ret = i2c_read(EEPROM_I2C_ADDR, 0, 2, &config_val, 1);
if (ret) {
DEBUG_INIT_S("sys_env_get_topology_update_info: TWSI Read failed\n");
return 0;
}
/* Set 16/32 bit configuration */
if ((0 == (config_val & DDR_SATR_CONFIG_MASK_WIDTH)) ||
(ecc_mode[board_id][TOPOLOGY_UPDATE_32BIT] == 0)) {
/* 16bit by SatR of 32bit mode not supported for the board */
if ((ecc_mode[board_id][TOPOLOGY_UPDATE_16BIT] != 0)) {
tui->update_width = 1;
tui->width = TOPOLOGY_UPDATE_WIDTH_16BIT;
}
} else {
/* 32bit */
if ((ecc_mode[board_id][TOPOLOGY_UPDATE_32BIT] != 0)) {
tui->update_width = 1;
tui->width = TOPOLOGY_UPDATE_WIDTH_32BIT;
}
}
/* Set ECC/no ECC bit configuration */
if (0 == (config_val & DDR_SATR_CONFIG_MASK_ECC)) {
/* NO ECC */
tui->update_ecc = 1;
tui->ecc = TOPOLOGY_UPDATE_ECC_OFF;
} else {
/* ECC */
if ((ecc_mode[board_id][TOPOLOGY_UPDATE_32BIT_ECC] != 0) ||
(ecc_mode[board_id][TOPOLOGY_UPDATE_16BIT_ECC] != 0) ||
(ecc_mode[board_id][TOPOLOGY_UPDATE_16BIT_ECC_PUP3] != 0)) {
tui->update_ecc = 1;
tui->ecc = TOPOLOGY_UPDATE_ECC_ON;
}
}
/* Set ECC pup bit configuration */
if (0 == (config_val & DDR_SATR_CONFIG_MASK_ECC_PUP)) {
/* PUP3 */
/*
* Check if PUP3 configuration allowed, if not -
* force Pup4 with warning message
*/
if ((ecc_mode[board_id][TOPOLOGY_UPDATE_16BIT_ECC_PUP3] != 0)) {
if (tui->width == TOPOLOGY_UPDATE_WIDTH_16BIT) {
tui->update_ecc_pup3_mode = 1;
tui->ecc_pup_mode_offset =
TOPOLOGY_UPDATE_ECC_OFFSET_PUP3;
} else {
if ((ecc_mode[board_id][TOPOLOGY_UPDATE_32BIT_ECC] != 0)) {
printf("DDR Topology Update: ECC PUP3 not valid for 32bit mode, force ECC in PUP4\n");
tui->update_ecc_pup3_mode = 1;
tui->ecc_pup_mode_offset =
TOPOLOGY_UPDATE_ECC_OFFSET_PUP4;
}
}
} else {
if (ecc_mode[board_id][TOPOLOGY_UPDATE_16BIT_ECC] !=
0) {
printf("DDR Topology Update: ECC on PUP3 not supported, force ECC on PUP4\n");
tui->update_ecc_pup3_mode = 1;
tui->ecc_pup_mode_offset =
TOPOLOGY_UPDATE_ECC_OFFSET_PUP4;
}
}
} else {
/* PUP4 */
if ((ecc_mode[board_id][TOPOLOGY_UPDATE_32BIT_ECC] != 0) ||
(ecc_mode[board_id][TOPOLOGY_UPDATE_16BIT_ECC] != 0)) {
tui->update_ecc_pup3_mode = 1;
tui->ecc_pup_mode_offset =
TOPOLOGY_UPDATE_ECC_OFFSET_PUP4;
}
}
/*
* Check for forbidden ECC mode,
* if by default width and pup selection set 32bit ECC mode and this
* mode not supported for the board - config 16bit with ECC on PUP3
*/
if ((tui->ecc == TOPOLOGY_UPDATE_ECC_ON) &&
(tui->width == TOPOLOGY_UPDATE_WIDTH_32BIT)) {
if (ecc_mode[board_id][TOPOLOGY_UPDATE_32BIT_ECC] == 0) {
printf("DDR Topology Update: 32bit mode with ECC not allowed on this board, forced 16bit with ECC on PUP3\n");
tui->width = TOPOLOGY_UPDATE_WIDTH_16BIT;
tui->update_ecc_pup3_mode = 1;
tui->ecc_pup_mode_offset =
TOPOLOGY_UPDATE_ECC_OFFSET_PUP3;
}
}
return MV_OK;
}
#endif /* CONFIG_ARMADA_38X */
#endif /* MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI */

2
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
View File

@ -364,8 +364,6 @@ u8 sys_env_device_rev_get(void);
u32 sys_env_device_id_get(void);
u16 sys_env_model_get(void);
struct dlb_config *sys_env_dlb_config_ptr_get(void);
u32 sys_env_get_topology_update_info(
struct topology_update_info *topology_update_info);
u32 sys_env_get_cs_ena_from_reg(void);
#endif /* _SYS_ENV_LIB_H */

16
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
View File

@ -13,6 +13,7 @@
#include <asm/arch/soc.h>
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
@ -55,6 +56,21 @@ static struct marvell_io_exp io_exp[] = {
{ 0x21, 3, 0xC0 } /* Output Data, register#1 */
};
static struct serdes_map board_serdes_map[] = {
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
{SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
{SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
};
int hws_board_topology_load(struct serdes_map *serdes_map_array)
{
memcpy(serdes_map_array, board_serdes_map, sizeof(board_serdes_map));
return 0;
}
/*
* Define the DDR layout / topology here in the board file. This will
* be used by the DDR3 init code in the SPL U-Boot version to configure

5
drivers/ddr/marvell/a38x/ddr3_a38x.h
View File

@ -12,11 +12,6 @@
#include "ddr3_hws_hw_training_def.h"
/* Allow topolgy update from board TWSI device*/
#if !defined(CONFIG_CUSTOMER_BOARD_SUPPORT)
#define MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI
#endif
#define ECC_SUPPORT
/* right now, we're not supporting this in mainline */

72
drivers/ddr/marvell/a38x/ddr3_init.c
View File

@ -96,7 +96,6 @@ u8 generic_init_controller = 1;
static u32 ddr3_get_static_ddr_mode(void);
#endif
static int ddr3_hws_tune_training_params(u8 dev_num);
static int ddr3_update_topology_map(struct hws_topology_map *topology_map);
/* device revision */
#define DEV_VERSION_ID_REG 0x1823c
@ -383,14 +382,6 @@ int ddr3_init(void)
}
#endif
/* Load topology for New Training IP */
status = ddr3_load_topology_map();
if (MV_OK != status) {
printf("%s Training Sequence topology load - FAILED\n",
ddr_type);
return status;
}
/* Tune training algo paramteres */
status = ddr3_hws_tune_training_params(0);
if (MV_OK != status)
@ -539,27 +530,6 @@ u32 ddr3_get_cs_num_from_reg(void)
return cs_count;
}
/*
* Name: ddr3_load_topology_map
* Desc:
* Args:
* Notes:
* Returns:
*/
int ddr3_load_topology_map(void)
{
struct hws_topology_map *tm = ddr3_get_topology_map();
#if defined(MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI)
/* Update topology data */
if (MV_OK != ddr3_update_topology_map(tm)) {
DEBUG_INIT_FULL_S("Failed update of DDR3 Topology map\n");
}
#endif
return MV_OK;
}
void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
{
u32 tmp, hclk = 200;
@ -781,48 +751,6 @@ int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
return MV_OK;
}
#if defined(MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI)
/*
* Name: ddr3_update_topology_map
* Desc:
* Args:
* Notes: Update topology map by Sat_r values
* Returns:
*/
static int ddr3_update_topology_map(struct hws_topology_map *tm)
{
struct topology_update_info topology_update_info;
topology_update_info.update_width = 0;
topology_update_info.update_ecc = 0;
topology_update_info.update_ecc_pup3_mode = 0;
sys_env_get_topology_update_info(&topology_update_info);
if (topology_update_info.update_width) {
tm->bus_act_mask &=
~(TOPOLOGY_UPDATE_WIDTH_32BIT_MASK);
if (topology_update_info.width == TOPOLOGY_UPDATE_WIDTH_16BIT)
tm->bus_act_mask =
TOPOLOGY_UPDATE_WIDTH_16BIT_MASK;
else
tm->bus_act_mask =
TOPOLOGY_UPDATE_WIDTH_32BIT_MASK;
}
if (topology_update_info.update_ecc) {
if (topology_update_info.ecc == TOPOLOGY_UPDATE_ECC_OFF) {
tm->bus_act_mask &=
~(1 << topology_update_info.ecc_pup_mode_offset);
} else {
tm->bus_act_mask |=
topology_update_info.
ecc << topology_update_info.ecc_pup_mode_offset;
}
}
return MV_OK;
}
#endif
/*
* Name: ddr3_hws_tune_training_params
* Desc: