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ARM: DRA7: Update DDR IO registers
Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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@ -592,11 +592,11 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
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.ctrl_ddrch = 0x40404040,
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.ctrl_ddrch = 0x40404040,
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.ctrl_lpddr2ch = 0x40404040,
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.ctrl_lpddr2ch = 0x40404040,
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.ctrl_ddr3ch = 0x80808080,
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.ctrl_ddr3ch = 0x80808080,
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.ctrl_ddrio_0 = 0xA2084210,
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.ctrl_ddrio_0 = 0x00094A40,
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.ctrl_ddrio_1 = 0x84210840,
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.ctrl_ddrio_1 = 0x04A52000,
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.ctrl_ddrio_2 = 0x84210000,
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.ctrl_ddrio_2 = 0x84210000,
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.ctrl_emif_sdram_config_ext = 0x0001C1A7,
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.ctrl_emif_sdram_config_ext = 0x0001C127,
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.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
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.ctrl_emif_sdram_config_ext_final = 0x0001C127,
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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};
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};
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@ -604,11 +604,11 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
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.ctrl_ddrch = 0x40404040,
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.ctrl_ddrch = 0x40404040,
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.ctrl_lpddr2ch = 0x40404040,
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.ctrl_lpddr2ch = 0x40404040,
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.ctrl_ddr3ch = 0x60606080,
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.ctrl_ddr3ch = 0x60606080,
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.ctrl_ddrio_0 = 0xA2084210,
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.ctrl_ddrio_0 = 0x00094A40,
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.ctrl_ddrio_1 = 0x84210840,
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.ctrl_ddrio_1 = 0x04A52000,
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.ctrl_ddrio_2 = 0x84210000,
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.ctrl_ddrio_2 = 0x84210000,
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.ctrl_emif_sdram_config_ext = 0x0001C1A7,
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.ctrl_emif_sdram_config_ext = 0x0001C127,
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.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
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.ctrl_emif_sdram_config_ext_final = 0x0001C127,
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
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};
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};
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