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armv8: layerscape: Add TFABOOT support
Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB
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help
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For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
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pins, select it when the pins are assigned to USB.
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config TFABOOT
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bool "Support for booting from TFA"
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default n
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help
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Enabling this will make a U-Boot binary that is capable of being
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booted via TFA.
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@ -88,7 +88,8 @@ static struct mm_region early_map[] = {
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#endif
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1,
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_TFABOOT) || \
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(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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@ -139,7 +140,8 @@ static struct mm_region early_map[] = {
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#endif
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1,
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_TFABOOT) || \
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(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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@ -1236,7 +1238,8 @@ void update_early_mmu_table(void)
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__weak int dram_init(void)
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{
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fsl_initdram();
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
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defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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#endif
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